經濟部中央標率局貝工消費合作社印掣 A7 B7 五、發明说明（1) 本發明係大致有關於非依電性記憶體，且更特別地有 關於電氣可抹除之非依電性記憶體。 非依電性記億體晶胞爲有利的，原因在於就算至記憶 體之電力被切斷，其仍保留被記錄之資訊。其有數種不同 型式之非依電性記憶體，包括可抹除的可程式唯讀記憶體 (EPROM )、電氣可抹除的可程式唯讀記憶體（EEPROM)與閃 EEPR0M記憶體。EPROM爲藉由光線曝現而爲可抹除的，但 可藉由在浮動閘上之槽溝電子注入而爲可電氣式程式化 的。慣用的EEPROM具有相同的程式化功能，但代之以被光 線抹除的是其可被電子隧穿抹除及程式化。因而，資訊可 被儲存於這些記憶體中，而當電力切斷時被保留，且這些 記憶體可用適當的技術在必要時被抹除以便再程式化。閃 EEPROM以塊被抹除，典型地比普通的EEPROM給予其較佳 的讀入存取時間。 目前，閃記憶體已獲得相當的普遍性。例如，閃記憶 體經常被用於微控制器、數據機與智慧卡之類可能需要快 速更新儲存碼的晶片上記憶體。 雖然閃記憶體與EEPROM爲緊密相關的，在許多實例中 閃記憶體爲較佳的，因其較小的晶胞大小意即其可更經濟 地被製造。然而，閃記憶體與EEPROM常非類似的晶胞屬 性。 .· .......... _ ...... 」 __ 當EEPROM被抹除時，一個或以上之晶胞在一次作業中 被抹除。高的正電位被施加至晶胞源極與（或）汲極。而控 制電極與基底被接地。其結果爲，在浮動閘上之負充電被 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ϋ HI I - i^i ......I - -I - i -- .....I— · -- - 1— - -- - 1 - ! - -- X» I m----n HI n - i (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消费合作社印製 A7 _B7 ._^___ 五、發明説明（2)The Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives printed A7 B7 V. Description of the invention (1) The present invention relates generally to non-dependent memory, and more particularly to electrically erasable non-dependent memory body. It is advantageous to record the billion-unit cell in a non-electrical manner, because even if the power to the memory is cut off, it still retains the recorded information. There are several different types of non-electrical memory, including erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash EEPR0M memory. EPROM is erasable by light exposure, but can be electrically programmed by slot electron injection on the floating gate. The conventional EEPROM has the same programming function, but instead it can be erased and programmed by electron tunneling instead. Thus, information can be stored in these memories and retained when the power is turned off, and these memories can be erased for reprogramming using appropriate techniques if necessary. Flash EEPROMs are erased in blocks, typically giving them better read access times than ordinary EEPROMs. Currently, flash memory has gained considerable popularity. For example, flash memory is often used for on-chip memory such as microcontrollers, modems, and smart cards that may require quick updates of stored codes. Although flash memory is closely related to EEPROM, flash memory is preferred in many instances because its smaller cell size means that it can be manufactured more economically. However, flash memory and EEPROM are often not of similar cell nature. .. .......... _ ...... '' __ When the EEPROM is erased, one or more unit cells are erased in one operation. A high positive potential is applied to the unit cell source and / or drain. The control electrode and the substrate are grounded. As a result, the negative charge on the floating gate is applied to the Chinese national standard (CNS) A4 specification (210X297 mm) by this paper size. Ϋ HI I-i ^ i ...... I--I-i- ..... I— ·--1—---1-!--X »I m ---- n HI n-i (Please read the notes on the back before filling this page) Economy Printed by A7 _B7 ._ ^ ___ of the Central Standards Bureau ’s Consumer Cooperatives V. Invention Description (2)
Fowler-Nordheim隱穿拉至源極與（或）汲極區。此技術在 浮動閘電極與源極與（或）汲極區間之介質非常薄之處爲有 效的。 慣用的抹除技術會發生數個缺點，包括其在源極與（或） 汲極與基底接頭間創造逆電壓停頓可能性之事實 '，其將造 成在氧化物中熱孔陷阱與可靠性之問題，如1988年IEEE Electron. Device Letters 第 9 卷第 588-590 頁由 Clii Chang 等人之 “Drain Avalanche.and Hole Trapping Induced Gate Leakage in Thin Oxide MOS Devices”文章所述。爲克服 此點，某些設If者曾使用所謂的雙重擴散接頭以強化接頭 基底停頓電壓。然而，該雙重擴散接頭具有某些缺點，包 括：（1)其可能須有額外晶胞尺寸之事實而降低電位晶胞密 度，（2)其仍然具有 Gate Induced Drain Leakage(GIDL) 電流。另一個可能的辦法爲在控制閘使用相當高的負電 位，因而有較少的電壓被施加於源極。如Sameer S. Hadda.d 等人在美國專利第5,077,691號，標題爲“FI ash EEPROM Array with Negative Gate Voltage Erase Operation” 所述。此則會降低橫過源極至基底接頭之場。 然而，當槽溝長度變小時，此孔陷阱變成與槽溝長度 相依。此效應已被描述爲可能的“對閃記憶體晶胞之依比率 決定之基本限制”。如 1995 年 IEDM-331，13.6.1-13.6.4 Jian Chen 等人在“Short Channel Enhanced Degradation During Discharge of Flash EEPROM Memory Cell”文章所 述。此文章表示，在放電應力之際，由波帶至波帶隧穿所 本紙張尺度適用中囷國家標準（CNS ) A4規格（210X297公釐） I II I I I I I I I I I I I I 訂— I I —— I |象 --- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消费合作社印聚 A7 B7 ·_ 五、發明说明（3) 產生之孔在整個矽對矽二氧化物介面移動，被強烈的側電 場加速，並獲得足夠的能量而變成活躍的熱孔。此文章解 釋負的閘電壓將這些活躍的熱孔拉至該閘，致使其衝擊表 面，被陷住並造成介面狀態。當槽溝長度減小時，側場提 高而增劇該效應》 此文章建議該問題可藉由增加槽溝長度加以避免。由 於此辦法係與依比率決定裝置，以逐漸越來越小尺寸來形 成較小維度、較低成本產品的產業長期間趨勢相抵觸，此 辦法並非特別所要的。Chen等人對此問題的建議爲對該汲 極施加正偏置f使該晶胞由汲極波節放電。雖然在文章中 之討論結果此確實會將問題改進到某種程度，某些品質惡 化在就算此方法被使用仍呈現會保持著》 其亦曾經建議使用以大負電壓被施加至控制閘及五伏 特之電壓被施加至P井與N井之槽溝抹除，會因靠近源極 區之熱孔產生降低，而可能改進閛干擾容差與可靠性。請 參閱 1992 年 11 月 IEEE Journal of Sold-State Circuits 期刊第27卷第11期第1 547- 1 554頁，T. Jinbo等人之“A 5-V-0nly 16-Mb Flash. Memory with Sector Erase Mode” 文章。此需有比汲極抹除情況高1/3之負閘電壓（Haddad 等人之第5,077,691號專利）。請參閱1993年5月日本IEEE VLSI技術硏討會論文集第81 ·2頁，Hsiang-Jen Wan等人 之 “Suppressing FI.ash EEPROM Erase Leakage with Negative Gate Bias and LDD Erase Junction”文章。 本發明之發明人相信，這些方法沒有一個是完全滿意 本紙張尺度適用中困困家揉隼（C»S ) A4規格（210X297公釐） ---------裝------訂------0 . J 一 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明（4) 的，且對有效的、可依比率決定的抹除機構有持續的需求。 因而，雖然熟習此技藝者已瞭解由使用有關EEPROM抹除週 期中之負控制閘電位可發生數個益處，各式的缺失已使追 求這些益處之熟習此技藝者感到受挫折》 依照本發明之一層面，一非依電性記億體晶胞被形成 於一 P型區內》該記憶體晶胞亦包括電晶體，具有一浮動 閘與一控制閘及一對被摻雜區作用成形成於該P型區內之 一源極與一汲極。該浮動閘以申浮動閘至該等被摻雜區之 一的電子隧穿而爲可抹除的。該P型區與該等被摻雜區之 一分別被正電g偏置。該被摻雜區_置與該P型區電位間 之差小於Vcc大於0，該控制閘以負壓被偏置。 依照本發明還有之另一層面，一種方法用於抹除具有 一控制閘、一浮動閘、一槽溝與一對被摻雜區作用成形成 於P井之一源極與一汲極再形成於一 N井內，包括將該控 制閘以負壓Μ置之步驟。該P井與該等被摻雜區之一以正 壓被偏置，使得該被摻雜區偏置減Ρ并偏置小於Vcc且大 於0。 第1圖爲一實施例之晶胞構造的圖形顯示；以及 第2圖爲另一實施例之晶胞構造的圖形顯示》 參照附圖，其中相同的字元在全部數個圖中被用於相 同的部位。第1圖顯示之記億體晶胞10包括一控制閘12 與浮動閘14。此構造被有益地實施於半導體層30,其上 置有電氣絕緣之浮動閘14»然而，此特殊晶胞構造並非關 鍵的，且本發明可使用各式的記憶體晶胞構造被實施，例 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） » 裝 II 11 — 象 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 • A7 ·. ·，._ B7___ 五、發明説明（5) 如分離閘與叠閘晶胞構造即是。 可以是爲一 P型半導體之基底30包括重摻雜之源極區 16與重摻雜之汲極區18»區域16與18亦可包括輕摻雜排 極（LDD)突伸物（未畫出）。汲極偏置電位24、基底極偏置 電位26、汲極電位20與閘偏置電位36可被調整以使晶胞 之績效達到最大》 晶胞10可使用任何已知技術被讀取與程式化》在第1 圓顯示之偏置電位係用以實施如箭頭“e”所示之由浮動閘 14主要至汲極18的Fowler-Nordheim電子險穿。 在抹除之際，控制閘1 2被強迫以源極20浮動或以等Fowler-Nordheim is pulled through to the source and / or drain regions. This technique is effective where the dielectric between the floating gate electrode and the source and / or drain electrodes is very thin. There are several disadvantages to the conventional erasing technique, including the fact that it creates the possibility of reverse voltage stalls between the source and / or drain and substrate junctions', which will cause hot hole traps and reliability in oxides. The problem is described in the "Drain Avalanche. And Hole Trapping Induced Gate Leakage in Thin Oxide MOS Devices" article by Clii Chang et al., 1988 IEEE Electron. Device Letters Volume 9, pages 588-590. To overcome this, some designers have used so-called double-diffusion joints to strengthen the joint base stop voltage. However, this double diffusion joint has certain disadvantages, including: (1) the fact that it may require additional cell size to reduce the potential cell density, and (2) it still has Gate Induced Drain Leakage (GIDL) current. Another possible solution is to use a relatively high negative potential at the control gate so that less voltage is applied to the source. As described by Sameer S. Hadda.d et al. In U.S. Patent No. 5,077,691, entitled "FI ash EEPROM Array with Negative Gate Voltage Erase Operation". This reduces the field across the source-to-substrate junction. However, as the slot length becomes smaller, the hole trap becomes dependent on the slot length. This effect has been described as a possible "basic limit on the ratio of flash memory cells". As described in 1995 IEDM-331, 13.6.1-13.6.4 Jian Chen et al. In "Short Channel Enhanced Degradation During Discharge of Flash EEPROM Memory Cell". This article indicates that in the case of discharge stress, the paper size from the waveband to the waveband tunneling is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) I II III III III III Order — II — I | Elephant — -(Please read the notes on the back before filling out this page) Printed Poly A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs · _ 5. Description of the invention (3) The generated holes move across the silicon-to-silicon dioxide interface , Is accelerated by a strong side electric field, and obtains enough energy to become an active hot hole. This article explains that a negative gate voltage pulls these active hot holes to the gate, causing it to hit the surface, trapping it, and causing an interface state. When the slot length decreases, the side field increases and the effect is exacerbated. "This article suggests that this problem can be avoided by increasing the slot length. Since this method is in conflict with the long-term industry trend of deciding the device according to the ratio to gradually reduce the size to form smaller dimensions and lower cost products, this method is not particularly necessary. Chen et al.'S suggestion for this problem is to apply a positive bias f to the drain to discharge the unit cell from the drain node. Although the results of the discussion in this article will indeed improve the problem to some extent, some quality deterioration will remain even if this method is used. It has also been suggested to use a large negative voltage to be applied to the control gate and five The voltage of volts that is applied to the trenches of wells P and N will be erased, which will reduce the thermal holes near the source region, which may improve the interference tolerance and reliability of chirp. Please refer to "A 5-V-0nly 16-Mb Flash. Memory with Sector Erase" by T. Jinbo et al., November 1992, Vol. 27, No. 11, page 1 547-1 554, IEEE Journal of Sold-State Circuits. Mode "article. This requires a negative gate voltage that is 1/3 higher than the drain erase situation (Haddad et al. Patent No. 5,077,691). See May 1993, Proceedings of the IEEE VLSI Technology Symposium, page 81 · 2, "Suppressing FI.ash EEPROM Erase Leakage with Negative Gate Bias and LDD Erase Junction" by Hsiang-Jen Wan et al. The inventor of the present invention believes that none of these methods is completely satisfied with the paper size application (C »S) A4 specification (210X297 mm) --------- installation ---- --Order ------ 0. J I (Please read the notes on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 B7 V. Description of the invention (4) There is a continuing need for effective, ratio-determinable erasure agencies. Thus, although those skilled in the art have learned that there are several benefits that can occur from using negatively controlled gate potentials in the erasing cycle associated with EEPROM, the absence of various types has frustrated those skilled in the art who are pursuing these benefits. On the one level, a non-electrically-characterized unit cell is formed in a P-type region. The memory cell also includes a transistor, which has a floating gate, a control gate, and a pair of doped regions. A source and a drain in the P-type region. The floating gate is erasable by applying an electron tunnel from the floating gate to one of the doped regions. The P-type region and one of the doped regions are each biased by a positive electric g. The difference between the potential of the doped region and the P-type region is less than Vcc and greater than 0, and the control gate is biased with a negative voltage. According to yet another aspect of the present invention, a method for erasing a control gate, a floating gate, a trench and a pair of doped regions to form a source and a drain of a P-well is performed. Formed in an N well, including the step of placing the control gate at a negative pressure M. The P-well and one of the doped regions are biased at a positive pressure such that the doped region is biased minus P and the bias is less than Vcc and greater than zero. FIG. 1 is a graphic display of a cell structure of one embodiment; and FIG. 2 is a graphic display of a cell structure of another embodiment. Referring to the drawings, the same characters are used in all the figures Same place. FIG. 1 shows that the billion cell unit 10 includes a control gate 12 and a floating gate 14. This structure is beneficially implemented on the semiconductor layer 30 with an electrically insulated floating gate 14 thereon. However, this particular cell structure is not critical, and the present invention can be implemented using a variety of memory cell structures. This paper size applies to China National Standard (CNS) A4 (210X297 mm) »Packing II 11 — Elephant (Please read the notes on the back before filling this page) Printed by the Shell Standard Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs • A7 ··· ， ._ B7___ V. Description of the invention (5) Such as the structure of the separation cell and the stacked cell. The substrate 30, which may be a P-type semiconductor, includes heavily doped source regions 16 and heavily doped drain regions 18 »regions 16 and 18 may also include lightly doped drain (LDD) protrusions (not shown) Out). The drain bias potential 24, the base bias potential 26, the drain potential 20 and the gate bias potential 36 can be adjusted to maximize the performance of the cell. The cell 10 can be read and programmed using any known technique. The bias potential shown in the first circle is used to implement the Fowler-Nordheim electronic breakdown from the floating gate 14 to the drain 18 as shown by the arrow "e". At the time of erasure, the control gate 12 is forced to float with the source 20 or wait
I 於P井電位之電位成爲例如-7至-14伏特之負電壓。藉由 維持控制閘偏置在-11伏特以下，用於形成晶胞之處理可 被做得與標準邏輯處理相容。 就汲極擴散18與基底30而言，其被偏置至接近Vcc 或更高之正電位。Vcc被所運用之特殊技術加以決定。以 目前的技術其例如爲5.0至2.5伏特。此降低穿過N+擴散 18與基底30間接頭之電場。降低的GIDL電流與側電場防 止在浮動閘14下方閘氧化物中熱孔陷阱之加速。 汲極18較佳地未被偏置到高於基底30之電壓至閘引 發汲極洩漏（GIDL)會成問題之程度》在現行技術下，此意 即汲極18偏置有益地不高於基底30偏置一到二伏特。見 1992 年 IEEE Transactions on Electron Devices 第 39 卷第 1694-1703 頁’Parke 等人之 “Design for Suppression of Gate-Induced Drain Leakage in LDD MOSFETs Using a 本纸張尺度適用中國國家標半（cns ) A4洗格（210x297公釐） ----------^------ΐτ---^----it 一 - (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標率局男工消费合作社印製 AT ， ’ B7 五、發明説明（6)The potential of I at the potential of P well becomes a negative voltage of, for example, -7 to -14 volts. By maintaining the control gate bias below -11 volts, the process used to form the unit cell can be made compatible with standard logic processes. With regard to the drain diffusion 18 and the substrate 30, they are biased to a positive potential near Vcc or higher. Vcc is determined by the special technology used. With current technology it is, for example, 5.0 to 2.5 volts. This reduces the electric field across the junction between the N + diffusion 18 and the substrate 30. The reduced GIDL current and side electric field prevent the acceleration of hot hole traps in the gate oxide below the floating gate 14. The drain 18 is preferably not biased to a voltage higher than the substrate 30 to the extent that the gate-induced drain leakage (GIDL) can be a problem. In current technology, this means that the drain 18 bias is beneficially no higher than The substrate 30 is offset by one to two volts. See 1992 IEEE Transactions on Electron Devices, Vol. 39, 1694-1703, “Design for Suppression of Gate-Induced Drain Leakage in LDD MOSFETs Using a Parke et al.” This paper is applicable to China National Standard Half (cns) A4 washing Grid (210x297 mm) ---------- ^ ------ ΐτ --- ^ ---- it I-(Please read the notes on the back before filling this page) Ministry of Economy Central Standards Bureau Prints AT for Male Workers 'Cooperatives,' B7 V. Description of Invention (6)
Quasi-two-dimonsional Analytical Model”文章。此外， 若汲極半導體偏置顯著地超過基底30偏置，熱孔陷阱可能 因側接頭場加速而發生。一般而言，較佳的是汲極18偏置 減基底30偏置爲大於0且小於Vcc » 施加正電壓至基底30之能力因P井30係被埋於N井 32內而提高》P井電壓26較佳地等於或小於N井電壓28 以避免P井/N井向前偏置。因此，施加Vcc或更高之正 電壓至P井30, N井32與汲極18可消除被GIDL所引發 之熱孔陷阱，而又允許汲極18電壓提高至Vcc或更高。 源極電位20可被允許來浮動。較佳的是，汲極偏置減P井 偏置爲大於0且小於Vcc» 通過電容器33之電壓一方面爲浮動閘14電位與擴散 18及P井30電位之差。當此差超過8至10伏特時，足夠 的電流被產生，且浮動閘14可在幾個百分之一秒的時框內 被抹除爲負電位，其視隧穿氧化物42之厚度而定。 電子隧穿至汲極區18(汲極抹除）。隧穿電流隨浮動閘 14至汲極18之電壓而定。然而，藉由以就汲極18所顯示 之方式偏置源極16下，源極偏置機構可被提供以取代汲極 偏置機構。在源極抹除之際，汲極電位可被允許浮動。 晶胞10與10a可使用如二層、單金屬CMOS處理之慣 用處理技術被形成。此處設立之說明性參數計畫做出具有 1 .8伏特之Vcc電位的〇.3 5pm或更低的形狀大小。若技術 上允許降低的電壓與較小的形狀尺寸，此處之參數可隨之 依比例改變》 本紙張尺度逋用中國國家標準（CNS ) Α4規格（210Χ 297公釐） ---------裝------訂------象 . - (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標率局貝工消费合作社印簟 A7 B7 五、發明説明（7) 起始的基底材料可典型地爲p型（100)矽’例如具有10 -20ohm· cm之電阻範圍。P井30被埋入於以所謂三重井處 理的N并32中。P井30典型上具有之井深度例如爲3至 4μπι，而具有例如每立方公分ΙχΙΟ16至5χ1016原子範圍之 摻雜濃度。 Ν井32典型上具有4·8μιη之井深度。摻雜濃度可由每 立方公分4χ1〇15至lxl〇16個原子。三重井係藉由將Ρ井 30反摻雜N井32而形成。 三重井之元件的形成如下列所述。N井植入例如以每 平方公分1.0至1.5χ1〇13原子典型用量之磷P31與以160 1 kev至約lOOkev之能量被完成。N井植入使用典型上6至 12小時之1125至1150°C的高混步驟被驅動。然後N井32 以P井植入被逆摻雜。P井植入之典型用量爲平方公分1.5 13 至2.5x10 原子以30kev至180fcev使用硼B11作爲種源。 此將該等井設定爲所要的摻雜濃度與深度。 在井形成後，隨後使用標準邏輯場處理之場氧化物形 成與場隔離。場氧化物厚度與場摻雜可稍微被調整以滿足 晶胞程式化要求。此後，記憶體晶胞植入可後實施。例如 以30至50kev每平方公分1.0至3.5χ1013原子用童之B11 植入可經由亂撥氧化物被做成。例如，85至100埃之乾氧 化物可在整個晶圖被成長。乾氧化物係例如以900°C在部 分氧氣後隨以975至1050°C退火被成長》Quasi-two-dimonsional Analytical Model "article. In addition, if the drain semiconductor bias significantly exceeds the substrate 30 bias, hot hole traps may occur due to the side-joint field acceleration. In general, the drain 18 bias is preferred Decrease the offset of the substrate 30 to be greater than 0 and less than Vcc To avoid forward bias of wells P / N. Therefore, applying a positive voltage of Vcc or higher to P well 30, N well 32 and drain 18 can eliminate hot hole traps caused by GIDL while allowing drain 18 voltage is increased to Vcc or higher. Source potential 20 may be allowed to float. Preferably, the drain bias minus P well bias is greater than 0 and less than Vcc »The voltage through capacitor 33 is a floating gate on the one hand The difference between the potential of 14 and the potential of diffusion 18 and P well 30. When the difference exceeds 8 to 10 volts, sufficient current is generated, and the floating gate 14 can be erased in the frame of a few hundredths of a second as Negative potential, depending on the thickness of the tunneling oxide 42. Electrons tunnel to the drain region 18 (drain erase). Tunneling The shoot-through current depends on the voltage from the floating gate 14 to the drain 18. However, by biasing the source 16 in the manner shown for the drain 18, a source biasing mechanism can be provided instead of the drain biasing mechanism. During source erasure, the drain potential can be allowed to float. Cells 10 and 10a can be formed using conventional processing techniques such as two-layer, single-metal CMOS processing. The illustrative parameter plan set up here is made A shape size of 0.35pm or lower with a Vcc potential of 1.8 volts. If technically a reduced voltage and a smaller shape size are allowed, the parameters here can be changed proportionally according to this paper. China National Standard (CNS) Α4 Specification (210 × 297 mm) --------- Installation ------ Order ------ Like.-(Please read the precautions on the back before filling (This page) A7 B7, Sealed Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) The starting base material can be typically p-type (100) silicon, for example, with a resistance range of 10 -20 ohm · cm P well 30 is buried in N and 32 treated in so-called triple wells. P well 30 typically has a well depth of, for example, 3 to 4 μm. It has, for example, a doping concentration in the range of 1 × 1016 to 5 × 1016 atoms per cubic centimeter. The N well 32 typically has a well depth of 4.8 μm. The doping concentration can be from 4 × 1015 to 1 × 1016 atoms per cubic centimeter. The triple well system borrows It is formed by inversely doping the P well 30 with the N well 32. The formation of the triple well is as described below. The N well is implanted with, for example, phosphorus P31 with a typical dosage of 1.0 to 1.5 x 1013 atoms per square centimeter and 160 1 Energy from kev to about 100kev is completed. N-well implants are driven using high-mixing steps typically between 1125 and 1150 ° C for 6 to 12 hours. N-well 32 is then reverse-doped with P-well implantation. P wells are typically implanted at 1.5 13 to 2.5 x 10 atoms per square centimeter and boron B11 is used as a seed source at 30 kev to 180 fcev. This sets the wells to the desired doping concentration and depth. After well formation, field oxide formation using standard logic field processing is then isolated from the field. The field oxide thickness and field doping can be adjusted slightly to meet the cell programming requirements. Thereafter, memory cell implantation can be performed later. For example, B11 implants for children with 30 to 50 kev 1.0 to 3.5 x 1013 atoms per square centimeter can be made by scrambling oxides. For example, 85 to 100 angstroms of dry oxide can be grown throughout the crystal pattern. Dry oxides are grown, for example, at 900 ° C after partial oxygen followed by annealing at 975 to 1050 ° C. "
然後浮動閘14可由聚矽、矽酸鹽或金靥被形成。若聚 矽被使用，其可爲1600埃厚度，且P0CL3在870至1000°C 本紙張尺度適用中國國家橾率（CNS ) A4規格（210X297公釐） -----^-----裝------訂------Φ '- (請先W讀背面之注意事項再填寫本頁) ^^389998_b7_ - Λ、發明説明（8) (請先閲讀背面之注意事項再填寫本頁) 被摻雜。多層間介質係由氧化物-氮鹽一氧化物（ΟΝΟ)三明 治所形成，具有下層之氧化物爲60至80埃，氮鹽層爲90 至180埃之厚度，且上層之氧化物爲30至40埃。然後控 .制閘12用之聚矽（第2層）在必要時可被沉積及做成矽酸 鹽。該等閘使用標準自我對齊閘蝕刻技術被做成模型與 界定。 在完成這些電容器電晶體構造後，接點與相互連 接層之後續處理隨後於標準邏輯後端處理進行。 經濟部中央標準局貝工消費合作社印製 本發明係特別要有小於等於 3 . 3伏特而具有 0.35μπι或更小形狀尺寸的技術。在此尺寸中，GIDL 創造了孔陷阱之問題，其有害地影響可靠性並造成 會有害地影響電源供應之汲極洩漏。因而，其要在 這些狀況下使G I DL最小以達到最小的形狀尺寸。此 可藉由使Ρ井與汲極偏置爲相同而完成。然而，此 會使得抹除電流成爲不利。在使得Ρ井電壓與汲極 電壓爲不同電壓成爲可能下，GIDL洩漏電流可被形 成可容忍的，而又使得隧穿抹除所用之Ρ井電位達 到最佳化》因此，Ρ井電位可被選擇來允許得到較小 的負控制閘電壓而達成優異的GIDL與抹除狀況。較 低的控制閘電位使得此技術與標準邏輯程序相容。 雖然數個參數與高度在前述描述中被提供，熟習本技 藝者將i解這些參數與高度僅爲說明之目的》例如，藉由 逆轉摻雜接頭之傳導型態與偏置極性下，使用基底熱孔注 入之晶胞構造可被實施。其欲於使申請專利範圍涵蓋所有 本纸張尺度適用中國國家揉率（CNS ) A4規格（210 X 297公釐） 經濟部中央標率局貝工消費合作社印聚 389998 at _ B7 五、發明説明（9ί) 修改與變化成爲本發明之真實精神與領域內。 元件標號對照 10 記憶體晶胞 10a 記憶體晶胞 12 控制閘 14 浮動閘 16 被摻雜源極區 18 被摻雜汲極區 20 源極電位 24 汲極偏置電位 26 基底偏置電位 28 Ν井電位 30 半導體層，Ρ井 32 Ν井 33 電容器 36 閘偏置電位 42 隧穿氧化物 (請先閲讀背面之注意事項再填寫本頁) -12 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）The floating gate 14 may then be formed of polysilicon, silicate, or gold. If polysilicon is used, its thickness can be 1600 angstroms, and P0CL3 is 870 to 1000 ° C. The paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) ----- ^ ----- Install ------ order ------ Φ '-(Please read the precautions on the back before filling this page) ^^ 389998_b7_-Λ, invention description (8) (Please read the precautions on the back first Fill out this page again). The interlayer dielectric is formed by an oxide-nitrogen salt-oxide (ONO) sandwich, with a lower oxide layer of 60 to 80 angstroms, a nitrogen salt layer of 90 to 180 angstroms, and an upper oxide layer of 30 to 40 Angstroms. The polysilicon (second layer) for the brake 12 can then be deposited and made into a silicate if necessary. The gates are modeled and defined using standard self-aligned gate etching techniques. After these capacitor transistor structures are completed, the subsequent processing of the contacts and interconnects is then performed on standard logic back-end processing. Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics The present invention is particularly a technology having a size of 3.3 volts or less and a shape size of 0.35 μm or less. In this size, GIDL creates a hole trap problem that adversely affects reliability and causes drain leakage that can adversely affect power supply. Therefore, it is necessary to minimize G I DL under these conditions to achieve the smallest shape size. This can be done by biasing the P wells and drains the same. However, this makes the erasure current disadvantageous. With the possibility that the P-well voltage and the drain voltage are different, the GIDL leakage current can be made tolerable, while optimizing the P-well potential used for tunneling erasure. Therefore, the P-well potential can be It is selected to allow a smaller negative control gate voltage to achieve excellent GIDL and erasure conditions. The low control gate potential makes this technology compatible with standard logic programs. Although several parameters and heights are provided in the foregoing description, those skilled in the art will understand these parameters and heights for illustrative purposes only. For example, by reversing the conduction type and bias polarity of a doped joint, using a substrate Cell structure for hot hole injection can be implemented. It intends to make the scope of the patent application cover all the paper sizes applicable to the Chinese national rubbing rate (CNS) A4 specification (210 X 297 mm). The Central Standards Bureau of the Ministry of Economic Affairs, Peugeot Consumer Cooperatives Co., Ltd. printed 389998 at _ B7 V. Description of the invention (9ί) Modifications and changes are within the true spirit and field of the invention. Component number comparison 10 memory cell 10a memory cell 12 control gate 14 floating gate 16 doped source region 18 doped drain region 20 source potential 24 drain bias potential 26 substrate bias potential 28 Ν Well potential 30 semiconductor layer, P well 32 Νwell 33 Capacitor 36 Gate bias potential 42 Tunneling oxide (please read the precautions on the back before filling this page) -12-This paper size applies to China National Standard (CNS) Α4 Specifications (210X297 mm)