CN100334715C - Non-volatile storage element - Google Patents
Non-volatile storage element Download PDFInfo
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- CN100334715C CN100334715C CNB031016855A CN03101685A CN100334715C CN 100334715 C CN100334715 C CN 100334715C CN B031016855 A CNB031016855 A CN B031016855A CN 03101685 A CN03101685 A CN 03101685A CN 100334715 C CN100334715 C CN 100334715C
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- trap
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Abstract
The present invention provides a nonvolatile storage element which is contained in an N-shaped well and forms a first PMOS transistor and a second PMOS transistor which share a p doping region, wherein the first PMOS transistor comprises a control grid; the second PMOS transistor comprises a source electrode, a drain electrode and a floating grid. The method also comprises the following steps: providing the first PMOS transistor with first biasing voltage to break over the first PMOS transistor; providing the second PMOS transistor with second biasing voltage to make the second PMOS transistor generate a grid current; adjusting the coupling capacitance among the floating grid, the drain electrode, the source electrode, the control grid and the N-shaped well according to the potential difference between the floating grid and the drain electrode of the second PMOS.
Description
Technical field
The invention provides a kind of monocrystalline silicon (single poly) single (one timeprogrammable able to programme, OTP) the muptiple-use programmable non-volatile memory cell of non-volatile memory cells or monocrystalline silicon (multiple time programmable, MTP) manufacture method, refer in particular to that a kind of (metal oxidesemiconductor, MOS) transistorized coupling capacitance is to speed the method that it writes data manipulation by adjusting a metal-oxide semiconductor (MOS) in this non-volatile memory cells.
Background technology
In recent years, can continue to preserve the interior data of memory after the non-volatile memory device of nonvolatile memory and so on owing to have is cut off the electricity supply, and have the characteristic that data were got/write to repeatable read, so often be used to store nonvolatil data.And the speed of nonvolatile memory read/write data also often is to judge the important reference of this nonvolatile memory quality quality.
Please refer to Fig. 1, Fig. 1 is the generalized section of a known non-volatile memory cells 10.Non-volatile memory cells 10 comprises one the one PMOS transistor 12 and one the 2nd PMOS transistor 14, the one PMOS transistor 12 and the 2nd PMOS transistor 14 are formed on the N type trap 16, and the 2nd PMOS transistor 14 is serially connected with a PMOS transistor 12 in the mode with a PMOS transistor 12 shared one the 2nd p+ doped regions 20.The one PMOS transistor 12 comprises one the one p
+ Doped region 18 as the drain electrode of a PMOS transistor 12, a control grid 24 is located between first doped region 18 and second doped region 20 and one source pole 20 (the 2nd p just
+ Doped region 20).The 2nd PMOS transistor 14 is floating grid transistors, and it comprises drain electrode 20 (the 2nd p just
+Doped region 20), one the 3rd p
+ Doped region 22 formed by single level polysilicon as source electrode, a floating grid 26 of the 2nd PMOS transistor 14 and a floating grid oxide skin(coating) 32 between floating grid 26 and N type trap 16.
The one PMOS transistor 12 of known non-volatile memory cells 10 and each utmost point of the 2nd PMOS transistor 12 all can be subjected to different voltage to carry out different programming operation (writing data or reading of data).For instance, refer again to Fig. 1, in the time data will being write to non-volatile memory cells 10, can be at the p of a PMOS transistor 12
+ Drain doping region 18 applies a bit-line voltage V
1=0V, in control grid 24 apply a word line voltage V
2=-2V (V
2Voltage should be lower than bit-line voltage V
1At least one start voltage value size).A P type raceway groove that is positioned at control grid 24 belows this moment can be opened, and then makes the 2nd p
+A doped region 20 and a p
+ Drain doping region 18 has identical current potential (that is the voltage of the drain electrode 18 of a PMOS transistor 12 and source electrode 20 is 0V).Then apply a trap voltage V in N type trap 16
3=5V, make the floating grid 26 of the 2nd PMOS transistor 14 keep floating states, in the 3rd p
+ Doped region 22 applies one source pole line voltage and V
4=5V makes the source electrode 22 of the 2nd PMOS transistor 14 have identical current potential with N type trap 16.Under above-mentioned operating condition, because the floating grid 26 of the 2nd PMOS transistor 14 can obtain a low-voltage (for example 3～4V) by capacitance coupling effect, and the 2nd P type raceway groove of floating grid 26 belows is opened, the collision in hole that can Yin Qinei in the 2nd P type raceway groove and produce hot electron, these hot electrons also can be crossed floating grid oxide skin(coating) 32 apace because of the electric field action of exhaustion region, and be caught to sink in the floating grid 26, to finish the operation that data write.
Please refer to Fig. 2, Fig. 2 is the floating grid 26 of the 2nd PMOS transistor 12 of non-volatile memory cells 10 and the potential difference V between the source electrode 22
FsWith the graph of a relation of the grid current I of the 2nd P type raceway groove of flowing through, wherein solid line is represented different bias voltages respectively with dotted line.As shown in Figure 2, as potential difference V
FsNear a threshold voltage V
ThThe time, grid current I can be near a largest gate electric current I
MaxThe size of grid current I can directly influence data and write (also comprising reading of data etc. certainly) and to the speed of non-volatile memory cells 10, that is to say, as the floating grid 26 of the 2nd PMOS transistor 14 and the potential difference V between the source electrode 22
FsWhen being greater than or less than this threshold voltage, the grid current I of the 2nd P type raceway groove of flowing through can be less than this largest gate electric current I
Max, and and then influence speed in the floating grid 26 of the 2nd PMOS transistor 14 that data write to non-volatile memory cells 10.By among Fig. 2 and can find out, no matter this bias value is why, the largest gate electric current I
MaxPairing threshold voltage V
ThValue all be approximately-1.2 volts.
Summary of the invention
Therefore, the floating grid that the object of the present invention is to provide the metal oxide semiconductor transistor in a kind of foundation one nonvolatile memory and the potential difference between drain electrode are adjusted the nonvolatile memory manufacture method of the coupling capacitance between each utmost point of this metal oxide semiconductor transistor, with the shortcoming of solution known technology.
Method of the present invention comprises following step: (a) form one first doped region on a trap, one second doped region and one the 3rd doped region, (b) between this first doped region and this second doped region, form a control grid, (c) between this second doped region and the 3rd doped region, form a floating grid, (d) between this first doped region and this control grid, provide one first bias voltage, so that this first doped region and this second doped region are able to conducting, (e) between this second doped region and this trap, provide one second bias voltage, so that produce a grid current between this second doped region and the 3rd doped region, (f) if the voltage difference between the 3rd doped region and this floating grid less than a threshold value, the increment rate that then makes the coupling capacitance between this floating grid and the 3rd doped region is greater than this floating grid and this N type trap, this floating grid and this second doped region, and the increment rate of the summation of the coupling capacitance between this floating grid and this control grid or make this floating grid and this control grid between the increment rate of coupling capacitance greater than this floating grid and the 3rd doped region, this floating grid and this trap, and the increment rate of the summation of the coupling capacitance between this floating grid and this second doped region, and (g) if the voltage difference between the 3rd doped region and this floating grid greater than this threshold value, the increment rate that then makes the coupling capacitance between this floating grid and the 3rd doped region is less than this floating grid and this trap, this floating grid and this second doped region, and the increment rate of the summation of the coupling capacitance between this floating grid and this control grid and make this floating grid and this control grid between the increment rate of coupling capacitance also less than this floating grid and the 3rd doped region, this floating grid and this trap, and the increment rate of the summation of the coupling capacitance between this floating grid and this second doped region.
Method of the present invention also comprises step (h) provides a P type substrate.
This above-mentioned trap can be a N type trap or a P type trap.If this trap is a N type trap, then this first doped region, this second doped region, and the 3rd doped region be all p
+Doped region, and this N type trap, this first doped region, this second doped region, and this control grid form a PMOS transistor, and this N type trap, this second doped region, the 3rd doped region, reach this floating grid and form another PMOS transistor; Otherwise, if this trap is a P type trap, then this first doped region, this second doped region, and the 3rd doped region be all n
+Doped region, and this P type trap, this first doped region, this second doped region, and this control grid form a nmos pass transistor, and this P type trap, this second doped region, the 3rd doped region, reach this floating grid and form another nmos pass transistor.
Description of drawings
Fig. 1 is the generalized section of known non-volatile memory cells.
Fig. 2 is the floating grid voltage of the metal oxide semiconductor transistor in the non-volatile memory cells of Fig. 1 and the graph of a relation of grid current.
Fig. 3 is the generalized section of non-volatile memory cells of the present invention.
Fig. 4 is the flow chart of method of the present invention.
Fig. 5 A to Fig. 5 F for use method of the present invention in the voltage of the floating grid of second MOS transistor of the shown non-volatile memory cells of Fig. 3 less than a threshold voltage V
ThThe time, adjust the equivalent circuit diagram of this non-volatile memory cells after the coupling capacitance of second MOS transistor of this non-volatile memory cells.
Fig. 6 A to Fig. 6 F for use method of the present invention in the voltage of the floating grid of second MOS transistor of the shown non-volatile memory cells of Fig. 3 less than threshold voltage V
ThThe time, adjust the equivalent circuit diagram of this non-volatile memory cells after the coupling capacitance of second MOS transistor of this non-volatile memory cells.
Fig. 7 A to Fig. 7 D for use method of the present invention in the voltage of the floating grid of second MOS transistor of the shown non-volatile memory cells of Fig. 3 greater than threshold voltage V
ThThe time, adjust the equivalent circuit diagram of this non-volatile memory cells after the coupling capacitance of second MOS transistor of this non-volatile memory cells.
Fig. 8 A to Fig. 8 D for use method of the present invention in the voltage of the floating grid of second MOS transistor of the shown non-volatile memory cells of Fig. 3 greater than threshold voltage V
ThThe time, adjust the equivalent circuit diagram of this non-volatile memory cells after the coupling capacitance of second MOS transistor of this non-volatile memory cells.
The reference numeral explanation
10,40 non-volatile memory cells 12 a PMOS transistor
14 the 2nd PMOS transistors, 16 N type traps
18 the one p
+ Doped region 20 the 2nd p
+Doped region
22 the 3rd P+ doped regions, 24 control grids
26 floating grids, 32 floating grid oxide skin(coating)s
42 P type semiconductor substrates, 44 traps
46 first doped regions, 48 second doped regions
50 the 3rd doped regions, 52 control grids
54 floating grids, 56 first MOS transistor
58 second MOS transistor
Embodiment
Before method of the present invention is described in detail in detail, earlier with the physical characteristic explanation relevant that non-volatile memory cells had with method of the present invention as after.Please refer to Fig. 3, Fig. 3 is the generalized section of non-volatile memory cells 40 of the present invention.Non-volatile memory cells 40 comprises that a P type semiconductor substrate 42, a trap 44 are formed on the P type semiconductor substrate 42, one first doped region 46, one second doped region 48, one the 3rd doped region 50, a control grid 52, an and floating grid 54.Trap 44, first doped region 46, second doped region 48 and control grid 52 common formation one first MOS transistor 56, and trap 44, second doped region 48, the 3rd doped region 50 and floating grid 54 common one second MOS transistor 58 that form.Because the data Writing condition of non-volatile memory cells 40 of the present invention and the data Writing condition and the process of process and known non-volatile memory cells 10 are identical, so repeat no more in this.
When floating grid 54 belows of first MOS transistor, 56 conductings of non-volatile memory cells 40 and second MOS transistor 58 because of channel hot electron effect (channel hot electron effect) when producing a grid current I, the floating grid 54 of second MOS transistor 58 can produce a coupled voltages V
f, coupled voltages V
fSize be relevant to the voltage of trap 44, second doped region 48, the 3rd doped region 50 and control grid 52 that is V
f=α
FwV
w+ α
FsV
s+ α
FdV
d+ α
FcV
c, V wherein
wBe the voltage of trap 44, voltage, the V that vs is second doped region 48
dBe voltage, the V of the 3rd doped region 50
cThen be the voltage of control grid 52, and α
Fw, α
Fs, α
Fd, and α
FcBe all coupling coefficient (couplingratio).As its name suggests, coupling coefficient is exactly V
w, V
s, V
d, and V
cRespectively to V
fThe degree of coupling, just V
w, V
s, V
d, and V
cRespectively to V
fThe magnitude of voltage that is provided.
The value of above-mentioned coupling coefficient α gs is relevant to the coupling capacitance that non-volatile memory cells 40 is produced when conducting, that is coupling coefficient α
Fd=C
Fd/ (C
Fs+ C
Fd+ C
Fw+ C
Fc) (please note α
Fs+ α
Fw+ α
Fd+ α
Fc=1, just increase α
Fd, α
Fc, relatively, α
Fs, α
FwWill reduce).Refer again to Fig. 3, the dotted line those shown is respectively floating grid 54 and 48 coupling capacitance C that produced of second doped region among Fig. 3
FsFloating grid 54 and 50 coupling capacitance C that produced of the 3rd doped region
Fd, floating grid 54 and 44 coupling capacitance C that produced of trap
Fw, and floating grid 54 and control grid 52 coupling capacitance C that produced
FcTherefore in making nonvolatile memory 40 processes, if the coupled voltages V that floating grid 54 is produced because of the channel hot electron effect
cBe not equal to threshold voltage V
Th, then can adjust coupling capacitance C through the layout type that changes second MOS transistor 58
Fs, C
Fd, C
Fw, and C
FcValue so that coupled voltages V
cBe tending towards threshold voltage V
Th, and and then make grid current I level off to the largest gate electric current I
MaxRepresent above-mentioned coupling capacitance C in the mode of dotted line
Fs, C
Fd, C
Fw, and C
FcBecause these coupling capacitances C
Fs, C
Fd, C
Fw, and C
FcOnly come from the electric effect of non-volatile memory cells 40, rather than really be present in the non-volatile memory cells 40.Threshold voltage V
ThAbsolute value between 0.5 to 1.5 volt.
In general, the 3rd doped region 50 of non-volatile memory cells 40 is connected to a bit line BL (not shown), and the control grid 52 of non-volatile memory cells 40 is connected to a word line WL (not shown), when data are desired to write to non-volatile memory cells 40, being connected to the bit line BL of non-volatile memory cells 40 and word line WL all can be configured to high voltage (for example the voltage of bit line BL is configured to 5 volts, the voltage of word line WL is configured to 10 volts), owing to the voltage V of the 3rd doped region 50 this moment
dAnd the voltage V of control grid 52
cAll greater than the voltage V of second doped region 48
sAnd the voltage V of trap 44
wSo, if the coupled voltages V that floating grid 54 is produced because of the channel hot electron effect
fLess than threshold voltage V
Th, then can be by increasing α
FdOr α
FcMode increase coupled voltages V
f(because increasing α
FdOr α
FcThe time, α
FsAnd α
FwAll can reduce, and because V
d, V
cGreater than V
s, V
wSo, can be by increasing α
FdOr α
Fc, to increase coupled voltages V
f), just can be by making C
FdOr C
FcRecruitment all greater than C
FsOr C
FwThe mode of recruitment increase coupled voltages V
fOtherwise, if the coupled voltages V that floating grid 54 is produced because of the channel hot electron effect
fGreater than threshold voltage V
Th, then can be by increasing α
FwOr α
FsMode increase coupled voltages V
f, just can be by making C
FdOr C
FcRecruitment all less than C
FsOr C
FwThe mode of recruitment reduce coupled voltages V
f
In order to specify the manufacture method of non-volatile memory cells 40 of the present invention, please refer to Fig. 4, Fig. 4 is flow process Figure 100 of the manufacture method of non-volatile memory cells 40 of the present invention, flow process Figure 100 comprises following step:
Step 102: beginning; (at this moment, suppose that the prototype of non-volatile memory cells 40 is made, just on P type semiconductor substrate 42, utilized general semiconductor fabrication to form the PMOS transistor of two serial connections or the nmos pass transistor of two serial connections)
Step 104: between first doped region 46 and control grid 52, provide one first bias voltage, so that first doped region 46 and second doped region 48 are able to conducting; (this first bias voltage needs the start voltage greater than first MOS transistor 56)
Step 106: one second bias voltage is provided between second doped region 48 and trap 44 so that produce a channel current between second doped region 48 and the 3rd doped region 50, with so that produce a grid current I; (value of this second bias voltage is regardless of size, as long as can make second MOS transistor 58 produce this grid current I, because threshold voltage V
ThCan't change because of the difference of the value of this second bias voltage)
Step 108: according to the potential difference and the threshold voltage V of 50 of floating grid 54 and the 3rd doped regions
ThRelation, adjust the layout of second MOS transistor 58; (just if the voltage difference of 54 of the 3rd doped region 50 and floating grids less than this threshold voltage, the increment rate that then makes the coupling capacitance between floating grid 54 and the 3rd doped region 50 is greater than floating grid 54 and N type trap 44, the floating grid 54 and second doped region 48, and the increment rate of floating grid 54 and the summation of the coupling capacitance of control between the grid 52 or the increment rate that makes floating grid 54 and control the coupling capacitance between the grid 52 are greater than floating grid 54 and the 3rd doped region 50, floating grid 54 and trap 44, and the increment rate of the summation of the coupling capacitance between the floating grid 54 and second doped region 48; And if the voltage difference of the 3rd doped region 50 and floating grid 54 greater than this threshold voltage, then makes the increment rate of coupling capacitance of 50 of floating grid 54 and the 3rd doped regions less than floating grid 54 and trap 44, the floating grid 54 and second doped region 48, and the increment rate of floating grid 54 and the summation of the coupling capacitance of control between the grid 52 and the increment rate that makes floating grid 54 and control the coupling capacitance between the grid 52 are also less than floating grid 54 and the 3rd doped region 50, floating grid 54 and trap 44, and the increment rate of the summation of the coupling capacitance between the floating grid 54 and second doped region 48.)
Step 110: finish; (at this moment, when non-volatile memory cells 40 is desired to be written into data, the bit line BL and the word line WL that are connected to non-volatile memory cells 40 can be configured to high voltage, and first MOS transistor, the 56 meeting conductings of non-volatile memory cells 40, and second MOS transistor 58 can produce this grid current I, and the floating grid 54 of second MOS transistor 58 can convergence threshold voltage V
Th, and grid current I can convergence largest gate electric current I
Max).
In the manufacture method of the invention described above non-volatile memory cells 40, step 108 is carried out sustainably, up to the potential difference and the threshold voltage V of 50 of floating grid 54 and the 3rd doped regions
ThTill very approaching.
Please refer to Fig. 5 A to Fig. 5 F, Fig. 5 A to Fig. 5 F for use method of the present invention in the voltage of the floating grid 54 of second MOS transistor 58 of non-volatile memory cells 40 less than threshold voltage V
ThThe time, adjust the equivalent circuit diagram of non-volatile memory cells 40 after the coupling capacitance of second MOS transistor 58 of non-volatile memory cells 40, wherein to be all PMOS, trap 44 be that the floating grid 54 that the control grid 52 of a N type trap, first MOS transistor 56 is connected to word line WL second MOS transistor 58 then is connected to bit line BL for first MOS transistor 56 and second MOS transistor.Note that the C among Fig. 5 B
FdNeed greater than C
Fs, the C among Fig. 5 C
FdNeed greater than C
Fw, the C among Fig. 5 E
FcNeed greater than C
Fs, and Fig. 5 F in C
FcNeed greater than C
Fw
Please refer to Fig. 6 A to Fig. 6 F, Fig. 6 A to Fig. 6 F for use method of the present invention in the voltage of the floating grid 54 of second MOS transistor 58 of non-volatile memory cells 40 less than threshold voltage V
ThThe time, the equivalent circuit diagram of non-volatile memory cells 40 after the coupling capacitance of second MOS transistor 58 of adjustment non-volatile memory cells 40.Be different from the non-volatile memory cells 40 among Fig. 5 A to Fig. 5 F, first MOS transistor 56 and second MOS transistor 58 in the non-volatile memory cells 40 of Fig. 6 A to Fig. 6 F are all nmos pass transistor, and trap 44 is a P type trap.Be noted that the C among Fig. 6 B equally
FdNeed greater than C
Fs, the C among Fig. 6 C
FdNeed greater than C
Fw, the C among Fig. 6 E
FcNeed greater than C
Fs, and Fig. 6 F in C
FcNeed greater than C
Fw
Please refer to Fig. 7 A to Fig. 7 D, Fig. 7 A to Fig. 7 D for use method of the present invention in the voltage of the floating grid 54 of second MOS transistor 58 of non-volatile memory cells 40 greater than threshold voltage V
ThThe time, adjust the equivalent circuit diagram of non-volatile memory cells 40 after the coupling capacitance of second MOS transistor 58 of non-volatile memory cells 40, wherein to be all PMOS, trap 44 be that the floating grid 54 that the control grid 52 of a N type trap, first MOS transistor 56 connects as for word line WL second MOS transistor 58 then is connected to bit line BL for first MOS transistor 56 and second MOS transistor.Note that the C among Fig. 7 C
FdLess than C
Fs, and Fig. 7 D in C
FdNeed less than C
Fw
Please refer to Fig. 8 A to Fig. 8 D, Fig. 8 A to Fig. 8 D for use method of the present invention in the voltage of the floating grid 54 of second MOS transistor 58 of non-volatile memory cells 40 greater than threshold voltage V
ThThe time, the equivalent circuit diagram of non-volatile memory cells 40 after the coupling capacitance of second MOS transistor 58 of adjustment non-volatile memory cells 40, be different from the non-volatile memory cells 40 among Fig. 7 A to Fig. 7 D, first MOS transistor 56 and second MOS transistor 58 in the non-volatile memory cells 40 of Fig. 8 A to Fig. 8 D are all nmos pass transistor, and trap 44 is a P type trap.Be noted that the C among Fig. 8 C equally
FdNeed less than C
Fs, the C among Fig. 8 D
FdNeed less than C
Fw
Compared to the production method of known non-volatile memory cells 10, the production method of non-volatile memory cells 40 of the present invention can make the grid current 1 of its interior second MOS transistor 58 level off to the largest gate electric current I
Max, so that the data writing rate of non-volatile memory cells of the present invention 40 is high far beyond the data writing rate of known non-volatile memory cells 10.In addition, method of the present invention utilizes existing semiconductor fabrication to make non-volatile memory cells 40, method just of the present invention is not except changing existing semiconductor fabrication, do not have extra manufacture process to make non-volatile memory cells 40, therefore method of the present invention can not have any change because of the difference (process-toprocess difference) of semiconductor fabrication or the difference (fab-to-fab difference) of semiconductor property yet.
The above only is preferred embodiment of the present invention, and all equivalences of making according to claims of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (6)
1. method of making the metal oxide semiconductor transistor in the nonvolatile memory, it comprises:
On a trap, form one first doped region, one second doped region and one the 3rd doped region;
Between this first doped region and this second doped region, form a control grid;
Between this second doped region and the 3rd doped region, form a floating grid;
Between this first doped region and this control grid, provide one first bias voltage, so that this first doped region and this second doped region are able to conducting;
One second bias voltage is provided between this second doped region and this trap so that produce a channel current between this second doped region and the 3rd doped region, with so produce a grid current;
If the increment rate that the voltage difference between the 3rd doped region and this floating grid, then makes the coupling capacitance between this floating grid and the 3rd doped region less than a threshold value greater than this floating grid and this trap, this floating grid and this second doped region, reach the coupling capacitance between this floating grid and this control grid summation increment rate or make this floating grid and this control grid between the increment rate of coupling capacitance greater than this floating grid and the 3rd doped region, this floating grid and this trap, reach the increment rate of the summation of the coupling capacitance between this floating grid and this second doped region; And
If the increment rate that the voltage difference between the 3rd doped region and this floating grid, then makes the coupling capacitance between this floating grid and the 3rd doped region greater than this threshold value less than this floating grid and this trap, this floating grid and this second doped region, reach the coupling capacitance between this floating grid and this control grid summation increment rate and make this floating grid and this control grid between coupling capacitance increment rate also less than this floating grid and the 3rd doped region, this floating grid and this trap, reach the increment rate of the summation of the coupling capacitance between this floating grid and this second doped region.
2. the method for claim 1, wherein the absolute value of this threshold value is between 0.5 to 1.5 volt.
3. the method for claim 1, wherein this trap is a N type trap, this first doped region, this second doped region, and the 3rd doped region be all p
+Doped region.
4. method as claimed in claim 3, it also comprises provides a P type substrate, wherein this N type trap, this first doped region, this second doped region, and this control grid form a P type MOS transistor, and this N type trap, this second doped region, the 3rd doped region, reach this floating grid and form another PMOS transistor.
5. the method for claim 1, wherein this trap is a P type trap, this first doped region, this second doped region, and the 3rd doped region be all n
+Doped region.
6. method as claimed in claim 5, it also comprises provides a P type substrate, wherein this P type trap, this first doped region, this second doped region, and this control grid form a nmos pass transistor, and this P type trap, this second doped region, the 3rd doped region, reach this floating grid and form another nmos pass transistor.
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| CNB031016855A CN100334715C (en) | 2003-01-14 | 2003-01-14 | Non-volatile storage element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031016855A CN100334715C (en) | 2003-01-14 | 2003-01-14 | Non-volatile storage element |
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|---|---|
| CN1518096A CN1518096A (en) | 2004-08-04 |
| CN100334715C true CN100334715C (en) | 2007-08-29 |
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| KR100849852B1 (en) * | 2005-08-09 | 2008-08-01 | 삼성전자주식회사 | Nonvolatile semiconductor integrated circuit device and fabrication method thereof |
| KR100998945B1 (en) * | 2008-09-05 | 2010-12-09 | 주식회사 하이닉스반도체 | Method for fabricating non-volatile memory device |
| CN105790573B (en) * | 2016-04-20 | 2018-11-23 | 合肥格易集成电路有限公司 | A kind of charging capacitor and pump circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5136541A (en) * | 1987-12-15 | 1992-08-04 | Sony Corporation | Programmable read only memory using stacked-gate cell erasable by hole injection |
| CN1252156A (en) * | 1997-04-11 | 2000-05-03 | 硅芯片公司 | Electrically erasable nonvolatile memory |
-
2003
- 2003-01-14 CN CNB031016855A patent/CN100334715C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5136541A (en) * | 1987-12-15 | 1992-08-04 | Sony Corporation | Programmable read only memory using stacked-gate cell erasable by hole injection |
| CN1252156A (en) * | 1997-04-11 | 2000-05-03 | 硅芯片公司 | Electrically erasable nonvolatile memory |
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