JPS63271973A - Electrically programmable and electrically erasable memory cell and manufacture of the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates in particular to the field of electrically programmable and electrically erasable memory cells using 70-digit gates.

[Prior art]

For many years, metal-oxide-semiconductor (MOS) technology has been used to make electrically programmable read-only memories (EPROMs). Many of these cells use a floating gate, ie, a polysilicon member completely surrounded by an insulator. Note that charges are determined by avalanche injection, channel injection, 7 Fowler-Nordheim
Various mechanisms such as tunneling, hot electron injection from the substrate, etc.
Transferred to gate. Various phenomena have been used to remove the charge, including exposing the memory to ultraviolet light. Commercially available E with floating gate
FROM originally used avalanche injection to charge the floating gate, but next generation memories use channel injection to program. These memories are currently erased by exposure to ultraviolet light.

Commercially available electrically programmable and electrically erasable memory+7 (EEFROM) devices use thin oxide regions at the negative gate to tunnel charge to and from the floating gate. are doing. A typical memory uses two transistor cells. For example, U.S. Patent No. 4,203,158
In the issue, there is an explanation about such cells,
Related circuitry is also described in U.S. Pat. No. 4,266,283. However, these EEPRO
M cell is Ii? Like ROM cells, it does not help reduce substrate area. Therefore, the relatively dense E
Although PROMs are currently in use (e.g., 256 λ FROMs cannot be used for high density play).

Ideally, an EEFROM that helps reduce the size (less than 50 μm, which is optimal for use in current cells)
is required. Also, EEPROMs must operate from a potential of 5 volts.

That is, the current required for high voltage programming and erasing must be provided by on-chip charge pumping circuitry.

One attempt to provide high density, low voltage EEFROM cells is provided in U.S. Pat. Nos. 4,432,075 and 4.57
7.295. Here, many cells share one hot electron source for programming. This has the advantage of not requiring large geometries, which is useful for ensuring channel implantation. However, this technology is slow to program and has not yet been commercialized.

Single transistor EEPRO using channel injection to program the floating gate and tunneling to discharge the gate
The M cell is disclosed in U.S. patent application Ser.
cell”.

This application has been assigned to the applicant.

The advantages of this cell are its small size, its ability to be scaled down, and its true one-transistor electrically programmable and electrically erasable cell. Additionally, this cell is compatible with common UV erasable EPROM processing.

〔Problems to be solved〕

However, as previously discussed, this memory cell has several potential problems. First, the threshold of this cell becomes negative (ie, depression-like) after erasure.

Such a negative threshold voltage after erase may disable all column lines in the array. Second, the limited gated diode breakdown voltage in the source region (the node where the erase voltage is supplied) can cause troublesome problems. This limited gated diode breakdown voltage makes it difficult to provide a suitable charge pump circuit and can also cause reliability problems.

As will be described later, the present invention provides a memory cell that can be implemented in a high-density play and that solves these problems.

As for other prior art, there is a paper titled "IPROM cell with high gate injection efficiency" presented by N. Kamya at the International Electron Device Meeting in San Francisco, California in December 1982. U.S. Pat. No. 4,114.255 also describes the use of a "p-type region formed as part of front-end processing" to more easily inject charge from the channel to the floating gate device. has been done.

[Summary of the invention]

An electrically programmable and electrically erasable memory cell of the present invention is described. The cell has first and second spaced apart regions of a first conductivity type forming a channel. A first gate member (floating gate) completely surrounded by an insulator includes at least a first
Extending from the edge of the region onto the channel. The second gate member (control gate) has a portion extending over the first gate member, and the second gate typically extends from the edge of at least the first region, over the channel, and into the at least second region. It extends to the edge. In addition, the main body
A third region of conductivity type is formed. This third area is
adjacent the edge of the second region and extending at least to the edge of the first gate member. The cell thus has both a memory device and an integrally formed selection device.

〔Example〕

A memory cell and a method of manufacturing the memory cell according to the present invention will be described. The memory cell of the present invention is an electrically programmable and electrically erasable metal-oxide-semiconductor device with an integrally formed select transistor. In the following description, various specific descriptions such as doping levels are provided to aid understanding of the present invention, and it will be apparent to those skilled in the art that the present invention is not limited to these specific descriptions. Probably. In other instances, well-known structures and processes are not described in detail so as not to obscure the present invention.

In the following description, the memory cell of the present invention is an NMO
Although formed on a p-type silicon substrate using S technology, the memory cells can be formed in wells, as is common in CMOS processing, or in layers such as epitaxial layers or other semiconductors. It will be obvious to those skilled in the art that it may also be formed on the body.

Figure 1 shows 1. Formed on a shaped single crystal silicon substrate 1o,
A completed memory cell is shown.

This has an n-type source region 1Sa spaced apart from n-type drain regions 18m and 18b. The channel area is
It is formed between the source and drain regions. The source region 16& extends deeper into the substrate than the main region 18& of the drain region. Furthermore, the drain region has a shallower portion 18b than the main drain region 1aa.

A third region 20m is formed in the substrate adjacent to the drain region, more particularly adjacent to the portion 18b of the drain region. This region 20& is formed of p-type dopant boron.

The first polysilicon layer is used to form polysilicon gate 12m. This gate is insulated from the substrate 10 by a gate silicon oxide film and is completely surrounded by the silicon oxide film. This gate is
A "floating gate" as used in many conventional EPROM and EEPROM cells. floating gate) 12m at least in the source region 1
It extends from the edge of 6a to the edge of area 20m.

In fact, due to the lateral diffusion that occurs during the processing process, w
The c3 region 20m and the source region 16m extend below the edge of the 70-ting gate 12m.

The memory cell has a control gate formed from a layer of polysilicon. Control gate 14a is isolated from 70-ting gate 12m and the substrate. The control gate extends from above floating gate 12a, beyond edge 13 of floating gate 12a, and overlaps drain regions 18m, 18b.

FIG. 2 shows polysilicon strip 12. FIG. A portion of this strip is etched in alignment with the polysilicon strip 14 above it to form the edge of floating gate 12m opposite edge 13. (The strip 14 forms the program/erase/read lines in the play containing the cells of the present invention. The strip 14 has a plurality of gates 14m in the play.) The contacts (metal contacts) , extending into and making contact with the drain region.

To program the device of FIG. 1, i.e., place electrons on floating gate 12a, the drain terminal is high (e.g., 5-8 volts) while control gate 14a is placed at a high voltage (e.g., 10 volts). ~
14 Porto). The source is grounded. In such conditions, channel injection takes place and electrons are transferred to the floating gate 12&. To erase the floating gate (1! remove the load), float the drain region while holding the control gate 14m at ground and applying a high voltage (e.g. 11-14 volts) to the source region. .

Under such conditions, charge is transferred to the source region.

In addition, the state of the floating gate can be determined by supplying a reference potential to the control gate 14m and determining whether conduction has occurred between the source region and the drain region, as is generally done. (in the read cycle). Note that depending on the application, "reverse erasing" may be used. In this case, the source and drain are opposite to those shown;
Programming and erasing is performed from the drain region.

Region 20m acts as a selection transistor (for example, selection transistors are often used, as shown in US Pat. No. 4,266,283).

When no reference potential is present on gate 14a (ie, when the gate is grounded), the integrally formed select transistor formed by region 20a is in an off state. Therefore, if the 70-ting gate 12a operates like a depletion mode device, no current will flow even if it is repeatedly erased. In this way, the columns of the memory array with cells are not affected. This is an advantage over prior art memory cells that do not use select transistors.

With reference to FIG. 3, the manufacturing process of the memory cell of the present invention will be described. A p-type single crystal silicon substrate 10 is implanted with boron to adjust the ultimate threshold voltage of the memory cell. For example, to provide the enhancement mode device of this example, boron is implanted to a level of 1×101174 m 2 in one or more implant steps.

As shown in FIG. 4, an insulating layer is formed on the substrate 10. As shown in FIG. This layer is preferably thermally grown silicon oxide and has a thickness of 150 Å or less. The threshold voltage adjustment dopant implant of FIG. 1 is performed through the gate oxide (as is sometimes done).

A first layer of polycrystalline silicon (polysilicon) is formed on gate oxide film 11 . In this embodiment, a floating gate edge 13 is formed as shown in FIG. (The sides of the gate form strips 12, as shown in FIG. 2.) The edges of the 70-ting gate opposite edge 13 may also be formed at this time, but as noted above, this implementation In the example, this second edge is formed in alignment with the subsequently formed control gate 14m.

Conventional photolithographic processing and etching is used to etch this first polysilicon layer.

Next, as shown in FIG. 5, a silicon oxide film 22 is formed by chemical vapor deposition (CVO) on the surface of the structure shown in FIG. The thickness of this layer is s,ooo~10.0OOA
It is.

This layer 22 is then subjected to an anisotropic plasma etching step. This process is controlled in a known manner to partially etch away layer 22. , the region adjacent edge 35 is thickened, as shown in FIG. 5, and the etching can be controlled to leave this thick region of oxide film 22. This thick region is shown as spacer 24 in FIG.

For substrates with spacers 24, 1.0 x 10
An n-type dopant implant (in this example arsenic is used) is performed to a level of 11'. Note that the thickness of spacer 24 is sufficiently thick so that no dopant implantation is performed under spacer 24.

Next, the spacer 24 is removed by a normal etching process, and boron is implanted to a level of 1xlQ 7cm, as shown in FIG. Note that a boron dopant is also deposited in region 1B, but the level of boron doping used is such that it changes the conductivity type of this region.
Since there is not enough, this region remains an n-type region.

Furthermore, an interpolysilicon dielectric layer is formed on the structure shown in FIG. For example, a CvD silicon oxide film is formed and a second layer of polysilicon is deposited on the silicon oxide film. The second layer of polysilicon is then etched to form a control gate 141 as shown in FIG. Conventional photolithographic and etching processes are used for this. As previously discussed, the edge of floating gate 12a opposite edge 35 is formed in alignment with control gate 14a above it. The etching process that creates this alignment between the first and second layers of polysilicon is described in U.S. Pat.
2.926.

Subsequently, as shown in FIG. 8, arsenic is implanted into this substrate. A conventional source/drain implant at a level of 4xlQ/lOM is used for this.

This injection is typically performed in alignment with control gate 14m. Therefore, the dopant in the source region is
The dopants in the drain region beyond the edge of the control gate) 14m are implanted in the substrate (region 16), while the dopants in the drain region beyond the edge of the control gate) 14m are
8). Furthermore, the area beyond edge 37 is
Since arsenic is implanted twice, the area adjacent to the edge) 1
It appears that more arsenic ions exist in the portion beyond the edge 3T of the gate 14 than below the edge 4&.

In FIG. 9, a photoresist masking member 30 is formed using a conventional masking process. This member 30 covers region 18 while leaving region 16 exposed. Another implant step is used to further dope region 16. The dopant at this time is phosphorus. In this example, phosphorus is 5×10 A to 1×1Q/117F!
is injected to the level of Phosphorus dopant was chosen because it diffuses more easily into silicon than arsenic, resulting in a more gradual source junction profile. That is, the n-type dopant changes at a slower rate in the junction than in the drain region.

Subsequently, the substrate is subjected to a high temperature driver process to activate the dopant. As a result, a source region 16m and shallow drain regions 18m and 18b are formed. The drain region has a main drain region 18m deeper than a portion 18b of the drain region.

The driver process drives the source region slightly below the edges of the floating gate and control gate, and drives a region 20m slightly below the edge 13 of the 70-ring gate. The deep portion 18J& of the drain region is driven below the edge of the control gate.

The device is then completed using conventional "rear-end processing" including passivation layer formation and metallization.

The process described above forms a <0.5 micron "spacer formation" channel region on the drain side of the memory cell. The boron implant used in this region is relatively high so that the boron does not diffuse outward. , 70 overlaps a small portion of the floating gate channel, i.e. the region 2oa extends below the edge 13 of the floating gate 12a, as described above.Due to the high boron concentration in this region, the A channel electric field is created, thus improving the programming properties. Importantly, the width of the spacer-forming boron region is kept nearly constant, i.e., despite major process variations. is largely unaffected. This is a result of the well-functioning nature of the anisotropic plasma etch used to form the spacer 24 of FIG.
The gap between the sidewalls of the zeroing gate and the control gate above it (separated by an interpoly dielectric) is more important in the reverse erase mode mentioned above, but as mentioned in Kamya's paper. In addition, the programming characteristics are improved.

Since the doping concentration under the floating gate on the source side of the device is relatively low, the source-gate diode breakdown voltage does not degrade. A high source-gated diode breakdown voltage allows the use of high erase voltages, resulting in
Erasing time can be shortened and/or the gate oxide film can be thickened.

As described above, the electrically programmable and electrically erasable memory cells of the present invention have a "spacer-forming" channel region that includes a floating gate device forming an integrated select device. are doing. This spacer formation region enhances the programming characteristics and also allows the memory cell to be
Cells can be erased to “depression”.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of the memory cell of the present invention, FIG. 2 is a plan view of the memory cell of FIG. 1, and FIG. 3 is a structure in which the memory cell of FIG. 1 is formed. 4 is a cross-sectional view of the substrate of FIG. 3 after formation of the gate oxide and partial formation of the first gate member; FIG. 5 is a cross-sectional view of the substrate of FIG. 6 is a cross-sectional view of the substrate of FIG. 5 after the etching step used to form the spacers, and FIG. 7 is a cross-sectional view of the substrate of FIG. 5 after the first ion implantation, with the spacers removed. Later, after the formation of the second polysilicon gate, the cross-sectional view of the substrate of FIG. 6 in the second implantation step, FIG. 8 is the cross-sectional view of the substrate of FIG. 7 in the third ion implantation step, and FIG. 8 is a cross-sectional view of the substrate of FIG. 8 at another doping step after formation of a photoresist layer covering a portion of the substrate; FIG. 10...Substrate, 11...Gate oxide film, 12m
...Floating gate, 14 & ... Control gate, 13, 35.37 ... Edge, 16
&...source region, 18m, 18b...drain region, 22...silicon oxide film. a1M person Intel Corporation agent Masaki Yamakawa (Iυ^2 people) Drawing reference 11) (no changes to the contents), 7: I:I/j-Memes//TL payment procedure amendment °), Indication of the case 1932 patent application No. Z14Z'3, person making the amendment

Claims (1)

Claims: (1) spaced apart first and second regions of a first conductivity type formed in a silicon body and forming a channel in the body therebetween; and at least an edge of the first region; a first gate member surrounded by an insulator extending from the edge of the first region over the channel; a second gate member extending to an edge of the region and insulated from the body and the first gate member; a third region of a second conductivity type formed therein to provide a memory cell having an integrally formed selection device; memory cells that are permanently erasable. (2) The memory cell according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. 3. The memory cell according to claim 1, wherein the first and second gate members are made of polysilicon. (4) In the memory cell according to claim 3, the main body includes:
A memory cell characterized in that it is doped with a p-type dopant. (5) The memory cell according to claim 1 or 4,
A memory cell characterized in that the first region extends deeper into the body than the second region. (6) The memory cell according to claim 5, wherein the third region is a boron-doped region. (7) The memory cell according to claim 6, wherein the second gate member overlaps the second region. (8) In the memory cell according to claim 7, the portion of the second region formed by the second gate member overlapping the second region is shallower than the remaining portion of the second region. A memory cell characterized by: (9) A source region formed in a silicon body, a drain region formed in the body apart from the source region and forming a channel region therebetween, and completely surrounded by an insulator. First polysilicon
the source, the gate member forming a third region doped in the body between an edge of the first gate member and the drain region with a dopant opposite to that forming the source and drain regions; a first polysilicon gate member extending from over the region, over the channel, to a portion spaced apart from the drain region; and aligned with and formed over the first gate member;
and a second polysilicon gate member extending from the first gate member over the channel region until overlapping the drain region and insulated from the first gate member and the main body, integrally formed. CLAIMS 1. An electrically programmable and electrically erasable memory cell formed in a silicon body, characterized in that the memory cell has a selected device. (10) The memory cell according to claim 9, wherein the source and drain regions are n-type regions, and the third
A memory cell characterized in that the region is a p-type region. (11) A source region formed in a silicon body, a drain region formed in the body apart from the source region and forming a channel region therebetween, and completely surrounded by an insulator. First polysilicon
the source, the gate member forming a third region doped in the body between an edge of the first gate member and the drain region with a dopant opposite to that forming the source and drain regions; a first polysilicon gate member extending from over the region, over the channel, to a portion spaced apart from the drain region; and aligned with and formed over the first gate member;
a second polysilicon gate member extending from the first gate member over the channel region until overlapping the drain region and insulated from the first gate member and the main body; , realizing a memory cell having an integrally formed selection device extending deeper into the body than the drain region;
An electrically programmable and electrically erasable memory cell formed in a silicon body. (12) The memory cell according to claim 11, wherein the source and drain regions are n-type regions, and the third region is a p-type region.
A memory cell characterized in that it is a shaped region. (13) The memory cell according to claim 12, wherein the second
A memory cell characterized in that a portion of the drain region that overlaps with the gate member is shallower than the remaining portion of the drain region. (14) forming a first insulating layer on the silicon body; and forming at least the first edge of the first polysilicon gate member from the first polysilicon layer formed on the first insulating layer. depositing a second insulating layer to cover the exposed portion of the first insulating layer and the first gate member; and forming a spacer member adjacent to the first edge of the first gate member. etching the second insulating layer so that the spacer member protects a first region of the body under the spacer member from receiving dopant; doping the silicon body with a dopant of a type; removing the spacer member; and doping the first region with a dopant of a second conductivity type. doping the body with a dopant of the shape of the body; forming a second gate member insulated from the first gate member, forming a second polysilicon layer thereon and extending over the first region; forming source and drain regions in the body in registration with the second gate member, in a third doping step, having an integrally formed selective device. 1. A method of manufacturing an electrically programmable and electrically erasable memory cell formed in a silicon body, characterized in that the memory cell is realized. (15) The manufacturing method according to claim 14, including the steps of covering the drain region and further doping the source region so as to form a source region deeper than the depth of the drain region. A method for manufacturing memory cells. (16) The method of manufacturing a memory cell according to claim 14 or 15, wherein the dopant of the first conductivity type is an n-type dopant, and the dopant of the second conductivity type is a p-type dopant. (17) The method of manufacturing a memory cell according to claim 15, wherein the first doping step comprises arsenic implantation. (18) The method of manufacturing a memory cell according to claim 16, wherein the second dopant step comprises boron implantation. (19) The manufacturing method of a memory cell according to claim 14 or 15, wherein the second edge of the first gate member and the edge of the second gate member are formed in alignment with each other. Method.