KR20010006135A - Electrically erasable nonvolatile memory - Google Patents

Abstract

Highly scaled nonvolatile memory cells include cells formed in triple wells. The control gate is negative biased. In erasing, by positively biasing the P-well and drain (or source) in a particular voltage region, degradation and GIDL current due to hole trapping are reduced, resulting in a highly scaled technique.

Description

ELECTRICALLY ERASABLE NONVOLATILE MEMORY

Nonvolatile memory cells have the advantage of retaining the recorded information even after power is lost to the memory. Various other types of nonvolatile memory include erasable programmable read only memory (EPROM), electrically erasable and programmable read only memory (EEPROM), and flash EEPROM memory. The EPROM is not only electrically programmable by channel hot electron injection on the floating gate, but also erasable through exposure. A typical EEPROM has the same program functionality except that it is programmed and erased by electronic tunneling instead of optically erasable. Thus, the information is stored in these memories, maintained even when the power is turned off, and if necessary, erasing for reprogramming is possible with appropriate techniques. Flash EEPROMs become erased blocks, typically having better read access times than normal EEPROMs.

At present, flash memory has gained considerable popularity. For example, flash memory is often used to provide on-chip memory to microcontrollers, modems and SMART cards, etc., which are desirable for storing code that requires fast updating.

While flash memory and EEPROM are closely related, flash memory is desirable in many respects because smaller cells make them more economical. However, flash memory and EEPROM often have very similar cell attributes.

When the nonvolatile memory is erased, one or more cells are erased in one operation. While the control electrode and the substrate are grounded, a high amount of potential is applied to the cell source and / or drain. As a result, negative charges enter the source and / or drain regions on the floating gate by Fowler-Nordheim tunneling. This technique is effective when the floating gate electrode and the dielectric between the source and / or drain regions are very thin.

Many advantages arise with conventional erase techniques, including the possibility of reverse voltage breakdown between the source and / or drain regions and the substrate junction, causing hot hole trapping and reliability problems in the oxide. "Drain Avalanche and Hole Trapping Induced Gate Leakage in Thin Oxide MOS Devices" by IEEE Chang, et al., IEEE Electron device Letters, Vol. 9, 1988, pp. 588-90. To overcome this, some designers have used a so-called double diffused junction to enhance the junction substrate breakdown voltage. However, double diffused junctions have some disadvantages, including (1) additional cell size is required to reduce potential cell density, and (2) drain leakage has induced gate (GIDL) current. Has Another potential solution is to apply a small voltage to the source using a relatively high negative potential above the control gate. US Patent No. 5077691, "Flash EEPROM Array with Negative Gate Voltage Erase Operation" by Sameer S. Haddad et al. This alternately reduces the field with substrate bonding along the source.

However, the smaller the channel length, the more hole confinement is affected by the channel length. This effect is possibly explained in "fundamental limitation to the scaling of flash memory cells". IEDM 1995-331, 13.6.1-13.6.4, "Short Channel Enhanced Degradation During Discharge of Flash EEPROM Memory Cell", by Jian Chen et al. This article explains that during discharge, the holes created from band-to-band tunneling movement through the silicon-to-silicon dioxide interface are accelerated by the strong lateral electric field, obtaining sufficient energy to make the active heat holes. This article explains that a negative gate voltage pulls active column holes, drops them to the surface, and binds them to create an interface state. As the channel length decreases, the side field increases and exacerbates this effect.

This article suggests that the problem can be avoided by increasing the channel length. This solution is to counter long-term industrial trends where device scale flows into ever smaller sizes for smaller size and smaller cost, which is undesirable. Chen et al. Present another solution to the problem of applying a positive bias to the drain while discharging the cell from the source node. Although the results discussed in this article have improved the problem to some extent, some deterioration remains, even when this approach is used.

By using channel erasing with a voltage of 5V applied to the P-well and N-well, and a large negative voltage applied to the control gate, it is possible to reduce heat hole generation near the source region, improving reliability and gate disturbance tolerance. It is also proposed. See "A 5-V-Only 16Mb Flash Memory with Sector Erase Mode" by T. Jinbo et al., 1992 IEEE Journal of Solid-state Circuit, Vol27, No.11 November 1992 1547-1554. This requires a negative gate voltage that is about one third higher than in the drain erase case (Haddad et al. 5077691). Hsing-jen Wan et al., Proc. of IEEE VLSI Technology Symposium (Japan) May 1993, p. See “Suppressing Flash EEPROM Erase Leakage with Negative Gate Bias and LDD Erase Junction” on 81-2.

The inventors of the present invention believe that their approach is not sufficiently satisfactory and that there is a continuing need for an effective and scaled erase mechanism. Thus, the use of negative control gate potentials in conjunction with the EEPROM erase cycle yields a number of advantages, but does not allow the various drawbacks in the art to pursue these advantages.

The present invention generally relates to nonvolatile memories, in particular electrically erasable nonvolatile memories.

1 is a structural explanatory diagram of a cell arrangement for the first embodiment;

Fig. 2 is a structural explanatory diagram of the cell arrangement for the second embodiment.

Summary of the Invention

By the first aspect of the present invention, a nonvolatile memory cell is formed in a P-type region. The memory cell includes a pair of doped regions acting as source and drain formed in the P-type region, and a transistor having a floating gate and a control gate. The floating gate is erasable by electron tunneling from the floating gate to one of the doped regions. One of the P-type region and the doped region is independently biased by positive potential. The difference between the doped region bias and the P-type region potential is greater than zero and less than Vcc. The control gate is negatively biased.

According to a second aspect of the present invention, a method for erasing a memory cell having a control gate, a floating gate, a channel, and a pair of doped regions operating as drains and sources formed in alternating P-wells in the N-well is controlled. Negative biasing the gate. To subtract the P-well bias from the doped region bias is greater than zero and less than Vcc, one of the P-well and the doped region is negatively biased.

Referring to the drawings, throughout the several drawings, like reference features have been used for the same parts, and the memory cell 10 shown in FIG. 1 includes a control gate 12 and a floating gate 14. This structure is advantageously implemented on the semiconductor layer 30, which has an electrically insulated floating gate 14 placed thereon. However, no special cell structure is important, and the present invention has been implemented using various memory cell structures, including, for example, split gate and stack gate cell structures.

The substrate 30, which is a P-type semiconductor, includes a highly doped source region 16 and a highly doped drain region 18. Regions 16 and 18 also include lightly doped drain (LDD) extensions (not shown). Drain bias potential 24, substrate bias potential 26, source potential 20, and gate bias potential 36 are made to maximize the performance of the cell.

Cell 10 is readable and programmable using any conventional technique. The bias potential described in FIG. 1 is primarily for implementing Fowler-Nordheim tunneling of electrons from the floating gate 14 to the drain 18, as indicated by arrow " e ".

During erase, for example, with the floated source 20, the control gate 12 receives a negative voltage from -7 to -14V or at the same potential as the P-well potential. By keeping the control gate bias below -11V, the process of cell formation is made more compatible with standard logic processes.

Drain diffusion 18 and substrate 30 are biased to a positive potential near or higher than Vcc. Vcc is determined by the specific technology used. For example, the current technology may be 5.0 to 2.5V. This reduces the electric field across the junction between N + diffusion 18 and the substrate 30. The reduced GIDL current and side electric field prevent the acceleration of the hot holes trapped in the gate oxide under the floating gate 14. The drain 18 is preferably not biased to a higher voltage than the substrate 30 because the gate GIDL where the drain leakage is induced is somewhat problematic. In the present art, this means that the drain 18 bias is advantageously at least about 1 to 2 V, not higher than the substrate 30. S. Parke, et al .; See "Design for Suppression of Gate-induced Drain Leakage in LDD MOSFETs using a Quasi-two-Dimentional Analytical Model," in IEEE Transactions on Electron Devices, Vol. 39, p. 1694-1703, 1992. In addition, when the drain 18 bias significantly exceeds the substrate 30 bias, hot hole confinement occurs due to lateral junction field acceleration. In general, it is preferred that the drain 18 bias minus the substrate 30 bias is greater than zero and less than Vcc.

The ability to apply a negative voltage to the substrate 30 is facilitated by using the P-well 30 embedded in the N-well 32, as shown in FIG. P-well voltage 26 is preferably equal to or less than N-well voltage 28 to avoid P-well / N-well forward bias. Therefore, by applying a positive voltage of Vcc or more to the P-well 30, the N-well 32, and the drain 18, the heat hole confinement induced by the GIDL when the drain 18 voltage becomes Vcc or more. Can be removed. Source potential 20 may be allowed to float. It is desirable that the drain bias minus the P-well bias is greater than zero and less than Vcc.

The voltage across the capacitor 33 is the difference between the potential of the opposite floating gate 14 and the potential of the diffusion 18 and the P-well 30. When this difference exceeds 8 to 10 V, sufficient tunneling current is generated and the floating gate 14 is erased at a negative potential in a time frame of several milliseconds to several seconds depending on the thickness of the tunneling oxide 42. Can be.

The electrons are tunneled to the drain region 18 (drain erase). The tunneling current is affected by the voltage from the floating gate 14 to the drain 18. However, by biasing the source 16 in the format described for drain 18, a source erase mechanism is provided instead of the drain erase mechanism. During source erase, the drain potential is allowed to float.

Cells 10 and 10a are formed using conventional process techniques such as dual poly, single metal CMOS processes. Exemplary parameters are stated in this text, considering a minimum wiring width of 0.35 μm or less with a Vcc potential of 1.8 V. As smaller minimum wiring widths and lower voltage techniques are allowed, the parameters of the dual eye are scaled accordingly.

The starting substrate material is typically P-type (100) silicon, for example having a resistance in the range of 10-20 Ωcm. P-well 30 is embedded in N-well 32 in a so-called triple well process. P-well 30 has a typical well depth (eg, 2-4 μm) at an average doping concentration (eg, atoms per 1 × 10 ¹⁶ to 5 × 10 ¹⁶ 3 square centimeters). Triple wells are formed by back doping the N-well 32 with the P-well 30.

N-well 32 has a typical well depth of, for example, 4-8 μm. Doping concentrations are atoms per 4 × 10 ¹⁵ to 1 × 10 ¹⁶ 3 square centimeters. Triple wells are formed by back doping the N-well 32 with the P-well 30.

The device formation in the triple well is as follows. Injection of the N-well is done, for example, with phosphorus (P31) of atoms per 1 × 10 ¹³ square centimeters, typically with energy from about 160 to 100 KeV. Injection of the N-well is typically pursued using a high temperature step which is 6-12 hours at 1125-1150 [deg.] C. Next, the N-well 32 is back doped with P-well injection. Typical dosages for P-well injections may be atoms per 1.5 × 10 ¹³ to 2.5 × 10 ¹³ square centimeters using species such as boron (B11) with energy between 30 KeV and 180 KeV. Next, the N-well 32 and the P-well 30 are typically sought at 1125 to 1150 ° C. for 6 to 10 hours. This allows the well of the desired doping concentration and depth to be set.

After well formation, standard insulators and field oxides are formed using standard logic field processes. Field oxide thickness and field doping are applied minutely to meet cell program requirements. After this, memory cell injection is performed. For example, injection of B (11) performed at atoms per unit injection amount of 1.0 to 3.5 × 10 ¹³ square centimeters at 30 to 50 KeV is completed through the sacrificial oxide. Next, a gate is formed. For example, 85-100 angstrom dry oxides are grown across the wafer. The dry oxide is grown at 900 ° C in partial oxygen by, for example, 975 to 1050 ° C annealing.

The floating gate 14 is then formed of polysilicon, silicide or metal. If polysilicon is used, it may be POCL 3 doped at 1600 angstroms thickness and 870 to 1000 ° C. The interpoly dielectric is formed of an oxide-nitride-oxide sandwich (ONO), has a bottom oxide that is 60 to 80 angstroms, the nitride layer has a thickness of 90 to 180 angstroms, and the top oxide is 30 to 40 angstroms. Next, polysilicon (poly 2) to the control gate 12 is deposited and, if desired, silicided. Using standard self-aligned gate etching techniques, the gates are patterned and defined.

With the completion of the structure of these capacitors and transistors, all subsequent processes for the contacts and interconnect layers follow a standard logic post-process.

It is particularly preferable that the present invention has a technology of Vcc of less than .35 µm minimum wiring width and of 3.3 V or less. At this size, GIDL creates a hole trapping problem that has an adverse effect on reliability, and a drain leakage source that has an adverse effect on power supply. Therefore, it is desirable to have a condition that reaches the smallest minimum wiring width and minimizes GIDL. This can be achieved by equalizing the P-well and drain bias voltages. However, this disadvantages the erase current. By making the P-well voltage and drain voltage possible to be different voltages, GIDL leakage current can be tolerated, but can improve the P-well potential for tunneling cancellation. Thus, the P-well potential can be chosen to allow a small negative control gate voltage to achieve the best GIDL and erase conditions. The lower the control gate potential is made, the more compatible the technology is in standard logic processes.

A plurality of parameters and levels have been provided in the foregoing specification, and those skilled in the art will recognize that the parameters and levels are for illustrative purposes only. This means that the appended claims are within the scope of the invention and all changes and modifications.

Claims (15)

In a nonvolatile memory cell formed in a P-type region, A transistor having a floating gate, a control gate, and a pair of doped regions operating as a source and a drain formed in said P-type region; And A positive bias is applied to one of the P-type region and the doped region to apply a negative bias on a control gate so that the difference between the doped region bias and the P-type region bias is greater than zero and less than Vcc. Wherein the floating gate is erasable by electrons tunneling from the floating gate to one of the doped regions. The cell of claim 1, wherein the N-well is positively biased. The cell of claim 1, wherein the P-type region and the doped region are biased above Vcc but below N-well bias. The cell of claim 1, wherein the P-type region is a P-well embedded in an N-well. The cell of claim 1, wherein the drain is a biased doped region. A method for erasing a memory cell having a control gate, a floating gate, a channel, and a pair of doped regions acting as drains and sources formed in P-wells alternately formed in N-wells, Negative biasing the control gate; Positive biasing the P-well; And And positively biasing one of the doped regions so that subtracting the P-well bias from the doped region bias is greater than zero and less than Vcc. 7. The method of claim 6 including causing electrons to discharge into the doped region. 7. The method of claim 6 including positive biasing the N-well. 7. The method of claim 6 including biasing the doped region at least about Vcc. 7. The method of claim 6 including biasing the P-well above about Vcc. 7. The method of claim 6 including biasing the N-well above about Vcc. 7. The method of claim 6 including biasing the control gate to a negative potential of less than -11V. 7. The method of claim 6 including making the potential difference between the doped region and the P-well bias about 1 to 2V. 7. The method of claim 6 wherein the drain is a biased doped region. 7. The method of claim 6 including biasing the doped region and the P-well to a potential that is less than or equal to the P-well bias potential.