JPH10335504A - Non-volatile memory cell and its erasing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile memory cell which can be electrically erased and measured freely. SOLUTION: This non-volatile memory cell, which can be measured freely, has a cell formed in a tripple well. Negative bias can be applied on a control gate 12. A GIDL(gate induction drain leakage) and the deterioration caused by Hall seizure can be reduced by applying positive bias in the specific voltage range, and the technique, with which scale can be changed freely, can be accomplished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile memory and a memory cell erasing method, and more particularly to an electrically erasable nonvolatile memory.

[0002]

2. Description of the Related Art Non-volatile memories have the advantage of retaining the information stored therein even when the power thereto is turned off. Erasable and programmable RO
M (EPROM (erasable programmable read only me
mory)), electrically erasable and programmable R
OM (EEPROM (electrically erasable and prog
rammable read only memory)), and flash EE
There are several different types of non-volatile memory, such as PROM memory (flashEEPROM memory). EPR
The OM is erasable by exposure to light, but is electrically programmable by injecting channel electrons into the floating gate. Conventional EEPROMs have the same programmable function, but instead of being erasable by light, are erased and programmed by electron tunneling. This allows information to be stored in these memories, even when power is turned off, and may be erased, if necessary, to reprogram the memory using appropriate techniques. Flash EEPRO
M is a block erased, typically a normal EEPROM
Gives better read access time than

Recently, flash memories have gained considerable popularity. For example, flash memory is often used in providing on-chip memory, such as small controllers, modems, and SMART cards where it is desirable to store code that requires fast updates.

[0004]

Although flash memory and EEPROM are closely related, flash memory is often preferred. The reason is,
This is because flash memory has smaller cells and can be manufactured more economically. However, flash memories and EEPROMs often have very similar cell characteristics.

When an EEPROM is erased, one operation erases one or more cells. A high positive potential is applied to the source and / or drain of the cell while the control electrode and the substrate are at ground potential. As a result, negative charges on the floating gate are directed to the source and / or drain regions by the Fowler-Nordheim tunneling phenomenon. This technique is effective where the dielectric between the floating gate electrode and the source and / or drain regions is very thin.

[0006] A number of disadvantages exist with conventional erase techniques. One of these is the fact that reverse voltage breakdown between the source and / or drain and substrate junctions may occur, which may cause hot hole oxide trapping and reliability problems. . In this regard, Volume 9 of the IEEE Electronic Device Letter (199)
8), pp. 588-90, a paper entitled "Drain Avalanche and Hole Trapping Induced Gate Leakage in Thin Oxide MOS Devices". To overcome this, some designers have used so-called double diffused junctions to increase the junction substrate breakdown voltage. However, double diffusion bonding has certain disadvantages.
Its disadvantages are (1) the fact that double diffusion junctions need to increase cell size, which can reduce the potential cell density possible, and (2) double diffusion junctions still have a gate. Induced drain leakage (GIDL (Gate
Induced Drain Leakage)) having current. Another possible solution is to use a relatively high negative potential on the control gate to apply a smaller voltage to the source. In this regard, U.S. Pat. No. 5, entitled "Flash EEPROM Array with Erase Operation with Negative Gate Voltage", by Haddad et al.
No. 077,691. This progressively reduces the electric field across the source / substrate junction.

[0007] However, as the channel length becomes smaller, this hole capture becomes dependent on the channel length. This effect has been described as a possible "basic limit on flash memory cell scaling". In this regard, Chen et al., IEDM 1995-33.
This will become clearer with reference to “Short channel expansion deterioration upon discharge of flash EEPROM memory cell” described in 13.6.1 to 13.6.4 of No. 1.
This paper states that during discharge pressure, holes created by band-to-band tunneling movement through the silicon dioxide-to-silicon dioxide interface are accelerated by strong lateral electric fields into active hot holes. It has been shown to gain sufficient energy.
Also, according to the description in this paper, a negative gate voltage pulls these active hot holes into the gate, which strikes the surface and is trapped, creating an interface state. Also, as the channel length decreases, the horizontal electric field increases, and the effect deteriorates.

The above article proposes that the problem may be avoided by increasing the channel length. This solution goes against the longstanding industry trend of making devices smaller and making them smaller, lower cost products,
This solution is not particularly desirable. Chen and colleagues propose another solution to the above problem by applying a positive bias to the drain while discharging the cell from the source node. Although the results discussed in the above paper show that this can be improved to some extent, it appears that some degradation remains even when this approach is used.

By using a channel erase while applying a large negative voltage to the control gate and applying a voltage of 5 volts to the P-type well (P-well) and the N-type well (N-well), It is also noted in the above article that gate disturbance tolerance and reliability are improved due to reduced hot hole generation near the region. In this regard, 19
Published in November 1992, IEEE 1992 on solid state circuits
1547-1 in E-journal Vol.27, No.11
Reference may be made to the article on page 554 entitled "5 Volt Only 16 Mb Flash Memory With Sector Erase Mode" by Jimbo et al. This is about one time less than when drain erasing.
A negative gate voltage is required which is higher by a factor of / 3 (see US Pat. No. 5,077,691 to Haddad et al.). In this regard, Wang et al., On page 81-2 in the proceedings of the IEEE VLSI Technology Symposium (held in Japan) in May 1993, describe "Flash EE with negative gate bias and LDD erase junction."
It will be clear from reference to a paper entitled "Control of PROM Erase Leakage."

The inventor of the present invention is convinced that none of these approaches are fully satisfactory and that there is a continuing need for an erasing mechanism that can be effectively scaled freely. doing. Thus, while those skilled in the art have acknowledged the numerous advantages that result from using a negative control gate potential with respect to the EEPRO erase cycle, various shortcomings have discouraged those skilled in the art from pursuing advantages.

[0011]

The present invention provides a nonvolatile memory cell which can solve the above-mentioned problems. The non-volatile memory cell includes a transistor having a floating gate formed in a P-type region, a control gate, and a set of doped regions formed in a P-type well serving as source and drain. Is also provided. The floating gate can be erased by a phenomenon of electron tunneling from the floating gate to one of the set of doped regions. The P-type region and the one region are separately positively biased. Doped region bias and P
The potential difference from the potential of the mold region is less than VCC and greater than zero. The control gate is negatively biased.

Further, the present invention can solve the above problems,
Erasing a memory cell having a control gate, a floating gate, a channel, and a set of doped regions formed in a P-well formed sequentially in an N-well and serving as a source and a drain. Provide a way to The method includes the step of negatively biasing the control gate. The P-well and one of the set of doped regions are positively biased, but the bias of one of the doped regions minus the P-well bias is less than Vcc and Should be greater than zero.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. However, in some drawings, similar components are denoted by the same reference numerals. The memory cell 10 shown in FIG. 1 includes a control gate 12 and a floating gate 14. This structure is advantageously configured with the electrically insulated floating gate 14 located on the semiconductor layer 30. However, this particular cell structure is not limited to this, and the present invention
It can be implemented using different cell structures with different split and stacked gates.

The substrate 30 may be a P-type semiconductor and has a heavily (fully) doped source region 16 and a heavily doped drain region 18. These areas 16,
18 may also have a lightly doped drain (LDD) extension (not shown). Drain bias potential 24, substrate bias potential 26, source potential 2
0 and the gate bias potential 36 are set to maximize cell performance.

Cell 10 may be read and programmed using any known techniques. FIG.
The bias potential shown in FIG. 3 is for realizing the Fowler-Nordheim tunneling phenomenon of electrons (indicated by the arrow "e") from the floating gate 14 to the drain 18 mainly.

During erasure, control gate 12 is throttled to a negative potential from -7 to -14 volts, for example, with source 20 floating or at a potential equal to the potential of the P-well. Control gate bias-
By maintaining the voltage below 11 volts, the process for forming the cell can be more compatible with standard logic operations.

With respect to drain diffusion region 18 and substrate 30, they are biased to a positive potential near or above Vcc. Vcc is determined by the particular technology used. For example, in the current technology, it is 5.0 to
It can be 2.5 volts. This gives N ⁺
The electric field across the junction between diffusion region 18 and substrate 30 is reduced. Due to reduced GIDL (gate induced drain leakage) current and lateral electric field, floating gate 14
Acceleration of hot holes trapped in the underlying gate oxide is suppressed.

With respect to the drain 18, the substrate 30 is brought to an extent that gate induced drain leakage (GIDL) is a problem.
It is not preferable to bias to a higher potential. According to the state of the art, this means that it is not advantageous for the bias of the drain 18 to be higher than the substrate 30 by about 1 to 2 volts. In this regard, "Using a quasi-two-dimensional analysis model," IEEE Transactions on Electronic Devices (1992) 39, pp. 1694-1703.
Park et al., Entitled "Designing to Suppress Gate-Induced Drain Leakage in LDD MOSFETs." In addition, if the bias at the drain 18 greatly exceeds the bias at the substrate 30, hot hole trapping may occur due to lateral junction field acceleration. In general, it is preferable that the value obtained by subtracting the bias of the substrate 30 from the bias of the drain 18 is greater than zero and less than Vcc.

As shown in FIG. 2, an N-well
l) By using the P-type well (P-well) 30 buried in 32, it becomes easy to apply a positive voltage to the substrate 30. The voltage 26 of the P-type well 30 is preferably equal to or lower than the potential 28 of the N-type well 32 in order to avoid a forward bias of the P-type well / N-type well. Thus,
By allowing a positive voltage Vcc or higher to be applied to the P-type well 30, the N-type well 32 and the drain 18 while allowing the voltage at the drain 18 to rise to a voltage above Vcc, GIDL allows The trapping of the induced hot holes can be eliminated. Floating the source potential 20 is allowed. The value obtained by subtracting the bias of the P-type well from the drain bias is preferably greater than zero and less than Vcc.

The voltage on capacitor 33 is the difference between the potential on one side floating gate 14 and the potential on diffusion region 18 and P-type well 30. When the potential difference exceeds 8 to 10 volts, a sufficient tunneling current is generated, and depending on the thickness of the tunneling oxide 42, the floating gate 14 is brought to a negative potential within a time frame of a few milliseconds to a few seconds. Can be erased.

The electrons tunnel to the drain region 18 (drain erasure). The tunneling current is applied to the floating gate 1
4 to the drain 18. However, the source 1 in the illustrated manner for the drain 18
By biasing 6, a source erase mechanism may be provided instead of a drain erase mechanism. During source erase, the drain potential may be floating.

Cells 10 and 10a have a double poly, single metal CMOS p process.
may be formed using conventional techniques such as rocess). The set of exemplary parameters already described herein completes a 0.35 μm thick or smaller feature size with a Vcc potential of 1.8 volts. According to the present technology, it is permissible to further reduce the voltage and the feature size, but the parameters are proportional in magnitude accordingly.

The starting substrate material is generally a P-type (10-10 ohm.cm) resistivity, for example.
0) Silicon. The P-type well 30 is an N-type well 32 in a so-called triple well process.
Embedded inside. The P-well 30 has a doping concentration in the range of, for example, 1 × 10 ¹⁶ to 5 × 10 ¹⁶ atoms per cubic centimeter, and typically has a depth of, for example, 2 to 4 μm.

The N-type well 30 is generally, for example, 4 to 8
It has a depth of μm. The doping concentration is in the range of 4 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms per cubic centimeter. The triple well is formed by counterdoping the P-well 30 into the N-well 32.

The formation of the element in the triple well is performed as follows. Implantation of N-type well 32 (implan
t) is, for example, 1 to 1.5 × 10 ¹³ per cubic centimeter.
The irradiation dose (dose) of one atom is from 160 keV to about 1
This is done using phosphorus (P ₃₁ ) having an energy of up to 00 keV. The implantation of the N-type well 32 is 1125 to 11
It is carried out using a high temperature step at 50 ° C., generally for 6 to 12 hours. After that, the N-type well 32 becomes the P-type well 3
Counter-doped by implantation of zero. A typical dose for implanting a P-type well 30 is boron (B
Using species such as ₁₁ ), 1.5-2.5 × 10 ¹³ atoms per cubic centimeter can be achieved with energies of 30-180 keV. The N-type well 32 and P-type well 30 are then generally
Placed at 150 ° C. This allows the well to have the desired doping concentration and depth.

After the wells have been formed, the formation of field oxides and field insulators is performed using standard logic field processing. The field oxide thickness and field doping are slightly adjusted to meet the programming requirements of the cell. After this formation, implantation of the memory cells may be performed. For example, the irradiation amount of 1.0 to 3.5 × 10 ¹³ atoms per cubic centimeter is increased by 30 to 50 through the anticorrosion oxide.
with an energy of kev may perform implantation of B _11. Thereafter, a gate is formed. For example, 85-100 Å of dry oxide may be grown across the wafer. Dry oxide is, for example, 975 to 10
Grow at 900 ° C. in partial oxygen before annealing at 50 ° C.

Thereafter, the floating gate 14 is made of polysilicon,
It may be formed from silicides or metals. If polysilicon is used, it may be 1600 thick, 870-
POCL3 doped at 1000 ° C. can be used. The interpoly dielectric is formed from an oxide-nitride-oxide sandwich (ONO), with the underlying oxide having a thickness of 60-80 Angstroms and the nitride having a thickness of 90-180 Angstroms. And the upper oxide is 30 to 40 angstroms thick. If necessary, the control gate 12 polysilicon (POLY2) may be subsequently deposited and silicided. The gate is patterned and configured using standard self-aligned gate etching techniques.

Once these capacitors and transistors are completed, all subsequent processing for contacts and interconnects will be standard logic rear end processing.
ocessing).

The present invention operates at a Vcc of less than 3.3 volts.
Particular preference is given to techniques having a characteristic size of a thickness of 35 μm or less. But at these sizes,
GIDLs create hole trapping problems that have a detrimental effect on reliability and cause drain leakage that has a detrimental effect on power supplies. Therefore, it is desirable to minimize GIDL so that the minimum characteristic size can be reached even under these conditions. This is made possible by making the P-well and drain bias the same. However, this disadvantages the erase current. According to the present invention, by enabling the P-type well voltage and the drain voltage to be different voltages, the GID can be optimized while optimizing the potential of the P-type well for tunneling erase.
L leakage current can be acceptable. Thus,
The P-type potential can be selected to allow for a smaller negative control gate voltage while still providing excellent GIDL and erase conditions. Lower control gate potentials make the technology more compatible with standard logic operations.

Although a number of parameters and levels have been described in the foregoing description, those skilled in the art will recognize that these parameters and levels are for illustrative purposes only. Also, any changes and modifications within the requirements of the claims are included in the true spirit and scope of the present invention.

[0031]

As described above, according to the present invention, an electrically erasable nonvolatile memory can be provided. Also, by applying a positive bias to the P-well and drain (or source) within a certain voltage range during erase, degradation due to GIDL current and hole trapping can be reduced, thus reducing the scale. A technique that can be changed freely is achieved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a cell configuration according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a cell configuration according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 12 control gate 14 floating gate 16 source region 18 drain region 30 P-type well 32 N-type well 33 capacitor 20, 24, 26, 28, 36 bias 42 oxide

Claims (15)

[Claims] 1. A non-volatile memory cell formed in a P-type region, comprising: a floating gate, a control gate, and a set of doped regions formed in the P-type well and serving as a source and a drain. The floating gate can be erased by a phenomenon of tunneling of electrons from the floating gate to one of the set of doped regions by the P-type region; While applying a negative bias to the gate,
The one of the set of doped regions is positively biased such that the potential difference between the bias of the doped region and the bias of the P-type region is less than Vcc and greater than zero. A nonvolatile memory cell characterized by being configured as described above. 2. The non-volatile memory cell according to claim 1, wherein said N-type well is positively biased. 3. The non-volatile memory cell of claim 1, wherein said P-type region and said doped region are biased above Vcc and below the bias of an N-type well. 4. The nonvolatile memory cell according to claim 1, wherein said P-type region is a P-type well embedded in an N-type well. 5. The non-volatile memory cell according to claim 1, wherein said drain is a biased doped region. 6. A control gate, a floating gate,
A method for erasing a memory cell comprising a channel and a set of doped regions formed in a P-type well formed in an N-type well and acting as a source and a drain, comprising: Applying a negative bias; (b) applying a positive bias to the P-type well; and (c) subtracting the bias of the P-type well from the bias of the doped region is less than Vcc; Applying a positive bias to one of the doped regions to be greater than zero. 7. The method as claimed in claim 6, further comprising the step of discharging electrons to the doped region. 8. The method according to claim 6, further comprising the step of applying a positive bias to said N-type well. 9. The method of claim 6, further comprising the step of applying a bias to the doped region at approximately Vcc or higher. 10. The method of claim 6, further comprising the step of applying a bias to the P-type well at approximately Vcc or higher. 11. The method according to claim 6, further comprising the step of applying a bias to the N-type well at approximately Vcc or higher. 12. The method according to claim 6, further comprising the step of: biasing the control gate to a negative potential of less than -11 volts. 13. The memory of claim 6, further comprising the step of making the potential difference between the bias of the doped region and the bias of the P-type well equal to a value between about 1 volt and 2 volts. Cell erase method. 14. The method of claim 6, wherein the drain is the biased doped region. 15. The method of claim 6, further comprising the steps of: biasing the P-type well; and biasing the doped region at a potential less than or equal to a bias potential of the P-type well. Memory cell erasing method.