3674twf.doc/008 A7 B7 五、發明说明（I ) 本發明是有關於一種溝渠隔離區(Trench Isolation)的製 造方法，特別是有關於一種改良的溝渠隔離區的製造方 法。其係利用基底上多沉積一層氧化層與多晶砂層，可以 完全消除習知的凹陷問題（Dishing Effect)。 在半導體製程上，習知常用的一種隔離結構爲淺溝渠 隔離區（Shallow Trench Isolation ; STI)，目的是用以隔離 出後續形成元件的主動區域。其形成方式是利用非等向性 的蝕刻法（Anisotropic Etching)，在半導體基底中挖出溝 渠，然後在此溝渠中塡滿氧化物，因而形成了元件隔離區。 相鄰的金氧半電晶體(Metal Oxide Semiconductor ; MOS)元 件之間，都以此溝渠隔離區來隔離。 第1A圖至第1D圖係繪示習知一種溝渠隔離區的製 造方法剖面示意圖。 請參照第1A圖，首先，提供半導體基底105，其上 覆蓋墊氧化層107，然後，利用化學氣相沉積法（Chemical Vapor Deposition : CVD)，在此墊氧化層107上形成氮化 矽層111，然後在氮化矽層111上形成具溝渠圖案之光阻 層（圖中未顯示）。接著，以光阻層爲罩幕進行蝕刻步驟， 蝕刻氮化矽層111、墊氧化層107與半導體基底105，在 半導體基底105中形p溝渠Π2的結構。然後，將此光阻 層去除。 請參照第1B圖，利用化學氣相沉積法形成一層氧化 矽層113將溝渠112 —滿。 請參照第1C圖，接著，在氧化矽層113上形成光阻 本紙張尺度適用中國固家榇芈（CNS ) A4規格（210X297公釐） (請先閲讀背面之注^^項再填寫本頁) 訂' 經濟部中央標準局貝工消费合作社印装 3674t\vi*.doc/008 A/ _B7 __ 五、發明説明（7 ) 層（未繪示於圖中）’定義光阻層的圖案，用以做爲反向定 義之罩幕，再進行非等向性蝕刻步驟，蝕刻部份氧化矽層 113，形成如圖示之氧化矽層113a。然後，再去除光阻層， 露出氧化矽層113a，對應於主動區的氧化矽層113已被部 份剝除。最後’進行化學—械硏磨法（Chemical Mechanical Polish ; CMP)，以氮化矽層111爲終止層（Stop Layer)，硏 磨氧化砂層113a直到與氮化砂層ill上方約50nm之高 度，但由先前以光阻層爲罩幕，進行非等向性的蝕刻步 驟時，因缺乏良好的蝕刻終止層，導至氮化矽層111上方 之氧化矽層殘餘的厚度不均勻，產生蝕刻均勻性不 佳的情況，使得進行化學機械硏磨時，無法準確地控制所 欲保留之厚度。 請參照第1D圖，再以溼蝕刻法去除氮化矽層111、 墊氧化層107與部份之氧化矽層113a，希望使基底表面爲 一平整的表面，以完成溝渠隔離區115的結構。 經濟部中央標準局貝工消費合作社印裝 ^n' aian ϋ— HI m m m ΙΛ ϋ— ϋ I HI 11 ·Βϋ (請先Bg-讀背面(V注意事項再填寫本頁) 但由於氮化矽層Π1上方之氧化矽層113a殘餘的厚 度不均勻，因此，在此種蝕刻均勻性不佳的情況下，若再 以蝕刻法去除氮化矽層Π1 '墊氧化層1〇7與部份之氧化 矽層,113a，則無法得到一表面平整的基底1〇5。 因此本發明的主要目的就是在提供一種溝渠隔離區的 製造方法，對氧化矽層進行非等向性蝕刻_，能有一良好 的蝕刻終止層，以得到較好的蝕刻均勻度’於後續製程中’ 才可以得到一表面平整的基底，以利製程之/進行。 爲達成本發明之目的，提出一種溝渠隔離i的製造方 4 本紙張尺度適用中國國家揉準（CNS ) Λ4規格（210X297公釐） 3674t\vf.doc/008 A7 B7 經濟部中央標準局負工消费合作社印製 五、發明説明（3 ) 法’提供一半導體基底，其上依序形成墊氧化層、氮化矽 層、”回蝕刻氧化層”與多晶矽層，定義多晶矽層、氧化層、 氮化砂層 '墊氧化層與半導體基底，用以在半導體基底中 形成溝渠。接著’形成一層，，回塡氧化層，，將溝渠塡滿。之 後’以多晶矽層爲蝕刻終止層，剝除主動區的氧化層，使 多晶砍層完全暴露出，由於此多晶矽層對，，回塡氧化矽層” 具有遠大於一的蝕刻選擇率，可做爲蝕刻的終止層，使得 蝕刻後可擁有較佳的厚度均勻度，故能改善現有製程均勻 度不佳的問題。接下來具有較佳厚度均勻度之”回蝕刻氧 化層”與多晶矽層可當作化學機械硏磨之緩衝，因爲此多 晶矽層對氧化矽的硏磨選擇率接近一，所以在硏磨時不致 產生製程上的差異，故可使主動區的表面平坦度較均勻。 而於進行硏磨時，此多晶砂層將完全去除，且於氮化砂層 上方一特定高度爲止，以蝕刻法依序去除氧化層、氮化矽 層、墊氧化層與部份之氧化層，使基底形成爲一平整的表 面，以完成溝渠隔離區。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式’作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1D圖係繪示習知一種溝療隔離區的製 造方法剖面示意圖； 第2A圖至第2F圖係根據本發明之一較隹實施例’一 種溝渠隔離區的製造方法剖面示意圖；以及 請 先 聞- 讀 意 事 項 再 旁 訂 本纸張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） 3674twf.doc/0〇8 A7 B7 五、發明説明（κ) 第3圖係根據本發明之一較佳實施例，於較薄的多晶 砂層上形成一層保護層後的溝渠隔離區剖面示意圖。 圖式之標記說明： , . (請先閲讀背面之注意事項再填寫本頁) 105、250 :基底 107、252 :墊氧化層 1Π、254 :氮化矽層 112、 260 :溝渠 113、 113a、256、262、262a、262b、262c :氧化層 115、265 :溝渠隔離區 258:多晶矽層 261 :主動區 270:特定高度 3〇〇 :保護層 實施例 第2A圖至第2E圖係根據本發明之一較佳實施例，一 種溝渠隔離區的製造方法剖面示意圖。 經濟部中央橾率局貝工消费合作杜印製 請參照第2A圖，首先，提供半導體基底250，比如 是矽基底，其上覆蓋墊氧化層252,例如厚度約50A〜200A。 然後，在此墊氧化層2W上形成氮化矽層254，例如，利 用化學氣相沉積法、厚度約500A〜2500A。再形成一層氧 化層256於氮化矽層2〗4之上，例如，厚度約500A〜2000A。 之後’形成一多晶矽層258於氧化層256之上，例如，利 用化學氣相沉積法，厚度約300A。 此一多晶砂層258必須有足夠厚度，因爲後續在溝渠 6 敢从埴用中囷國家揉準（CNS >八4胁（210X297公釐） 3674iwf.doc/008 A, _^__B7______ 五、發明説明（t) 隔離區被定義出來後，會有一道氧化步驟來形成襯氧化層 (未繪示於圖中）於溝渠隔離區與基底250的接觸界面，如 果多晶矽層258厚度不夠，則可能在襯氧化層形成的同時， 被氧化爲氧化砂，使得無法利用、多晶砂與氧化砂間的高蝕 刻比來進行後續以多晶矽P 258爲蝕刻終點的製程。 或是可以只形成一層較薄的多晶矽層258，例如，厚 度約50A〜100A，如第’3圖所示，第3圖中其他標號的意 義與第2A圖同。再於此層較薄的多晶矽層258上形成— 層厚度約100A之保護層300，例如氧化矽材質，來保護 較薄的多晶矽層258，使得後續在形成襯氧化層的同時， 多晶矽層258不會被氧化爲氧化矽。 請參照第2B圖’然後在多晶矽層258上方形成—具 溝渠圖案之光阻層(未繪示於圖中）。接著，進行触刻步驟， 依序蝕刻多晶矽層、氧化層256、氮化矽層254、墊氧 化層252與半導體基底250，在半導體基底25〇中形成溝 渠260，以定義出元件主動區201。然後，將此光阻層去 除。 經濟部中央揉率局貝工消费合作社印装 ---------cI- (請先M-讀背面之注意事項再填寫本頁) 請參照第2C圖，接著’形成一層氧化層262將溝渠 26〇塡滿’其材質比如是氧化砂’其形成方法例如利用化 學氣相沉積法。 請參照第2D圖’形成一層光阻層（圖中未顯示）覆蓋 對應於溝渠260上方之氧化層262上。接_著，以此光阻層 爲罩幕’多晶政層2 5 8爲触刻終止層’進行触刻步驟，例 如以非等向性蝕刻’蝕刻未被光阻層覆蓋之氧化層262， 7 本紙張纽適用中國國家揉準（CNS ) A4胁Γ^Χ297公釐) '-- 3674tw l.doc/008 A7 B7 五、發明説明（& ) 如果先前於多晶砂層258之上有形成一層防止多晶矽層 258被氧化的保護層3〇〇 (如第3圖所示），則此蝕刻步 驟會同時去除多晶砂層258上之保護層300 晶矽層258，使主動區的表面平坦度較堉勻 ，以綦露出多 並使氧化層 阻層，使溝渠260 經濟部中央標準局貝工消费合作社印¾ 262轉爲氧化層262a。然锋，再去除此光 的氧化層262a凸出基底250之表面。 請參照第2E圖’然後，進行化學也械硏磨法，磨除 部份氧化層262a和多晶矽層258後，暴露出氧化層256， 繼續以氮化矽層254舄終止層，硏磨氧化層256，直到氮 化砂層254上方一特定高度270爲止，例如，氮化矽層上 方〇A〜5〇oA。此時，便可得到一完整的表面。 習知的做法是硏磨到完全暴露出氮化矽層254爲止， 但由於化學機械硏磨法可能造成氧化層262b表面有微刮 痕產生’如果完全硏磨到暴露出氮化矽層254爲止，則微 刮痕也同時深入氧化層262b內部，造成後續以_刻法去 除墊氧化層後252 ’仍殘留微刮痕於半導體基底名表面。 因此本發明只要所硏磨的表面已經夠平整，便可以停 止硏磨，使氮化矽層254上方保留一層氧化層256a，因硏 磨的時間不會太長，使氧化層262b表面微刮痕之深度不 會靠近半導體基底250之表面，且避免了習知因爲蝕刻均 勻度不佳而無法得到一平整的表面來促進後續以蝕刻，後 續完成蝕刻製程之後，可以完全消除微刮痕。 請參照第2F圖，接著再去除氧化層256a、氮化矽層 254 '墊氧化層252與部份之氧化層262b，其方法比如是 請 先 閱. 意 事 項 再 旁3674twf.doc / 008 A7 B7 V. Description of the Invention (I) The present invention relates to a method for manufacturing a trench isolation area, and more particularly to a method for manufacturing an improved trench isolation area. It uses an additional oxide layer and polycrystalline sand layer deposited on the substrate, which can completely eliminate the conventional Dishing Effect. In semiconductor processes, a commonly used isolation structure is a shallow trench isolation region (Shallow Trench Isolation; STI), which is used to isolate the active area of the subsequent formed elements. Its formation method is to use anisotropic etching (Anisotropic Etching) to dig a trench in a semiconductor substrate, and then fill the trench with an oxide, thereby forming an element isolation region. Adjacent Metal Oxide Semiconductor (MOS) devices are isolated by this trench isolation area. Figures 1A to 1D are schematic cross-sectional views showing a conventional method for manufacturing a trench isolation area. Referring to FIG. 1A, first, a semiconductor substrate 105 is provided, and a pad oxide layer 107 is covered thereon. Then, a silicon nitride layer 111 is formed on the pad oxide layer 107 by a chemical vapor deposition method (Chemical Vapor Deposition: CVD). Then, a photoresist layer (not shown) with a trench pattern is formed on the silicon nitride layer 111. Next, the photoresist layer is used as a mask to perform an etching step, and the silicon nitride layer 111, the pad oxide layer 107, and the semiconductor substrate 105 are etched, and a p-channel Π2 structure is formed in the semiconductor substrate 105. Then, this photoresist layer is removed. Referring to FIG. 1B, a silicon oxide layer 113 is formed by chemical vapor deposition to fill the trench 112. Please refer to Figure 1C. Next, a photoresist is formed on the silicon oxide layer 113. The paper size is applicable to China Gujiao (CNS) A4 specification (210X297 mm) (Please read the note ^^ on the back before filling this page ) Order 'Printing 3674t \ vi * .doc / 008 A / _B7 __ of the Central Standards Bureau of the Ministry of Economic Affairs of the Shellfish Consumer Cooperatives. 5. Description of the Invention (7) Layer (not shown in the figure)' defines the pattern of the photoresist layer, It is used as a mask for the reverse definition, and then anisotropic etching step is performed to etch a part of the silicon oxide layer 113 to form a silicon oxide layer 113a as shown in the figure. Then, the photoresist layer is removed to expose the silicon oxide layer 113a, and the silicon oxide layer 113 corresponding to the active region has been partially stripped. Finally, a chemical-mechanical honing method (Chemical Mechanical Polish; CMP) is performed, with the silicon nitride layer 111 as a stop layer, and the oxide sand layer 113a is honed to a height of about 50 nm above the nitride sand layer ill. When the photoresist layer was used as a mask and the anisotropic etching step was performed, due to the lack of a good etching stop layer, the residual thickness of the silicon oxide layer over the silicon nitride layer 111 was uneven, resulting in uneven etching uniformity. The best conditions make it impossible to accurately control the thickness to be retained when performing chemical mechanical honing. Referring to FIG. 1D, the silicon nitride layer 111, the pad oxide layer 107, and a part of the silicon oxide layer 113a are removed by a wet etching method. It is desirable to make the surface of the substrate a flat surface to complete the structure of the trench isolation region 115. Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives ^ n 'aian ϋ— HI mmm ΙΛ ϋ— ϋ I HI 11 · Bϋ (please read Bg-back first (please fill in this page with V precautions) but due to the silicon nitride layer The residual thickness of the silicon oxide layer 113a above the Π1 is not uniform. Therefore, in the case of such poor etching uniformity, if the silicon nitride layer is removed by etching, the oxidization layer 107 and a part of the oxide are partially oxidized. For the silicon layer 113a, a flat surface substrate 105 cannot be obtained. Therefore, the main object of the present invention is to provide a method for manufacturing a trench isolation region. The silicon oxide layer can be anisotropically etched. Etching the stop layer to obtain a better etch uniformity 'in subsequent processes' before a flat surface substrate can be obtained to facilitate the process / process. In order to achieve the purpose of the invention, a manufacturing method for trench isolation i is proposed. 4 This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 3674t \ vf.doc / 008 A7 B7 Printed by the Central Consumers Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. V. Description of Invention (3) Method 'Provides a semiconductor Substrate A pad oxide layer, a silicon nitride layer, a "etch-back oxide layer", and a polycrystalline silicon layer are sequentially formed on the top, defining the polycrystalline silicon layer, the oxide layer, the nitrided sand layer, the pad oxide layer, and the semiconductor substrate to form a trench in the semiconductor substrate. Then 'form a layer, return the oxide layer, and fill the trench. After that,' use the polycrystalline silicon layer as the etching stop layer, strip the oxide layer of the active area, and expose the polycrystalline layer completely. "Reverted silicon oxide layer" has an etching selectivity much greater than one, and can be used as an etching termination layer, so that it can have better thickness uniformity after etching, so it can improve the problem of poor uniformity of the existing process. Next The "etch-back oxide layer" and the polycrystalline silicon layer with better thickness uniformity can be used as a buffer for chemical mechanical honing. Because the polycrystalline silicon layer has a honing selectivity of silicon oxide close to one, it does not cause a manufacturing process during honing. Therefore, the surface flatness of the active area can be made more uniform. When honing, the polycrystalline sand layer will be completely removed, and up to a certain height above the nitrided sand layer. The oxide layer, the silicon nitride layer, the pad oxide layer and a part of the oxide layer are sequentially removed by an etching method, so that the substrate is formed into a flat surface to complete the trench isolation region. In order to achieve the above and other objects and features of the present invention, , And advantages can be more obvious and easy to understand. The following is a detailed description of a preferred embodiment and the accompanying drawings' as follows: A brief description of the drawings: Figures 1A to 1D show a known trench Sectional schematic diagram of a method for manufacturing a therapeutic isolation zone; Figures 2A to 2F are schematic sectional diagrams of a method for manufacturing a trench isolation zone according to one of the comparative embodiments of the present invention; The scale is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 3674twf.doc / 0〇8 A7 B7 V. Description of the invention (κ) Figure 3 is a preferred embodiment of the present invention. A schematic cross-sectional view of a trench isolation area after a protective layer is formed on a polycrystalline sand layer. Symbols of the drawings: (Please read the notes on the back before filling this page) 105, 250: Base 107, 252: Pad oxide layer 1Π, 254: Silicon nitride layer 112, 260: Ditch 113, 113a, 256, 262, 262a, 262b, 262c: oxide layer 115, 265: trench isolation region 258: polycrystalline silicon layer 261: active region 270: specific height 300: protective layer embodiment FIGS. 2A to 2E are according to the present invention A preferred embodiment is a schematic sectional view of a method for manufacturing a trench isolation area. Please refer to Figure 2A. First, provide a semiconductor substrate 250, such as a silicon substrate, with a pad oxide layer 252 over it, such as a thickness of about 50A to 200A. Then, a silicon nitride layer 254 is formed on the pad oxide layer 2W. For example, the thickness is about 500A to 2500A by using a chemical vapor deposition method. An oxide layer 256 is further formed on the silicon nitride layer 2; for example, the thickness is about 500A to 2000A. After that, a polycrystalline silicon layer 258 is formed on the oxide layer 256, for example, using a chemical vapor deposition method, with a thickness of about 300A. This polycrystalline sand layer 258 must have sufficient thickness, because in the trench 6, dare to rub it from the middle-country country (CNS > Ya 4 threats (210X297 mm) 3674iwf.doc / 008 A, _ ^ __ B7______ V. Invention Note (t) After the isolation region is defined, there will be an oxidation step to form a liner oxide layer (not shown in the figure) at the contact interface between the trench isolation region and the substrate 250. If the polycrystalline silicon layer 258 is not thick enough, it may be At the same time as the liner oxide layer is formed, it is oxidized to oxidized sand, making it impossible to use the high etching ratio between polycrystalline sand and oxidized sand to carry out subsequent processes that use polycrystalline silicon P 258 as the end point of etching. Or it can form only a thin layer The polycrystalline silicon layer 258, for example, has a thickness of about 50A to 100A. As shown in FIG. 3, the other symbols in FIG. 3 have the same meaning as those in FIG. 2A. Then, a thin polycrystalline silicon layer 258 is formed on this layer—the thickness is about A 100A protective layer 300, such as a silicon oxide material, protects the thinner polycrystalline silicon layer 258, so that the polycrystalline silicon layer 258 will not be oxidized to silicon oxide in the subsequent formation of the liner oxide layer. Please refer to FIG. 2B ' Layer 25 A photoresist layer with a trench pattern (not shown in the figure) is formed over the top. Next, a touch-etching step is performed to sequentially etch the polycrystalline silicon layer, the oxide layer 256, the silicon nitride layer 254, the pad oxide layer 252, and the semiconductor substrate. 250, a trench 260 is formed in the semiconductor substrate 25 to define the element active area 201. Then, this photoresist layer is removed. Printed by the Shelling Consumer Cooperative of the Central Rubbing Bureau of the Ministry of Economic Affairs --------- cI- (Please read M-Notes on the back side before filling out this page) Please refer to Figure 2C, and then 'form an oxide layer 262 to fill the trench 26〇' with a material such as oxide sand ', and its formation method, for example, using chemical Vapor deposition method. Please refer to FIG. 2D to form a photoresist layer (not shown) to cover the oxide layer 262 corresponding to the trench 260. Then, use the photoresist layer as a mask. Layer 2 5 8 is the etching stop layer. The etching step is performed, for example, anisotropic etching is used to etch the oxide layer 262 which is not covered by the photoresist layer. 7 This paper is suitable for China National Standard (CNS) A4. ^ Χ297mm) '-3674tw l.doc / 008 A7 B7 V. & Invention Description If a protective layer 300 is formed on the polycrystalline sand layer 258 to prevent the polycrystalline silicon layer 258 from being oxidized (as shown in FIG. 3), this etching step will simultaneously remove the protective layer 300 on the polycrystalline sand layer 258. The silicon layer 258 makes the surface flatness of the active area more uniform, so as to expose more and make the oxide layer resistive layer, so that the trench 260 is converted to the oxide layer 262a by the Central Engineering Bureau of the Ministry of Economic Affairs. Then, the light oxide layer 262a is removed to protrude from the surface of the substrate 250. Please refer to FIG. 2E. Then, perform a chemical or mechanical honing method to remove a portion of the oxide layer 262a and the polycrystalline silicon layer 258, and then expose the oxide layer 256. Continue to stop the layer with the silicon nitride layer 254, and then hob the oxide layer. 256 until a specific height 270 above the nitrided sand layer 254, for example, 0A to 50oA above the silicon nitride layer. At this point, a complete surface is obtained. The conventional method is honing until the silicon nitride layer 254 is completely exposed, but the chemical mechanical honing method may cause micro scratches on the surface of the oxide layer 262b. 'If the honing is completely until the silicon nitride layer 254 is exposed, , The micro-scratch also penetrates into the inside of the oxide layer 262 b at the same time, resulting in that the micro-scratch still remains on the surface of the semiconductor substrate after the pad oxide layer is subsequently removed by the etch method. Therefore, according to the present invention, as long as the surface being honed is sufficiently flat, the honing can be stopped, so that an oxide layer 256a remains on the silicon nitride layer 254. Because the honing time is not too long, the surface of the oxide layer 262b is slightly scratched The depth will not be close to the surface of the semiconductor substrate 250, and it is avoided that it is not possible to obtain a flat surface to facilitate subsequent etching due to poor etching uniformity. After the subsequent etching process is completed, micro-scratch can be completely eliminated. Please refer to FIG. 2F, and then remove the oxide layer 256a, the silicon nitride layer 254 ', the pad oxide layer 252, and a part of the oxide layer 262b. The method is, for example, please read it first.
C 訂 本紙張尺度適用中國國家揉率（CNS ) A4规格（210χ297公釐） 36 74twfdoc/008 A7 B7 五、發明説明（〇) 濕式蝕刻法，使基底250形成爲一平整的表面，於是完成 溝渠隔離區265的結構。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。 (1) 本發明於塡入溝渠的氧化層下方形成一層多晶矽 層’由於氧化層與多晶矽層間的高蝕刻選擇率，使得後續 蝕刻用於塡入溝渠中的氧化層時，多晶矽層可以扮演一個 良好的蝕刻終止層’於蝕刻完之後，多晶矽層可以完全暴 露出’以於主動區得到〜蝕刻均勻度極佳的表面，有利於 化學機械硏磨法的進行。 (2) 本發明之氮化矽層上有一層厚度均勻的氧化層和 多晶矽層’且此多晶矽層與氧化層之間的硏磨選擇率接近 一，因此在進行化學機械硏磨法的步驟時，只要所硏磨的 表面已經夠平整，便可以停止硏磨，因此縮短硏磨的時間， 使氮化矽層上方保留一厚度的氧化層，因此，氧化層表面 微刮痕之深度不會靠近半導體基底之表面，後續以蝕刻製 程去除氮化矽層與墊氧化層之後，可以完全消除微刮痕， 得到一平整的基底表面。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注f項再填寫本頁) -訂 經濟部中央搮準局貝工消費合作社印«-C. The size of the paper is applicable to the Chinese national kneading rate (CNS) A4 specification (210 x 297 mm) 36 74twfdoc / 008 A7 B7 V. Description of the invention (〇) The wet etching method makes the substrate 250 a flat surface, and is completed. Structure of the trench isolation area 265. As can be seen from the above-mentioned preferred embodiments of the present invention, the application of the present invention has the following advantages. (1) The present invention forms a polycrystalline silicon layer under the oxide layer of the trench. Due to the high etching selectivity between the oxide layer and the polycrystalline silicon layer, the polycrystalline silicon layer can play a good role when the subsequent etching is used for the oxide layer of the trench. After the etching is completed, the polycrystalline silicon layer can be completely exposed, so that the surface of the active region has an excellent etching uniformity, which is beneficial to the chemical mechanical honing method. (2) The silicon nitride layer of the present invention has an oxide layer and a polycrystalline silicon layer having a uniform thickness, and the honing selectivity between the polycrystalline silicon layer and the oxide layer is close to one. Therefore, when performing the steps of the chemical mechanical honing method, As long as the honing surface is flat enough, the honing can be stopped, so the honing time is shortened, so that a thick oxide layer remains on the silicon nitride layer, so the depth of the micro-scratch on the surface of the oxide layer will not approach After the silicon nitride layer and the pad oxide layer are subsequently removed by an etching process on the surface of the semiconductor substrate, micro-scratch can be completely eliminated to obtain a flat substrate surface. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the note f on the back before filling out this page) -Ordered by the Central Laboratories Bureau of the Ministry of Economy