37l0t\vf.doc/008 A7 B7 五、發明説明（（） 本發明是有關於一種積體電路元件隔離結構的製造方 法，特別是有關於一種可避免碟陷（Dishing )現象之淺溝 渠隔離結構（Shallow Trench Isolation; STI )的製造方法。 兀件隔離區係用以防止載子（Carrier)通過基底而在 相鄰之元件間移動，比如於相鄰的金氧半（M〇s )電晶體 間形成元件隔離區，藉以減少由金氧半電晶體產生的電荷 遺漏（Charge Leakage)。隨著元件積集度的提高以及線 寬的縮小，當製程進入0.25微米以下時，淺溝渠隔離結構 已是必須之元件隔離結構。其形成方式是利用非等向性的 貪虫刻法（Anisotropic Etching)，在半導體基底中挖出溝 渠’然後在此溝渠中塡滿絕緣物質，因而形成了元件隔離 區° 在半導體製程進入深次微米（Deep Sub-micron)領域 後’化學機械硏磨製程（Chemical Mechanical Polishing; CMP)已成爲一習用之製程，但於製造淺溝渠隔離結構的 過程中，會造成碟陷的問題出現。 第1A圖至第1B圖係繪示習知一種淺溝渠隔離的製 造方法之剖面示意圖。 首先請參照第1A圖，於半導體基底10上形成墊氧化 (Pad Oxide )層12，並覆蓋一層氮化砂層14做爲触刻溝 渠15a和15b之硬罩幕（Hard Mask)，其中溝渠15a的 寬度較小，而溝渠15b的寬度較大。之後，利用化學氣相 沈積（CVD)法，沈積一層氧化層16覆蓋於氮化矽層14 上’並塡入溝渠15a和15b中。而由於溝渠l5a和所 3 本紙張尺度埴用中国躅家揉準（CNS ) Α4規格（21〇χ297公釐） --------虚II (請先閲讀#-面之注*·Ϋ項再填寫本頁) 訂 經濟部中央揉率局貝工消费合作社印«. 3710twf.doc/008 A7 B7 五、發明説明（>) 造成基底1〇上的形貌（Topographic)變化，因此使所形 成的氧化層16爲不平坦的表面。 接著請參照第1B圖，經緻密化（Densification)製程 後，進行化學機械硏磨步驟，用以去除氮化砂層14上多 餘的氧化層16，使氧化層16轉爲氧化層16a。 然而，當CMP進行時’晶片的正面壓在舖有一層硏 磨墊（Polishing Pad)的硏磨台上，由於氧化層16的不平 坦，使硏磨墊在寬度較大的_渠處15b易產生變形 (Deformation)而接觸到溝渠15b處的氧化層16，使得 經平坦化過程後，產生下列問題：（1)較寬的溝渠15b處 的氧化層16a會產生碟陷18，而造成氧化層l6a在較寬的 溝渠15b內變薄；（2)氮化矽層14的較大平台處14b，有 氧化層16a的殘留；（3)因氮化矽層14平台的大小不同， 若欲單單以CMP製程來去除氮化層14上方的氧化層16， 並使經CMP後的氧化層16a具有極佳的均勻性 (Uniformity)是很困難的。 在剝除氮化矽層14之前，爲了將其上的氧化層16完 全去除，通常以過度硏磨（Over-polishing )的方法來進行， 如此可解決氧化層16a殘留於氮化矽層14的問題，但是 卻會使氧化層16a碟陷和氮化矽層14侵蝕的問題更加嚴 重。 爲了解決碟陷的問題，習知提出一種利用虛擬圖案 (Dummy Pattern)的結構，來避免碟陷的現象。如第2 圖所示，圖中標號的意義與第1圖相同，其方法係於較寬 本紙張尺度逍用中國國家標率（CNS ) A4規格（210X297公釐） 請 先 閲 讀 背- 項 訂 經濟部中央橾準局"C工消费合作社印裝 37l0twf.doc/008 A7 B7 五、發明説明（>) 的溝渠（如第1B圖中的16a)中間，佈局一虛擬圖案20， 使原本爲一個較寬的溝渠（如第1B圖中的16a)轉爲兩 個較窄的溝渠16c，因此所有溝渠15a和15c的寬度並沒 有太大的差異，於是可以避免碟陷的問題發生，但由於氮 化石夕層14的平台大小仍有極大的差異，因此氮化砂層14 上方之氧化層16a殘留的問題仍無法獲得解決。 因此本發明的第一目的，就是在提供一種淺溝渠隔離 結構的製程方法，可以避免碟陷的現象發生。 本發明的第二目的，就是在提供一種淺溝渠隔離結構 的製程方法，可以避免氧化物殘留的問題。 經濟部中央標率局貝工消费合作社印製 (請先聞讀t-面之注t·事項再填寫本頁) 爲達成本發明之目的，提出一種淺溝渠隔離結構的製 造方法，於基底上依序形成墊氧化層、罩幕層與多晶矽層， 並形成溝渠穿透多晶矽層、罩幕層和墊氧化層直達基底 內，藉以定出元件主動區。接著形成一層絕緣層將溝渠塡 滿，再進行化學機械硏磨製程，當進行至多晶矽層暴露出 後，由於多晶矽層的硏磨速率大於絕緣層的硏磨速率，可 避免前述因硏磨墊在寬度較大的溝渠處變形而產生碟陷的 現象發生，當化學機械硏磨製程進行至氮化矽層暴露後即 停止。最後再進行習知的剝除製程，剝除罩幕層和墊氧化 層，用以於基底中形成一具有平整表面的淺溝渠隔離的結 構。 此外，本發明尙可配合反相罩幕，於基底上依序形成 墊氧化層、罩幕層與多晶矽層，並形成溝渠穿透多晶矽層、 罩幕層和墊氧化層直達基底內，藉以定出元件主動區。接 5 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " 經濟部中夬標準局貝工消费合作社印製 37IOtwf.doc/008 A 7 __ B7 五、發明説明（L) 著形成一層絕緣層將溝渠塡滿，利用反相罩幕，將主動區 的絕緣層部份剝除後’本發明之多晶矽層正好可做爲此時 之蝕刻停止層，有助於提昇蝕刻之均勻度；之後再進行化 學機械硏磨製程’這時因部份絕緣層已被剝除，所以可減 少進行化學機械硏磨的時間，且因多晶矽層的硏磨速率大 於絕緣層的硏磨速率，更能避免前述因硏磨塾在寬度較大 的溝渠處變形而產生碟陷的現象發生，當化學機械硏磨製 程進行至氮化矽層暴露後即停止'。最後再進行習知的剝除 製程，剝除罩幕層和墊氧化層，用以於基底中形成一具有 平整表面的淺溝渠隔離的結構。因此，本發明於罩幕層上 方形成一層多晶砂層，即可有效解決習知的問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉二較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1B圖係繪示習知一種淺溝渠隔離結構 的製造方法之剖面示意圖； 第2圖係繪示習知一種配合虛擬圖案的淺溝渠隔離結 構之剖面示意圖； 第3A圖至第3C圖係繪示根據本發明一較佳實施例 之一種淺溝渠隔離結構的製造方法剖面示意圖；以及 第4A圖至第4D圖係繪示根據本發明另一較佳實施 例之一種淺溝渠隔離結構的製造方法剖面示意圖，此實施 例係配合反相蝕刻罩幕的使用。 6 本纸張尺度適用中國國家揉率（CNS ) A4规格（210X297公釐） (請先閲讀背面之注$項再填寫本頁) 訂 經濟部中央標準局贵工消費合作社印製 37 I0tvvf.doc/008 A7 B7 五、發明説明（C) 圖式之標記說明： 10、100 基底 12 ' 102 ' 102a 墊氧化層 14 ' 104 ' 104a 氮化矽層 14a、14b 氮化砂層的平台 16、16a 氧化砂層 15a ' 15b ' 15c ' 105a ' 105b 溝渠 108、108a、108b 絕緣層 109 厚度 第一實施例 第3A圖至第3C圖係根據本發明之一較佳實施例之 一種淺溝渠隔離結構的製造流程之剖面示意圖。 首先請參照第3A圖，於基底100表面形成一層墊氧 化層102，其方法比如是熱氧化法。之後於墊氧化層上形 成罩幕層104，其材質比如是氮化矽，其厚度比如約爲 500A〜2000A。再於罩幕層104上形成一層多晶矽層106， 此爲本發明的特徵之一，所形成之多晶矽層106的厚度約 500〜2000A ° 接著請參照第3B圖，於多晶矽層106上覆蓋一已圖 案化的光阻層（未繪示於圖中），用以於基底1〇〇中形成 溝渠105a和105b，藉以將基底100定義出主動區（Active Region)，其方法比如是利用乾式蝕刻之非等向性的蝕刻 方法，使墊氧化層102、罩幕層104和多晶矽層106轉爲 墊氧化層102a、罩幕層104和多晶砂層106a。其中溝渠105a 7 本纸張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） —I----------- (請先閲讀背面之注意事項再填寫本頁)37l0t \ vf.doc / 008 A7 B7 V. Description of the invention (() The present invention relates to a method for manufacturing an integrated circuit element isolation structure, and in particular, to a shallow trench isolation structure capable of avoiding dishing (Dishing) phenomenon (Shallow Trench Isolation; STI) manufacturing method. The element isolation area is used to prevent carriers (Carrier) from moving between adjacent components through the substrate, such as adjacent metal oxide semiconductor (MOS) transistor Element isolation areas are formed between them to reduce the charge leakage generated by the metal-oxide semiconductors. With the increase of the element accumulation and the reduction of the line width, the shallow trench isolation structure has been reduced when the process enters below 0.25 microns. It is a necessary element isolation structure. Its formation method is to use the anisotropic etch method to dig a trench in a semiconductor substrate and then fill the trench with insulating material, thereby forming an element isolation region ° After the semiconductor process enters the deep sub-micron field, 'Chemical Mechanical Polishing (CMP) has become a customary system However, in the process of manufacturing a shallow trench isolation structure, the problem of dishing will occur. Figures 1A to 1B are schematic cross-sectional views showing a conventional manufacturing method for shallow trench isolation. Please refer to Figure 1A first. A pad oxide layer 12 is formed on the semiconductor substrate 10 and covered with a layer of nitrided sand layer 14 as a hard mask for touching the trenches 15a and 15b. The width of the trench 15a is small and the trench is 15 The width of 15b is large. Then, a chemical vapor deposition (CVD) method is used to deposit an oxide layer 16 over the silicon nitride layer 14 'and penetrate into the trenches 15a and 15b. The trenches 15a and 3 sheets The scale is in Chinese standard (CNS) Α4 size (21 × 297 mm) -------- Virtual II (please read #-面 之 Note * · Item before filling out this page) Order economy Printed by the Central Government Bureau of the Bayer Consumer Cooperative «. 3710twf.doc / 008 A7 B7 V. Explanation of the invention (>) caused the topographic change on the substrate 10, so that the oxide layer 16 formed was not Flat surface. Please refer to Figure 1B, after the densification process, A chemical mechanical honing step is performed to remove the excess oxide layer 16 on the nitrided sand layer 14 and turn the oxide layer 16 into an oxide layer 16a. However, when the CMP is performed, the front side of the wafer is pressed with a honing pad ( On the honing table of Polishing Pad, due to the unevenness of the oxide layer 16, the honing pad is prone to deform at the _ channel 15b with a larger width and contacts the oxide layer 16 at the channel 15b, so that the surface is flat. After the siliconization process, the following problems occur: (1) the oxide layer 16a at the wider trench 15b will generate dish 18, which causes the oxide layer 16a to become thinner within the wider trench 15b; (2) the silicon nitride layer 14 At the larger platform 14b, there is a residual oxide layer 16a; (3) Because the size of the silicon nitride layer 14 platform is different, if the CMP process is used to remove the oxide layer 16 above the nitride layer 14, and after CMP, It is difficult for the oxide layer 16a to have excellent uniformity. Before the silicon nitride layer 14 is stripped, in order to completely remove the oxide layer 16 thereon, it is usually performed by an over-polishing method, so that the residual oxide layer 16a on the silicon nitride layer 14 can be solved. The problem is, however, the problem of sinking the oxide layer 16a and the silicon nitride layer 14 is more serious. In order to solve the problem of dishing, the conventional method proposes a structure using a dummy pattern to avoid the dishing phenomenon. As shown in Figure 2, the meaning of the labels in the figure is the same as that in Figure 1. The method is to use the Chinese paper standard (CNS) A4 specification (210X297 mm) in a wider paper size. Please read the back-item order Central Standards Bureau of the Ministry of Economic Affairs " C Industrial Consumer Cooperatives printed 37l0twf.doc / 008 A7 B7 5. In the middle of the trench of the invention description (such as 16a in Figure 1B), a virtual pattern 20 is laid out so that the original A wide trench (such as 16a in Figure 1B) is converted into two narrow trenches 16c, so the widths of all trenches 15a and 15c are not much different, so the problem of dishing can be avoided, but Since the platform size of the nitrided stone layer 14 is still extremely different, the problem of the residual oxide layer 16a above the nitrided sand layer 14 still cannot be solved. Therefore, a first object of the present invention is to provide a manufacturing method for a shallow trench isolation structure, which can avoid dishing. A second object of the present invention is to provide a method for manufacturing a shallow trench isolation structure, which can avoid the problem of oxide residue. Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the t-face note t · items before filling out this page) In order to achieve the purpose of the invention, a method for manufacturing a shallow trench isolation structure is proposed on the substrate A pad oxide layer, a mask layer, and a polycrystalline silicon layer are sequentially formed, and a trench is formed to penetrate the polycrystalline silicon layer, the mask layer, and the pad oxide layer directly into the substrate, thereby determining the active area of the device. Then an insulating layer is formed to fill the trench, and then the chemical mechanical honing process is performed. When the polycrystalline silicon layer is exposed, the honing rate of the polycrystalline silicon layer is greater than the honing rate of the insulating layer, which can avoid the aforementioned problem of honing pads. The phenomenon of dishing caused by the deformation of the trench with a larger width occurs. The chemical mechanical honing process stops after the silicon nitride layer is exposed. Finally, a conventional stripping process is performed to strip the mask layer and the pad oxide layer to form a shallow trench isolation structure with a flat surface in the substrate. In addition, the present invention can cooperate with an inversion mask to sequentially form a pad oxide layer, a mask layer, and a polycrystalline silicon layer on the substrate, and form a trench penetrating the polycrystalline silicon layer, the mask layer, and the pad oxide layer to reach the substrate directly. Out of the component active area. Then 5 paper sizes are applicable to Chinese National Standards (CNS) A4 specifications (210X297 mm) " Printed by Shelley Consumer Cooperative, China Standards Bureau, Ministry of Economic Affairs 37IOtwf.doc / 008 A 7 __ B7 V. Description of the invention (L) By forming an insulating layer to fill the trench, the inverse mask is used to strip the insulating layer in the active area. The polycrystalline silicon layer of the present invention can be used as an etching stop layer at this time, which can help improve the etching. Uniformity; then the chemical mechanical honing process is performed at this time because part of the insulation layer has been stripped, so the time for chemical mechanical honing can be reduced, and because the honing rate of the polycrystalline silicon layer is greater than the honing rate of the insulating layer, It can also avoid the phenomenon of dishing caused by the honing and deformation at the trench with a larger width, and stop when the chemical mechanical honing process is performed until the silicon nitride layer is exposed '. Finally, a conventional stripping process is performed to strip the mask layer and the pad oxide layer to form a shallow trench isolation structure with a flat surface in the substrate. Therefore, the present invention can effectively solve the conventional problems by forming a polycrystalline sand layer above the mask layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the two preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A FIG. 1 to FIG. 1B are schematic cross-sectional views of a conventional method for manufacturing a shallow trench isolation structure; FIG. 2 is a schematic cross-sectional views of a conventional shallow trench isolation structure with a virtual pattern; FIGS. 3A to 3C FIG. 4A is a schematic cross-sectional view showing a method for manufacturing a shallow trench isolation structure according to a preferred embodiment of the present invention; and FIGS. 4A to 4D are views illustrating manufacturing of a shallow trench isolation structure according to another preferred embodiment of the present invention; A schematic cross-sectional view of the method. This embodiment is used in conjunction with the inversion etching mask. 6 This paper size applies to China's national kneading rate (CNS) A4 size (210X297 mm) (please read the note on the back before filling this page) Order printed by Guigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 37 I0tvvf.doc / 008 A7 B7 V. Description of the invention (C) Marking of the drawings: 10, 100 substrate 12 '102' 102a pad oxide layer 14 '104' 104a silicon nitride layer 14a, 14b oxidation of the silicon nitride layer 16 and 16a Sand layer 15a '15b' 15c '105a' 105b trench 108, 108a, 108b insulation layer 109 thickness First embodiment Figures 3A to 3C are a manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention Schematic cross-section. First, referring to FIG. 3A, a pad oxidation layer 102 is formed on the surface of the substrate 100, such as a thermal oxidation method. Then, a mask layer 104 is formed on the pad oxide layer, and the material is, for example, silicon nitride, and the thickness is, for example, about 500A to 2000A. Then, a polycrystalline silicon layer 106 is formed on the mask layer 104, which is one of the features of the present invention. The thickness of the formed polycrystalline silicon layer 106 is about 500 ~ 2000A. Then, referring to FIG. 3B, a layer of polycrystalline silicon layer 106 is covered. A patterned photoresist layer (not shown in the figure) is used to form trenches 105a and 105b in the substrate 100, thereby defining the substrate 100 as an active region. The method is, for example, using dry etching The anisotropic etching method converts the pad oxide layer 102, the mask layer 104 and the polycrystalline silicon layer 106 into the pad oxide layer 102a, the mask layer 104 and the polycrystalline sand layer 106a. Among them, the ditch 105a 7 paper size is applicable to Chinese National Standard (CNS) Α4 specification (210X297 mm) —I ----------- (Please read the precautions on the back before filling this page)
、1T 37*〇twf.doc/008 A7 B7 五、發明説明（4) (請先聞讀梵面之注愈事項再埃寫本頁) 表示溝渠的寬度較小，溝渠105b表示溝渠的寬度較大。 之後形成一層絕緣層108覆蓋於多晶矽層106a上，並塡 入溝渠105a和105b中，其中絕緣層108的材質比如是氧 化矽。在形成絕緣層108之前更包括於溝渠105a和l〇5b 之基底100表面形成一層襯氧化層（未繪示於圖中），其 方法比如是熱氧化法。 接著請參照第3C圖，絕緣層108經緻密化步驟後， 進行CMP製程，用以剝除罩幕層l〇4a上方的絕緣層108 和多晶矽層l〇6a。由於多晶矽層106a的硏磨速率約比絕 緣層108快3〜4倍，所以當多晶矽層i〇6a暴露出後，多 晶矽層106a的剝除速率會比溝渠i〇5a和105b部份的絕 緣層108快。CMP製程完成後，使絕緣層ι〇8轉爲略具突 起的絕緣層108b，因此可以避免碟陷的現象發生。另外， 可以藉由調整多晶砂層106a的厚度，來控制CMP後所形 成之絕緣層108b的突起高度。此爲本發明的特徵之一。 之後進行後續的半導體製程，此非關本發明，在此不 多贅言。 第二實施例 經濟部中央橾率局貝工消費合作社印氧 第4A圖至第4D圖係根據本發明之另一較佳實施例 之一種淺溝渠隔離結構的製造流程之剖面示意圖，此實施 例係配合使用反相蝕刻罩幕。圖中標號的意義與第一實施 例之圖式相同。 首先請參照第4A圖，於基底100表面形成一層墊氧 化層102，其方法比如是熱氧化法。之後於墊氧化層上形 8 本纸張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） 3 7 I 01 \v f. d 〇 c / 0 0 8 A7 B7 五、發明説明（9) 成罩幕層104，其材質比如是氮化矽，其厚度比如約爲 500A〜2000A。再於罩幕層1〇4上形成一層多晶矽層1〇6， 此爲本發明的特徵之一，所形成之多晶矽層106的厚度約 500〜2000A ° 接著請參照第4B圖，於多晶矽層106上覆蓋一已圖 案化的光阻層（未繪示於圖中），用以於基底100中形成 溝渠l〇5a和l〇5b，藉以將基底1〇〇定義出主動區，其方 法比如是利用乾式蝕刻之非等向性的蝕刻方法，使墊氧化 層102、罩幕層1〇4和多晶矽層106轉爲墊氧化層l〇2a、 罩幕層104和多晶矽層106a。其中溝渠l〇5a表示溝渠的 寬度較小，溝渠105b表示溝渠的寬度較大。之後形成一 層絕緣層108覆蓋於多晶矽層106a上，並塡入溝渠l〇5a 和105b中，其中絕緣層108的材質比如是氧化矽。在形 成絕緣層108之前更包括於溝渠l〇5a和l〇5b之基底100 表面形成一層襯氧化層（未繪示於圖中），其方法比如是 熱氧化法。 接著請參照第4C圖，絕緣層1〇8經緻密化步驟後， 爲了避免主動區的絕緣層108需較長的硏磨時間而影響到 整體絕緣層108的硏磨均勻性，於是進行反相蝕刻（Reverse Pattering)，將主動區的絕緣層108利用触刻法先行部份 剝除，其方法係於絕緣層1〇8上覆蓋一層已圖案化的光阻 層（未繪示於圖中），其中光阻層覆蓋的區域對應於溝渠 105a和105b的上方，此光阻層即爲一反相罩幕 (Reverse-Tone Mask)。之後以此光阻層爲罩幕，剝除多 9 本紙張尺度適用中國鬮家標準（CNS ) A4規格（21〇Χ297公釐） (請先閲讀t面之注項再填寫本頁) 經濟部中夾揉率扃貞工消费合作社印簟、 1T 37 * 〇twf.doc / 008 A7 B7 V. Description of the invention (4) (Please read the notes on the Vatican side before writing this page) It indicates that the width of the trench is smaller, and the trench 105b indicates that the width of the trench is smaller than Big. Then, an insulating layer 108 is formed to cover the polycrystalline silicon layer 106a, and is inserted into the trenches 105a and 105b. The material of the insulating layer 108 is, for example, silicon oxide. Before forming the insulating layer 108, a layer of an oxide liner (not shown in the figure) is formed on the surface of the substrate 100 of the trenches 105a and 105b. The method is, for example, a thermal oxidation method. Referring to FIG. 3C, after the densification step of the insulating layer 108, a CMP process is performed to strip the insulating layer 108 and the polycrystalline silicon layer 106a above the mask layer 104a. Since the honing rate of the polycrystalline silicon layer 106a is about 3 to 4 times faster than that of the insulating layer 108, after the polycrystalline silicon layer 106 is exposed, the peeling rate of the polycrystalline silicon layer 106a will be faster than that of the insulating layers in the trenches 105a and 105b. 108 fast. After the CMP process is completed, the insulating layer ι8 is turned into a slightly protruding insulating layer 108b, so that the dishing phenomenon can be avoided. In addition, the height of the protrusion of the insulating layer 108b formed after CMP can be controlled by adjusting the thickness of the polycrystalline sand layer 106a. This is one of the features of the present invention. Subsequent semiconductor processes are performed thereafter, which is not related to the present invention, and it is not necessary to repeat them here. Second Embodiment Figures 4A to 4D of the printing of oxygen by the Shellfish Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs are schematic cross-sectional views of a manufacturing process for a shallow trench isolation structure according to another preferred embodiment of the present invention. It is used in conjunction with the reverse etching mask. The meaning of the reference numerals in the figure is the same as that of the first embodiment. First, referring to FIG. 4A, a pad oxidation layer 102 is formed on the surface of the substrate 100, such as a thermal oxidation method. Then form on the oxide layer of the pad 8 This paper size is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 3 7 I 01 \ v f. D oc / 0 0 8 A7 B7 V. Description of the invention (9 ) To form the mask layer 104, the material of which is, for example, silicon nitride, and the thickness thereof is, for example, about 500A to 2000A. Then, a polycrystalline silicon layer 10 is formed on the mask layer 104, which is one of the features of the present invention. The thickness of the formed polycrystalline silicon layer 106 is about 500 ~ 2000A. Then, please refer to FIG. 4B, on the polycrystalline silicon layer 106. A patterned photoresist layer (not shown in the figure) is covered thereon to form trenches 105a and 105b in the substrate 100, thereby defining the substrate 100 as an active area. The method is, for example, The non-isotropic etching method of dry etching is used to convert the pad oxide layer 102, the mask layer 104, and the polycrystalline silicon layer 106 into the pad oxide layer 102a, the mask layer 104, and the polycrystalline silicon layer 106a. The trench 105a indicates that the width of the trench is smaller, and the trench 105b indicates that the width of the trench is larger. Then, an insulating layer 108 is formed to cover the polycrystalline silicon layer 106a, and is inserted into the trenches 105a and 105b. The material of the insulating layer 108 is, for example, silicon oxide. Before forming the insulating layer 108, a substrate oxide layer (not shown) is formed on the surface of the substrate 100 of the trenches 105a and 105b. The method is, for example, a thermal oxidation method. Next, please refer to FIG. 4C. After the insulating layer 108 is densified, in order to avoid the longer honing time of the insulating layer 108 in the active region, which affects the honing uniformity of the entire insulating layer 108, reverse phase is performed. Etching (Reverse Pattering), the insulation layer 108 in the active area is partially stripped by the touch-etching method. The method is to cover the insulation layer 108 with a patterned photoresist layer (not shown in the figure). The area covered by the photoresist layer corresponds to the trenches 105a and 105b, and this photoresist layer is a reverse-tone mask. Then use this photoresist layer as a mask to strip off more than 9 paper sizes. Applicable to China Standard (CNS) A4 specification (21〇 × 297 mm) (please read the note on t side first and then fill out this page) Ministry of Economy Central pinch rate 夹 工 工 扃 工 扃 社 消费 簟
經濟部中央棵準局負工消费合作社印装 3 7 I Otwf.doc/008 A7 __B7____ 五、發明説明（Ϊ ) 晶矽層106a上方部份的絕緣層丨〇8，至絕緣層i〇8於多晶 矽層106a上方殘留一厚度1〇9，使絕緣層ι〇8轉爲絕緣層 108a，此厚度109約爲1000A〜2000A，剝除部份絕緣層108 的方法比如是乾式蝕刻法或是濕式蝕刻法。另外，由於多 晶矽層106a對材質比如爲氧化矽的絕緣層1〇8之蝕刻選 擇比大於1，因此可配合以多晶矽層106a做爲反相蝕刻的 蝕刻終止層（Etching Stop Layer)，同時可提昇反相蝕刻 的蝕刻均勻性（爲簡化圖示，此部份未繪示於圖式中）。 之後移除光阻層。 接著請參照第4D圖，進行CMP製程，用以剝除罩幕 層104a上方的絕緣層108a和多晶矽層l〇6a。由於多晶矽 層106a的硏磨速率約比絕緣層l〇8a快3〜4倍，所以當多 晶矽層106a暴露出後，多晶矽層l〇6a的剝除速率會比溝 渠l〇5a和l〇5b部份的絕緣層l〇8a快，CMP製程完成後， 使絕緣層l〇8a轉爲略具突起的絕緣層108b，因此可以避 免碟陷的現象發生。另外，可以藉由調整多晶矽層l〇6a 的厚度，來控制CMP後所形成之絕緣層lOSb的突起高度。 此爲本發明的特徵之一。 由於本發明係利用多晶矽層106配合反相罩幕的使用 來避免碟化的問題，還可以避免絕緣層1〇8殘留於覃幕層 l〇4a的上方。利用反相罩幕的優點，在於可以縮短CMP 進行的時間，因此可增加產能與淺溝渠隔離製程的裕度 (Window)，所謂的裕度就是在製程控制中，製作產品 可以容許的上下極限的範圍。另外’縮短了過度硏磨的時 (請先Η讀背面之注意事項再填寫本頁) 訂Printed by the Ministry of Economic Affairs of the Central Bureau of Work, Consumer Cooperatives 3 7 I Otwf.doc / 008 A7 __B7____ V. Description of the Invention (Ϊ) The insulating layer above the crystalline silicon layer 106a 丨 〇8, to the insulating layer i〇8 在Above the polycrystalline silicon layer 106a, a thickness of 109 remains, so that the insulating layer ι0 is converted to an insulating layer 108a. The thickness 109 is about 1000A to 2000A. The method of stripping part of the insulating layer 108 is, for example, dry etching or wet Etching. In addition, since the polysilicon layer 106a has an etching selectivity ratio of a material such as a silicon oxide insulating layer 108, the polysilicon layer 106a can be used in conjunction with the polysilicon layer 106a as an etching stop layer (Etching Stop Layer) for reverse etching, and can also improve Etching uniformity of reverse etching (for simplicity, this part is not shown in the figure). After that, the photoresist layer is removed. Next, referring to FIG. 4D, a CMP process is performed to strip the insulating layer 108a and the polycrystalline silicon layer 106a above the mask layer 104a. Since the honing rate of the polycrystalline silicon layer 106a is about 3 to 4 times faster than that of the insulating layer 108a, when the polycrystalline silicon layer 106a is exposed, the peeling rate of the polycrystalline silicon layer 106a will be higher than that of the trenches 105a and 105b. The portion of the insulating layer 108a is fast. After the CMP process is completed, the insulating layer 108a is turned into a slightly protruding insulating layer 108b, so the phenomenon of dishing can be avoided. In addition, by adjusting the thickness of the polycrystalline silicon layer 106a, the protrusion height of the insulating layer lOSb formed after the CMP can be controlled. This is one of the features of the present invention. Since the present invention uses the polycrystalline silicon layer 106 in combination with the inversion mask to avoid the problem of dishing, it can also avoid that the insulating layer 108 remains on the top of the screen layer 104a. The advantage of using the inverse mask is that it can shorten the time of CMP, so it can increase the window of the production process and the shallow trench isolation process. The so-called margin is the upper and lower limits that the product can tolerate in the process control. range. In addition, the time of excessive honing is shortened (please read the precautions on the back before filling this page)
37 l0tvv!'.doc/008 A7 B7 五、發明説明（q) 間，對罩幕層l〇4a的硏磨程度會減少，因爲CMP製程所 產生之碟陷的現象也會減少。 之後進行後續的半導體製程，此非關本發明，在此不 多贅言。 綜上所述，本發明的特徵如下： (1) 於罩幕層上所形成的多晶矽層，由於多晶矽材質 對塡入溝渠中的絕緣材質有大於’1的蝕刻選擇比，因此可 以於反相蝕刻的製程中，做爲蝕刻終止層，同時提高反相 蝕刻的均勻度。 (2) 由於罩幕層上的多晶矽層之硏磨速率大於溝渠中 的絕緣材質，因此硏磨後可以使溝渠內的絕緣材質略爲突 起，於是可以避免碟陷的現象發生。 雖然本發明已以二較佳實施例揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍內，當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局員工消费合作社印製 本紙張尺度逍用中國國家標準（CNS ) A4規格（210X297公嫠）37 l0tvv! '. Doc / 008 A7 B7 5. In the description of the invention (q), the degree of honing of the cover layer 104a will be reduced, because the dishing phenomenon caused by the CMP process will also be reduced. Subsequent semiconductor processes are performed thereafter, which is not related to the present invention, and it is not necessary to repeat them here. To sum up, the features of the present invention are as follows: (1) The polycrystalline silicon layer formed on the mask layer has an etching selection ratio greater than '1 because the polycrystalline silicon material has an insulation selection ratio in the trench, which can be reversed. In the etching process, it is used as an etching stop layer, and at the same time, the uniformity of the reverse etching is improved. (2) Since the honing rate of the polycrystalline silicon layer on the cover layer is higher than that of the insulating material in the trench, the insulating material in the trench can be slightly raised after honing, so that the dishing phenomenon can be avoided. Although the present invention has been disclosed above with two preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper uses the Chinese National Standard (CNS) A4 specification (210X297)