415014 A7 B7 五、發明說明（/ ) 技術領域： 本發明係關於一種積體電路的製程方法，特別是關於一 種積體電路製程中製作平坦之淺溝渠隔離（Shallow Trench Isolation; STI)的方法。 讀背面之注$項再填寫本頁j 發明背景： 淺溝渠隔離（STI)的製程方法已被廣泛的應用於提供 主動元件區間之隔離，特別是應用於超大積體電路（ULSI) 元件之中。在淺溝渠隔離形成之後，經常利用化學機械研磨 法（Chemical Mechanical Polish; CMP)來進行良好的平坦 化處理，然而，由於銲墊結構的變形，寬溝渠的開口處容易 被研磨形成凹陷，導致寬溝渠中氧化層變薄的現象。 請參閱圖一，圖一係爲利用習知技藝所完成的部分積 體電路元件結構的剖面示意圖，其中所述結構係爲一已形成 有一氮化矽層14的半導體基板U)，所述基板10已定義出 數個溝渠，並充填有一氧化層17於所述溝渠中。上述結構 在經過CMP研磨之後形成如圖二所示之結構，於箭頭所指 之寬溝渠區域19可發現氧化層17的凹陷現象，並造成所述 寬溝渠區域19中之氧化層17結構缺乏一致性。 經濟部智慧財產局員工消費合作社印製 在積體電路的領域中，已經有很多的研究人員嘗試去 避免上述的問題產生，如：美國專利第4962064號中揭露一 種覆蓋在溝渠氧化物充填材料上的複晶矽層的使用，其中所 述氧化物材料在進行後續的CMP研磨及乾式或濕式蝕刻的 平坦化處理時，包含了至少兩次的蝕刻步驟；美國專利第 M94857號中揭露一種淺溝渠的CMP處理，利用反相方式 I紙張尺度適用中國國家標準（CNS)A4規格（210 X 2¾公釐） 415014 A7 _ B7 五、發明說明（>) 光罩（reverse-tone mask)於寬溝渠中形成塊狀氧化物及一 氮化矽結構之研磨終止層；美國專利第5641704號中揭露一 種利用一平坦的保角式第一氧化層（conformal oxide)及後 續形成的保角式第二氧化層來充填溝渠的製程方法，其中所 述充填林料係透過一光罩圖案，以化學蝕刻法蝕刻主動元件 區域來進行平坦化處理，隨後進行CMP處理，並以一氮化 矽層爲終點；美國專利第54928分號中揭露一種在溝渠充填 氧化層之前’先形成一氮化矽薄層於溝渠中的製程方法，後 續並對所述氧化層進行回火、電阻層回蝕刻及CMP步驟； 美國專利第5663107號中揭露一種利用一已摻雜玻璃(doped glass)作爲充填材料’並於其上形成一氮化矽層的製程方法， 後續之平坦化處理係包含CMP、非均向回蝕刻、乾式蝕刻 移除氮化層及第二次的CMP步驟。 發明之概述： 本發明之主要目的爲提供一種在積體電路中形成平坦的 淺溝渠隔離的方法。 本發明之另一目的爲提供一種形成平坦的淺溝渠隔離， 並可消弭氧化層凹陷現象的方法 本發明之又一目的爲提供一種形成平坦的淺溝渠隔離， 並可容易控制剩餘氧化層厚度的方法β 本發明之再一目的爲提供—種利用化學機械研磨法及伴 隨的乾式蝕刻法，形成平坦的淺溝渠隔離的方法。 爲了達到_t述之各項目的’本發明提供一種在積體電路 中形成平勵淺溝渠醜的方法。首先，提供一已形成有— ，讀背面之注意事項再填寫本頁) .J. n n 1_ n 訂-------- 經濟部智慧財產局員工消费合作杜印製 本紙張尺度通用中國囤豕標準（CNS)A4規格（210 X 2§7 ) 415014 A7 B7 五、發明說明（)） 第一氮化層的半導體基板，並於所述基板上定義數個隔離溝 渠，其中所述溝渠係包括至少一個寬溝渠及至少一個窄溝 渠；接著，形成一第一氧化層於所述基板上，並填滿所述隔 離溝渠；然後，依序形成一第二氮化層頂蓋（capping nitride layer) &—第二氧化層，並研磨所述第二氧化層，其中所述 第二氧化層及第二氮化層頂蓋只留下位於所述寬溝渠區域上 之部分；再接著，利用乾式触刻法蝕刻所述第一氧化層及第 二氧化層，並過度蝕刻所述第一氧化層，令蝕刻終止於完全 移除第二氮化矽層中的第二氧化層並露出第一氮時；最 後，移除所述第二氮化層及第一氮化層，完成所述積體電路 元件之淺溝渠隔離區域的製作。 圖式簡要說明： 圖一爲習知技藝製作之部分積體電路元件結構之剖面示 意圖。 圖二爲習知技藝製作之部分積體電路元件結構在經 CMP研磨後之剖面示意圖。 圖三爲本發明實施例中於半導體基板上形成一墊氧化層 及第一氮化層之剖面示意圖。 圖四爲本發明實施例中於基板中定義數個淺溝渠之剖面 示意圖。 圖五爲本發明實施例中形成一第一氧化層之剖面示意 圖。 圓六爲本發明實施例中於第一氧化層上形成第二氮化矽 層之剖面示意圖。 本紙張尺度適用中國固家標準（CNS)A4規格(210 X 2^7公釐） (_請先間tt·背面之注意事項再填窝本頁) 裝--------訂---------. 經濟部智慧財產局員工消費合作杜印製 415014 A7 _________ B7 經濟邨智慧財產局員工消費合作社印製 五、發明說明（f) 圓七爲本發明實施例中於第二氮化矽層上形成第二氧化 層之剖面示意圖》 圓八爲本發明實施例中第二氧化層及第二氮化矽層經 CMP研磨後之剖面示意圖。 圖九爲本發明實施例中蝕刻移除剩餘第二氧化層及露出 第一氮化矽層之剖面示意圖。 圖十爲本發明實施例中形成淺溝渠隔離之剖面示意圖。 圖十一爲本發明實施例中一完整積體電路元件之剖面示 意圚。 圖號說明： 10-基板 14-第一氮化矽層 Π-氧化層 20-第一氧化層 26-第二氧化層 34-源極/汲極區域 38-導電接觸窗 發明詳細說明： 首先，請參閱圖三、圖四及圓五，提供一已形成有一墊 氧化層（pad oxide layer) 12及一第一氮化矽層14的半導體 基板10，並利用微影及蝕刻技術於所述基板10中定義數個 淺溝渠（shallow trench) 16，其中所述淺溝渠係包括至少一 個寬溝渠及至少一個窄溝渠：接著，利用化學氣相沉積法 (Chemical Vapor Deposition; CVD)开多成一第一氧20 12-墊氧化層 關溝渠 19-寬溝渠區域 22-第二氮化矽層 32-閘極結構 36-介電隔離層 (·請先閲价背面之注項再填寫本頁) 裝-----1 111111. 本紙張尺度適用中國國家標準（CNS)A4規格(210 X 2切公釐） 415014 A7 B7 五、發明說明（f) 於所述基板10上，並填滿所述淺溝渠16。其中所述墊氧化 層12厚度係介於50A至250 A之間；所述第一鐵化矽層14 厚度係介於500A至2500 A之間；所述淺溝渠16深度係介 於2500A至5000人之間；所述第一氧化層20厚度係介於 5000A 至 16000 A 之間。 接下來形成之第二氮化矽層22頂蓋係爲本發明一重要 特徵，請參閱圖六，利用化學氣相沉積法或電漿增強化學氣 相沉積法（Plasma Enhanced Chemical Vapor Deposition; PECVD)於所述第一氧化層20上形成一第二氮化矽層22 頂蓋。其中所述第二氮化矽層22厚度係介於400A至2000 A 之間，而且所述第二氮化矽層22亦可以其他材質取代，只 要所述材質與第一氧化層20間具有足夠之研磨及蝕刻選擇 比。 接著，請參閱圖七及圖八，利用化學氣相沉積法或電漿 增強化學氣相沉積法於所述第二氮化矽層22頂蓋上形成一 第二氧化層26，並利用化學機械研磨法（Chemical Mechanic Polish; CMP)研磨所述第二氧化層26，以窄溝渠上方之第 二氮化矽層22被研磨移除，且露出第一氧化層20時爲研磨 終點，其中所述CMP係利用時間控制模式，目的在確保研 磨移除所述第二氮化矽層22，只留下位於寬溝渠位置上的 第二氮化矽層22。上述之第二氧化層26厚度係介於1000A 至5000 A之間，而且第二氧化層26與第一氧化層20最好 具有相同材質，但亦可爲兩種不同材質。 再接著，請參閱圖九，利用乾式蝕刻法完全移除所述第 請， 先 閲 讀， 背 事1 項I 再 填- I裝 訂 經濟邨智慧財產局員工消费合作社印製 ^^尺度適用中國國家標準（CNS)A4規格（210 X 2舴公釐 經濟部智慧財產局貝工消费合作社印製 415014 A7 B7 五、發明說明（L) 二氧化層26及第一氮化矽層14上方之第一氧化層20，並 以過度蝕刻氮化矽層時爲蝕刻終點。當蝕刻第二氮化矽層底 部時，繼續進行約10%至20%的過度蝕刻，因此可以將所 有覆蓋在第二氮化矽層22上之第二氧化層26完全移除。其 中所述過度蝕刻係使用了一可容易控制剩餘的氧化層厚度的 蝕刻終點偵測器（endpointdetector) » 綜上所述可以發現，本發明於寬溝渠上形成第二氮化矽 層22的設計，可消萌習知寬溝渠之凹陷問題。最後，請參 閱圖十，利用傳統之濕式蝕刻法移除所述寬溝渠區域上方之 第二氮化矽層22、第一氮化矽層14及墊氧化層14，完成了 淺溝渠隔離的製作。接下來即利用習知之製程步驟進行，例 如：製作一半導體元件結構，係包括有利用習知技藝形成之 閘極結構32、源極/汲極（source/drain)區域34及於介電隔 離層（dielectric isolation layer) 34間開啓之導電接觸窗38 等，如圖十一所示。 本發明係揭露一利用CMP及乾式蝕刻法來製作平坦的 淺溝渠隔離，並且消弭氧化層凹陷問題的方法，其中所述過 度蝕刻係使用了一可容易控制剩餘的氧彳b®厚度的蝕刻終點 偵測器。 上述說明係以較佳實施例來閫述本發明，而非限制本發 明，並且熟知半導體技藝之人士皆能明瞭，適當而作些微的 改變及調整，仍將不失本發明之要義所在，亦不脫離本發明 之精神和範圍。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 29+公釐）415014 A7 B7 V. Description of the Invention (/) Technical Field: The present invention relates to a method for manufacturing integrated circuits, and more particularly, to a method for manufacturing flat shallow trench isolation (STI) in the process of integrated circuits. Read the note on the back and fill in this page. J Background of the Invention: The shallow trench isolation (STI) process method has been widely used to provide isolation for active component intervals, especially in ultra-large integrated circuit (ULSI) components. . After the shallow trench isolation is formed, chemical mechanical polishing (CMP) is often used to perform good planarization. However, due to the deformation of the pad structure, the opening of the wide trench is easily ground to form a depression, resulting in a wide width. The phenomenon of thin oxide layer in the trench. Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of a structure of a partial integrated circuit element completed by a conventional technique, wherein the structure is a semiconductor substrate U having a silicon nitride layer 14 formed therein. A number of trenches have been defined and filled with an oxide layer 17 in the trenches. After the above structure is polished by CMP, the structure shown in FIG. 2 is formed. The depression phenomenon of the oxide layer 17 can be found in the wide trench region 19 indicated by the arrow, and the uniform structure of the oxide layer 17 in the wide trench region 19 is lacking. Sex. In the field of integrated circuits, there have been many researchers trying to avoid the above problems in the field of integrated circuits printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, a patent covering a trench oxide filling material is disclosed in US Patent No. 4,962,064. Use of a polycrystalline silicon layer, wherein the oxide material includes at least two etching steps during subsequent CMP polishing and planarization of dry or wet etching; U.S. Patent No. M94857 discloses a shallow The CMP process of the trench uses the inversion method. I paper size applies the Chinese National Standard (CNS) A4 specification (210 X 2¾ mm) 415014 A7 _ B7 V. Description of the invention (reverse-tone mask) in wide A block oxide and a silicon nitride structure are formed in the trench to stop the grinding; U.S. Patent No. 5,641,704 discloses the use of a flat conformal first oxide (conformal oxide) and a subsequently formed conformal second A process method for filling trenches with an oxide layer, wherein the filling forest material is etched by a chemical etching method to etch the active device area through a photomask pattern for planarization. Chemical treatment, followed by CMP treatment, and ending with a silicon nitride layer; U.S. Patent No. 54928 discloses a process method of 'forming a silicon nitride thin layer in the trench before filling the trench with an oxide layer, followed by And tempering the oxide layer, etching back the resistive layer, and performing CMP steps; U.S. Patent No. 5,663,107 discloses a method using a doped glass as a filling material and forming a silicon nitride layer thereon. The subsequent planarization process includes CMP, non-uniform etchback, dry etching to remove the nitride layer, and a second CMP step. Summary of the Invention: The main object of the present invention is to provide a method for forming a flat shallow trench isolation in an integrated circuit. Another object of the present invention is to provide a method for forming a flat shallow trench isolation and eliminating the phenomenon of sag of an oxide layer. Another object of the present invention is to provide a method for forming a flat shallow trench isolation and easily control the thickness of the remaining oxide layer. Method β Another object of the present invention is to provide a method for forming a flat shallow trench isolation by using a chemical mechanical polishing method and an accompanying dry etching method. In order to achieve the above-mentioned items, the present invention provides a method for forming a flat shallow trench in an integrated circuit. First, provide one that has been formed, read the notes on the back, and then fill out this page) .J. Nn 1_ n Order -------- Consumption Cooperation between Employees and Intellectual Property Bureau of the Ministry of Economy Du Printed Paper Standards General China Hoarding standard (CNS) A4 specification (210 X 2§7) 415014 A7 B7 V. Description of the invention ()) A semiconductor substrate with a first nitride layer and a plurality of isolation trenches defined on the substrate, wherein the trenches The system includes at least one wide trench and at least one narrow trench. Next, a first oxide layer is formed on the substrate and fills the isolation trench. Then, a second nitride layer cap is formed in sequence. layer) &-a second oxide layer, and grinding the second oxide layer, wherein the second oxide layer and the second nitride layer cover only a part of the wide trench area; and then, The dry contact etching method is used to etch the first oxide layer and the second oxide layer, and over-etch the first oxide layer, so that the etching is terminated by completely removing the second oxide layer in the second silicon nitride layer and exposing the first oxide layer. One nitrogen; finally, remove the second nitride layer and The first nitride layer completes the fabrication of the shallow trench isolation region of the integrated circuit element. Brief description of the drawings: Fig. 1 is a schematic cross-sectional view of the structure of a part of an integrated circuit device produced by a conventional technique. Figure 2 is a schematic cross-sectional view of a part of the integrated circuit device structure produced by conventional techniques after CMP grinding. FIG. 3 is a schematic cross-sectional view of forming a pad oxide layer and a first nitride layer on a semiconductor substrate according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a plurality of shallow trenches defined in a substrate according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of forming a first oxide layer in the embodiment of the present invention. Circle six is a schematic cross-sectional view of forming a second silicon nitride layer on a first oxide layer in an embodiment of the present invention. This paper size is applicable to China Solid Standard (CNS) A4 specification (210 X 2 ^ 7 mm) (_Please note on the back of tt · Fill in this page) Packing -------- Order- --------. Printed by the Consumer Property Cooperation Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs 415014 A7 _________ B7 Printed by the Consumer Cooperatives of the Smart Property Bureau of the Economic Village. Cross-sectional schematic diagram of forming a second oxide layer on a second silicon nitride layer "Yuanba is a cross-sectional schematic diagram of the second oxide layer and the second silicon nitride layer after CMP polishing in the embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of removing the remaining second oxide layer and exposing the first silicon nitride layer by etching according to the embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of forming a shallow trench isolation according to an embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of a complete integrated circuit element according to an embodiment of the present invention. Description of drawing numbers: 10-substrate 14-first silicon nitride layer Π-oxide layer 20-first oxide layer 26-second oxide layer 34-source / drain region 38-conductive contact window Detailed description of the invention: First, Please refer to FIG. 3, FIG. 4 and circle 5 to provide a semiconductor substrate 10 having a pad oxide layer 12 and a first silicon nitride layer 14 formed thereon, and using lithography and etching techniques on the substrate A plurality of shallow trenches 16 are defined in 10, wherein the shallow trench system includes at least one wide trench and at least one narrow trench: Next, a chemical vapor deposition method (Chemical Vapor Deposition; CVD) is used to open a first trench. Oxygen 20 12-pad oxide layer closed trench 19-wide trench area 22-second silicon nitride layer 32-gate structure 36-dielectric isolation layer (Please read the note on the back of the price before filling this page) ---- 1 111111. This paper size is in accordance with China National Standard (CNS) A4 (210 X 2 cut mm) 415014 A7 B7 V. Description of the invention (f) on the substrate 10, and fill the paper Ditch 16. The thickness of the pad oxide layer 12 is between 50A and 250 A; the thickness of the first silicon iron layer 14 is between 500A and 2500 A; and the depth of the shallow trench 16 is between 2500A and 5000. Between people; the thickness of the first oxide layer 20 is between 5000A and 16000 A. The top cover of the second silicon nitride layer 22 formed next is an important feature of the present invention. Referring to FIG. 6, a chemical vapor deposition method or plasma enhanced chemical vapor deposition (PECVD) method is used. A second silicon nitride layer 22 is formed on the first oxide layer 20. Wherein, the thickness of the second silicon nitride layer 22 is between 400 A and 2000 A, and the second silicon nitride layer 22 may be replaced by other materials, as long as there is sufficient space between the material and the first oxide layer 20. Grinding and etching selection ratio. Next, referring to FIGS. 7 and 8, a second oxide layer 26 is formed on the top cover of the second silicon nitride layer 22 by using a chemical vapor deposition method or a plasma enhanced chemical vapor deposition method. The second oxide layer 26 is polished by a polishing method (Chemical Mechanic Polish; CMP). The second silicon nitride layer 22 above the narrow trench is polished and removed, and the end point of the polishing is when the first oxide layer 20 is exposed. The CMP system uses a time-controlled mode to ensure that the second silicon nitride layer 22 is removed by polishing, leaving only the second silicon nitride layer 22 in a wide trench position. The thickness of the second oxide layer 26 is between 1000 A and 5000 A, and the second oxide layer 26 and the first oxide layer 20 are preferably made of the same material, but they can also be two different materials. Then, please refer to Figure 9 and use the dry etching method to completely remove the first request, read first, and then back to 1 item I and then fill-I binding Economic Village Intellectual Property Bureau employee consumer cooperative printed ^ ^ standard applicable Chinese national standards (CNS) A4 specification (210 X 2 mm printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 415014 A7 B7 V. Description of the invention (L) First oxidation over the oxide layer 26 and the first silicon nitride layer 14 Layer 20, and the end point of the etching is when the silicon nitride layer is over-etched. When the bottom of the second silicon nitride layer is etched, about 10% to 20% of the over-etching is continued, so all the second silicon nitride layer can be covered The second oxide layer 26 on layer 22 is completely removed. The over-etching uses an etching endpoint detector that can easily control the thickness of the remaining oxide layer. In summary, it can be found that the present invention The design of forming the second silicon nitride layer 22 on the wide trench can eliminate the problem of the depression of the wide trench. Finally, referring to FIG. 10, the second nitridation over the wide trench area is removed by using a conventional wet etching method. Silicon layer 22 The first silicon nitride layer 14 and the pad oxide layer 14 complete the production of shallow trench isolation. The next step is to use conventional process steps, for example, to fabricate a semiconductor device structure, which includes gates formed using conventional techniques. The structure 32, the source / drain region 34, and the conductive contact window 38 opened between the dielectric isolation layer 34 are shown in Fig. 11. The present invention discloses the use of CMP And dry etching to make flat shallow trench isolation and eliminate the problem of oxide layer depression, wherein the over-etching uses an etching endpoint detector that can easily control the remaining thickness of the oxygen oxide b®. The present invention is described in a preferred embodiment, rather than limiting the present invention, and those who are familiar with semiconductor technology will understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention, nor deviate from the present invention. The spirit and scope of the invention. This paper size is applicable to China National Standard (CNS) A4 (210 X 29 + mm)