409347 籽泸部屮夾^^Ληί-Τ消於合作卬 A7 B7 五、發明説明（/ ) 發明領域= 本發明係有關於積體電路裝置的製造，並且 更特別地是有關於一種在積體電路製造中用 以有效率地形成高品質氧化物淺溝渠隔離的 方法。 發明背景： 淺溝渠隔離法(STI)在積體電路製造中係漸 漸地受重視。多數的STI係使用臭氧-TEOS (四 乙基正矽酸鹽）塡隙，其次光阻回蝕以及化學 機械硏磨（CMP)而平坦化。 如Lee等人所發表的美國專利第5,229,3 1 6 號之傳統STI法係使用CMP作爲較佳的平坦化 蝕刻技術。此係接著以濕式蝕刻法移除犧牲材 % 料層。此將留下突出於上基板表面的一柱溝渠 塡充材料。該柱溝渠塡充材料必須於後序被平 坦化，其將使得溝渠的肩部變圓。該變圓的肩 部係爲諸如多晶矽閘極蝕刻等後續製程所 需。409347 泸 部 部 屮 ^^ Ληί-Τ Eliminates cooperation A7 B7 V. Description of the invention (/) Field of the invention = The present invention relates to the manufacture of integrated circuit devices, and more particularly to an integrated circuit device. Method for efficiently forming high-quality oxide shallow trench isolation in circuit manufacturing. BACKGROUND OF THE INVENTION: Shallow trench isolation (STI) is gaining increasing importance in the fabrication of integrated circuits. Most STIs are flattened using ozone-TEOS (tetraethyl orthosilicate) gaps, followed by photoresist etchback and chemical mechanical honing (CMP). The traditional STI method, such as US Patent No. 5,229,316, published by Lee et al., Uses CMP as a preferred planarization etching technique. This system then removes the sacrificial material% layer by wet etching. This will leave a pillar trench filling material protruding from the surface of the upper substrate. The pillar trench filling material must be flattened in the subsequent sequence, which will round the shoulder of the trench. This rounded shoulder is needed for subsequent processes such as polysilicon gate etching.
Fazan 與 Mathes 發表於"A Highly Manufacturable Trench Isolation Process of Deep Submicron DRAMS/'IEDM Tech Digst 93-57, p.3·6.1至3.6.4係說明使用結合可棄式氧化 物I間隙壁形成的濕式蝕刻法而避免溝渠邊緣 變銳角的方法。該技術亦說明於Fazan所發表的 I紙張尺度逆扣中®國家標隼（CNS〉Λ4規格（210X^97公釐） (锖先閱讀背面之註意事項苒填寫本萸)Fazan and Mathes published in "A Highly Manufacturable Trench Isolation Process of Deep Submicron DRAMS / 'IEDM Tech Digst 93-57, p. 3.6.1 to 3.6.4. Method for avoiding sharp angles of trench edges by using an etching method. This technology is also explained in the I-paper size reverse buckle published by Fazan® National Standard (CNS> Λ4 Specification (210X ^ 97 mm) (锖 Read the precautions on the back first 苒 Fill this 萸)
409347 A7 B7 五、發明説明（>) 美國專利第5,433,794號中。 必須避免在溝渠邊緣產生銳角，因爲其爲形 成各種裝置漏電流的機制，諸如不規則啓始電 流、閘極對汲極重疊區與溝渠角產生的交叉處 的閘極誘發汲極漏電流及多晶矽發生短路的· 多晶砂枕。409347 A7 B7 V. Description of the Invention (>) US Patent No. 5,433,794. Acute angles must be avoided at the edges of trenches, as they are mechanisms for forming various device leakage currents, such as irregular start currents, gate-induced drain leakage at the intersection of gate-drain overlap and trench angle, and polycrystalline silicon Short-circuited polycrystalline sand pillow.
Chang 與 Sze 在 McGraw-Hill 所出版的 ULSI Technology , 1997，p.354中表示各種氮化矽 (SiN)與二氧化矽（Si02)用的乾式蝕刻化學物 質。Chang and Sze in ULSI Technology, 1997, p.354 by McGraw-Hill, describe various dry etching chemicals for silicon nitride (SiN) and silicon dioxide (Si02).
Jang等人所發表的美國專利第5,731，241號 係表示位於STI隔離層上的一自行對齊犠牲氧 化層以及該犧牲氧化層的回蝕。Jang並未同時 蝕刻氮化矽層及氧化層。U.S. Patent No. 5,731,241, issued by Jang et al., Describes a self-aligned silicon oxide layer on an STI barrier layer and the etch-back of the sacrificial oxide layer. Jang did not etch the silicon nitride layer and the oxide layer at the same time.
Lee等人所發表的美國專利第5,229,3 1 6號 '^係表示一種使用濕式蝕刻該柱溝渠塡充材料 而使溝渠角變圓的方法。該方法蝕刻該柱溝渠 塡充材料，使其與氮化層分離。 本發明係使用步驟移除犧牲層並留下變圚 的肩部於溝渠角上之一種特殊的乾式蝕刻法 取代前述的二階段步驟：（1)移除犧牲材料層以 及（2)將該柱溝渠塡充材料平坦化。 發明槪述： 因此，本發明的主要目的係爲提供一種用以 Γ 丨一^J· (請先閲讀背面之注意事項再填寫本頁) 裝· 釘 本紙張尺度適川中國國家標準（CNS ) Λ4規格（210X297公釐） 耔：^部屮^^^^力工消价合作社卬^ 409347 A7 ________________B7_ 五、發明説明（)） 在積體電路製造中形成自行變圓淺溝渠隔離 的方法。 .本發明的另一個目的係爲提供一種用以使 用較少的加工步驟而有效率地形成高品質氧 化物淺溝渠隔離的方法。 根據本發明的目的，一種用以形成自行變圓 淺溝渠隔離的方法係已達成。一襯墊氧化層係 設於半導體基板表面。其次，一氮化層係沈積 於該襯墊氧化層上。其次，隔離溝渠係使用蝕 刻方式穿經該氮化物及襯墊氧化層而進入半 導體基板。其次，一氧化層係沈積於該氮化層 上以及該隔離溝渠中。其次，氧化層係藉由化 學機械硏磨而被硏磨移除，其中該基板係爲平 ' 坦。其次，該氮化層係使用對氮化矽蝕刻速率 較對氧化物高的特殊乾式蝕刻法蝕刻移除。該 '乾式蝕刻法對於矽基板亦有極低的蝕刻速 率。此舉將使氮化層被移除，使溝渠肩部變圓 並留下未受影響的基板。積體電路裝置的製造 完成。 圖式簡要說明： 第1圖至第5圖係爲本發明之第一個較佳實 施例的截面圖。 .第6圖至第10圖係爲本發明之第二個較佳實 施例的截面圖。 (諳先閱讀背面之注意事項再填寫本頁) -裝. 丁 . 丨·50 本紙張尺度適用屮國國家標準（CNS ) Λ4規格（210X297公釐） 409347 A7 B7 五、發明说明（f) 第11圖係爲以本發明之方法所製造的完整 積體電路裝置的截面圖。 圖號說明： 10-半導體基板 13-犧牲氧化層 16-淺溝渠 20-閘極電極 12-襯墊氧化矽層 14-氮化矽層 17-氧化層 24-源極/汲極區 發明詳細說明： 第一實施例 首先，請參考第1圖，一襯墊氧化矽層12(pad silicon oxide)係於該半導體基板10表面上成長 大約90至300A間的厚度。接著，一氮化矽層14 係於該襯墊氧化矽層12上成長大約1500至 3000&間的厚度。 接續，參考第2圖，淺溝渠16(shallow trench) 係使用傳統光學微影（photolithography)及蝕刻 技術而蝕刻入半導體基板10。該淺溝渠1 6係蝕 刻入半導體基板10內大約2500至5000 A間的深 度。 參考第3圖，一氧化層17係以化學氣相沈積 法（Chemical vapor deposition ;CVD)沈積大 約5〇00至8000A間的厚度於半導體基板10表面 並塡充該淺溝渠16。 其次，該氧化層17係使用化學機械硏磨法 (諳先閱讀背面之注意事項再填寫本頁) .裝. • IL. 丁 本纸張尺度適州中囤國家標準（CNS ) Λ4規格（2丨οχ297公釐） 409347 五、發明説明（f) {#先閱讀背面之注意事項再填寫本頁) (chemical mechanical polish ; CMP )硏磨而形 成第4圖中所舉例的平坦淺溝渠隔離。氧化層 17係被硏磨至位於半導體基板10表面上大約 2500至5000A間的厚度》 接續，請參考第5圖，位於半導體基板10表 面上的氮化砂層14及氧化層1 7係使用乾式蝕 刻（dry etching)未移除。一特殊的乾式蝕刻法 係用於本步驟中。該蝕刻法的主要參數爲：介 於2 seem至1 0 seem間的氧氣（〇2)流量，介於 ' 5 seem至30 seem間的三氟化甲院（CHF3 )流 量，以及介於5 seem至30 seem間的四氟化碳 (CF4 )流量，大約10 m Torr至200 m Torr間的 壓力以及介於300 Watts至800 Watts間的射頻 功率（Rf Dower)。氧化矽對氮化矽的蝕刻選擇 比係爲1 : (1.1〜1.5)。 使用該乾式触刻製程（dry etching process)，移除氮化矽層14及襯墊氧化層12時 將使氧化層17的肩部變圓。該蝕刻法對半導體 基板10具有極低的蝕刻速率，因此，該蝕刻可 於半導體基板10終止，而且，氮化矽半導體基 板10的選擇性係大於5。 第二實施例 然而，上述之乾式蝕刻可能會損傷半導體基 板10表面。根據本發明的另一方法係於第6圖 至第10圖中做說明。第1-5圖的實施例中的各層 _______6------- 本紙張尺度適;U屮囤國家標準（CNS ) Λ4规格（2丨0X297公釐} 409347 A7 -----------------------------Β7 五、發明説明（&) 中所使用的標號與第6-10圖的實施例相同。在 該實施例中，一犧牲氧化層係被使用以保護基 板表面不受到餽刻損傷。 參考第6圖，一犧牲氧化層13已被沈積於該 襯墊氧化層U上。當在本實施例中使用乾式蝕 刻’該犧牲氧化層12可使用以保護半導體基板 1〇不受乾式蝕刻的影響。該犧牲氧化層12具有 大約150至500A的厚度。 參考第7圖，淺溝渠16係使用傳統光學微影 及蝕刻技術而被蝕刻進入上述的半導體基板 中。 上述之氧化層17係以化學氣相沈積法 (CVD)沈積大約5000至8000A間的厚度於半 導體10基板表面並塡充該淺溝渠16，如第8圖 '所示。 其次，該氧化層17係使闬化學機械硏磨法 (CMP)硏磨而形成第9圖中所舉例的平坦淺 溝渠隔離。氧化層17係被硏磨至位於半導體基 板10表面上大約2500至5000A間的厚度。 參考第10圖，其次，位於半導體基板1〇表面 上的氮化矽層14及氧化層Π係使用上述的特 殊乾式蝕刻法而被移除。在此實施例中，因爲 犧牲氧化層13的出現，所以部份的襯墊氧化層 12在氮化矽層14完全移除後仍殘留’且氧化物 17的肩部已變圓。 (請先閲讀背面之注意事項再§本頁) .裝. -¾ ★ 本紙张尺度適州中國围家標準（CNS ) Λ4規格< 公釐） A7 409347 五、發明説明（7 ) 本發明的方法係使用乾式蝕刻製程而形成 平坦化的淺溝渠隔離。該乾式蝕刻製程在單一 步驟中同時移除該氮化矽層並使塡充溝渠的 氧化物肩部變圓。本步驟係較使用二階段以獲 致相同效果的傳統濕式蝕刻製程更有效率。本 方法的結果係表示於第5圖及第10圖中。 接續，完成平坦化的淺溝渠隔離後與傳統方 式相同，在半導體裝置結構於STI區域間或上 方的半導體基板中或上方。例如，如第11圖所 舉例，閘極電極20及源極/汲極區24已被形成於 STI區域間的半導體基板中或上方。接下去習 知之製作半導體元件步驟：如形成絕緣層或連 線結構並未在此說明。 雖然本發明已被特別地揭示並參考較佳實 施例做說明，但各種形式的改變與細節可於不 '違背本發明之精神與範疇下爲之係爲熟習本 技藝之人士所瞭解的。 (請先閱讀背面之注意事項再填寫本頁) .裝. -訂 好"'‘部中夾":·^^,Β-τίΛ·^Ι;合作打卬於 紙珉尺度適州中囤國家標準（CNS ) Λ4規格（210Χ 297公釐）U.S. Patent No. 5,229,316 published by Lee et al. Represents a method for rounding the trench angle using wet etching of the pillar trench filling material. The method etches the pillar trench filling material to separate it from the nitride layer. The present invention uses a special dry etching method that removes the sacrificial layer and leaves the shackled shoulders on the trench corners in steps to replace the aforementioned two-stage steps: (1) removing the sacrificial material layer and (2) placing the pillar The trench filling material is flattened. Description of the invention: Therefore, the main purpose of the present invention is to provide a method for Γ 丨 a ^ J · (please read the precautions on the back before filling this page). Λ4 specification (210X297 mm) 耔: ^ 部 屮 ^^^^ 力 工 消 价 价 社 卬 ^ 409347 A7 ________________B7_ V. Description of the invention ()) A method of forming a self-turning and shallow trench isolation in integrated circuit manufacturing. Another object of the present invention is to provide a method for efficiently forming a high-quality oxide shallow trench isolation with fewer processing steps. According to the object of the present invention, a method for forming a self-rounding shallow trench isolation has been achieved. A pad oxide layer is provided on the surface of the semiconductor substrate. Next, a nitride layer is deposited on the pad oxide layer. Second, the isolation trenches are etched through the nitride and pad oxide layers into the semiconductor substrate. Next, an oxide layer is deposited on the nitride layer and in the isolation trench. Secondly, the oxide layer is removed by honing by chemical mechanical honing, wherein the substrate is flat. Secondly, the nitrided layer is removed by etching using a special dry etching method which has a higher etching rate for silicon nitride than for oxides. The 'dry etching method' also has a very low etching rate for silicon substrates. This will remove the nitride layer, round the trench shoulders and leave the unaffected substrate. Manufacturing of integrated circuit devices is completed. Brief description of the drawings: Figures 1 to 5 are sectional views of the first preferred embodiment of the present invention. 6 to 10 are cross-sectional views of a second preferred embodiment of the present invention. (Please read the precautions on the back before filling this page) -Packing. Ding. 丨 · 50 This paper size applies the national standard (CNS) Λ4 specification (210X297 mm) 409347 A7 B7 V. Description of the invention (f) Article 11 is a cross-sectional view of a complete integrated circuit device manufactured by the method of the present invention. Description of figure number: 10-semiconductor substrate 13-sacrificial oxide layer 16- shallow trench 20-gate electrode 12-pad silicon oxide layer 14-silicon nitride layer 17-oxide layer 24-source / drain region : First Embodiment First, referring to FIG. 1, a pad silicon oxide layer 12 (pad silicon oxide) is grown on the surface of the semiconductor substrate 10 by a thickness of about 90 to 300 A. Next, a silicon nitride layer 14 is grown on the pad silicon oxide layer 12 to a thickness of about 1500 to 3000 & Next, referring to FIG. 2, the shallow trench 16 is etched into the semiconductor substrate 10 using conventional photolithography and etching techniques. The shallow trench 16 is etched into the semiconductor substrate 10 to a depth of about 2500 to 5000 A. Referring to FIG. 3, an oxide layer 17 is deposited on the surface of the semiconductor substrate 10 by a chemical vapor deposition (CVD) method to a thickness of about 5000 to 8000 A and fills the shallow trench 16. Secondly, this oxide layer 17 uses chemical mechanical honing method (read the precautions on the back before filling this page). Packing. • IL. Titanium Paper Standard Shizhou National Standard (CNS) Λ4 Specification (2丨 οχ297 mm) 409347 V. Description of the invention (f) {#Read the precautions on the back before filling this page) (chemical mechanical polish; CMP) Honed to form the flat shallow trench isolation illustrated in Figure 4. The oxide layer 17 is honed to a thickness of about 2500 to 5000 A on the surface of the semiconductor substrate 10. Continuing, please refer to FIG. 5. The nitrided sand layer 14 and the oxide layer 17 on the surface of the semiconductor substrate 10 are dry-etched (Dry etching) is not removed. A special dry etching method is used in this step. The main parameters of this etching method are: the flow rate of oxygen (〇2) between 2 seem and 10 seem, the flow of trifluoride A (CHF3) flow between 5 seem and 30 seem, and 5 seem Carbon tetrafluoride (CF4) flow from 30 to 30 seem, pressure between about 10 m Torr and 200 m Torr, and RF power (Rf Dower) between 300 Watts and 800 Watts. The etching selection ratio of silicon oxide to silicon nitride is 1: (1.1 to 1.5). Using this dry etching process, when the silicon nitride layer 14 and the pad oxide layer 12 are removed, the shoulders of the oxide layer 17 are rounded. This etching method has an extremely low etching rate for the semiconductor substrate 10, so that the etching can be terminated at the semiconductor substrate 10, and the selectivity of the silicon nitride semiconductor substrate 10 is greater than 5. Second Embodiment However, the dry etching described above may damage the surface of the semiconductor substrate 10. Another method according to the present invention is illustrated in FIGS. 6 to 10. Each layer in the embodiment of Figs. 1-5 _______ 6 --------- This paper is suitable in size; U 屮 national standard (CNS) Λ4 specification (2 丨 0X297 mm) 409347 A7 ------ ----------------------- B7 5. The symbols used in the & description of the invention are the same as those in the embodiment of Figs. 6-10. In the embodiment, a sacrificial oxide layer is used to protect the surface of the substrate from feeding damage. Referring to FIG. 6, a sacrificial oxide layer 13 has been deposited on the pad oxide layer U. When used in this embodiment Dry etching 'The sacrificial oxide layer 12 can be used to protect the semiconductor substrate 10 from dry etching. The sacrificial oxide layer 12 has a thickness of about 150 to 500 A. Referring to FIG. 7, the shallow trench 16 uses conventional optical lithography And etching technology to be etched into the semiconductor substrate. The oxide layer 17 is deposited by chemical vapor deposition (CVD) to a thickness of about 5000 to 8000 A on the surface of the semiconductor 10 substrate and fills the shallow trench 16, such as It is shown in FIG. 8. Next, the oxide layer 17 is formed by honing a chemical mechanical honing method (CMP) to form a flat plate as exemplified in FIG. 9. Shallow trench isolation. The oxide layer 17 is honed to a thickness between approximately 2500 and 5000 A on the surface of the semiconductor substrate 10. Referring to FIG. 10, secondly, the silicon nitride layer 14 and the oxide layer Π on the surface of the semiconductor substrate 10. It was removed using the special dry etching method described above. In this embodiment, because of the appearance of the sacrificial oxide layer 13, part of the pad oxide layer 12 remains after the silicon nitride layer 14 is completely removed 'and The shoulder of the oxide 17 has been rounded. (Please read the precautions on the back before § this page). Packing. 5. Description of the invention (7) The method of the present invention uses a dry etching process to form a flat shallow trench isolation. The dry etching process simultaneously removes the silicon nitride layer in a single step and rounds the oxide shoulders of the trenches. This step is more efficient than the traditional wet etching process using two stages to achieve the same effect. The results of this method are shown in Figures 5 and 10. Subsequently, the planarized shallow trench isolation is the same as the conventional method, and the semiconductor device structure is in or above the semiconductor substrate between or above the STI region. For example, as shown in FIG. 11, the gate electrode 20 and the source / drain region 24 have been formed in or above a semiconductor substrate between STI regions. The conventional steps for fabricating a semiconductor device, such as forming an insulating layer or a wiring structure, are not described here. Although the present invention has been particularly disclosed and described with reference to preferred embodiments, various changes and details may be understood by those skilled in the art without departing from the spirit and scope of the present invention. (Please read the notes on the back before filling in this page) National Standard (CNS) Λ4 specification (210 × 297 mm)