TW367587B - Manufacturing method for on-chip interconnected wiring without damage to inter-layer dielectric - Google Patents

Abstract

The invention relates to an improved manufacturing method for on-chip interconnected wiring structure which is to depose a metal layer or inorganic dielectric as passivation layer before via etching and used to cover the exposed surface of inter-metal dielectric with low dielectric constant so that after forming the via and to remove the photo-resist, the said inter-metal dielectric will be damaged by oxygen plasma etching or organic solvent. The method is to provide a semiconductor substrate with the first layer of metal wiring formed; on the semiconductor substrate and the first layer of metal wiring, it covers the first dielectric, an etching stop layer, and the second dielectric with low dielectric constant; then, selectively etching the second dielectric and used to form a trench for following accommodation for the second layer of wiring; then, form a passivation layer in the trench, sidewall and surface of second dielectric; employing photo-resist as the mask to selectively etch the passivation layer, etching stop layer and the first dielectric layer which are used to form the via of the first layer of metal wiring connected in the said trench area to constitute an on-chip opening structure; then, removing the said photo-resist layer and preventing damage of sidewall of the second dielectric by the passivation layer; then, filling a conductive layer in the trench and contacts to accomplish the process of on-chip interconnected wiring structure.