TW365063B - Single chip memory system and the operation method thereof - Google Patents

Single chip memory system and the operation method thereof

Info

Publication number
TW365063B
TW365063B TW086115919A TW86115919A TW365063B TW 365063 B TW365063 B TW 365063B TW 086115919 A TW086115919 A TW 086115919A TW 86115919 A TW86115919 A TW 86115919A TW 365063 B TW365063 B TW 365063B
Authority
TW
Taiwan
Prior art keywords
memory cell
data
sense amplifier
transferred
type flip
Prior art date
Application number
TW086115919A
Other languages
English (en)
Inventor
Kiminori Hayano
Yasuhiro Maeda
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Application granted granted Critical
Publication of TW365063B publication Critical patent/TW365063B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
TW086115919A 1996-10-29 1997-10-28 Single chip memory system and the operation method thereof TW365063B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08286607A JP3130807B2 (ja) 1996-10-29 1996-10-29 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW365063B true TW365063B (en) 1999-07-21

Family

ID=17706610

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086115919A TW365063B (en) 1996-10-29 1997-10-28 Single chip memory system and the operation method thereof

Country Status (4)

Country Link
US (1) US5930190A (zh)
JP (1) JP3130807B2 (zh)
KR (1) KR100301542B1 (zh)
TW (1) TW365063B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100329024B1 (ko) * 1998-03-27 2002-03-18 아끼구사 나오유끼 파괴 읽기형 메모리 회로, 이를 위한 리스토어 회로 및 감지 증폭기
US6046924A (en) * 1998-06-19 2000-04-04 Kabushiki Kaisha Toshiba Semiconductor memory device having a sense amplifier region formed in a triple-well structure
JP2000040370A (ja) * 1998-07-24 2000-02-08 Nec Corp 半導体記憶装置
JP2003158205A (ja) * 2001-11-26 2003-05-30 Hitachi Ltd 半導体装置及び製造方法
JP5710945B2 (ja) * 2010-11-25 2015-04-30 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125891A (ja) * 1990-09-17 1992-04-27 Oki Electric Ind Co Ltd 半導体記憶装置
JP3129336B2 (ja) * 1991-12-09 2001-01-29 沖電気工業株式会社 半導体記憶装置
KR0139496B1 (ko) * 1994-06-21 1998-06-01 윤종용 반도체 메모리장치의 비트라인 감지증폭기
KR0177776B1 (ko) * 1995-08-23 1999-04-15 김광호 고집적 반도체 메모리 장치의 데이타 센싱회로

Also Published As

Publication number Publication date
US5930190A (en) 1999-07-27
KR19980033235A (ko) 1998-07-25
JPH10135422A (ja) 1998-05-22
KR100301542B1 (ko) 2001-11-22
JP3130807B2 (ja) 2001-01-31

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees