TW359010B - Method of producing a semiconductor body - Google Patents

Method of producing a semiconductor body

Info

Publication number
TW359010B
TW359010B TW087101069A TW87101069A TW359010B TW 359010 B TW359010 B TW 359010B TW 087101069 A TW087101069 A TW 087101069A TW 87101069 A TW87101069 A TW 87101069A TW 359010 B TW359010 B TW 359010B
Authority
TW
Taiwan
Prior art keywords
semiconductor
layer
sector
insulation layer
producing
Prior art date
Application number
TW087101069A
Other languages
English (en)
Inventor
Matthias Stecher
Hermann Peri
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW359010B publication Critical patent/TW359010B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW087101069A 1997-02-12 1998-01-26 Method of producing a semiconductor body TW359010B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19705351A DE19705351C2 (de) 1997-02-12 1997-02-12 Verfahren zum Herstellen eines Halbleiterkörpers

Publications (1)

Publication Number Publication Date
TW359010B true TW359010B (en) 1999-05-21

Family

ID=7820024

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087101069A TW359010B (en) 1997-02-12 1998-01-26 Method of producing a semiconductor body

Country Status (6)

Country Link
US (1) US6057199A (zh)
EP (1) EP0859401B1 (zh)
JP (1) JPH11145473A (zh)
KR (1) KR100402143B1 (zh)
DE (2) DE19705351C2 (zh)
TW (1) TW359010B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6368970B1 (en) * 2000-08-24 2002-04-09 Infineon Technologies Ag Semiconductor configuration and corresponding production process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0120196B1 (ko) * 1987-05-13 1997-10-17 미다 가쓰시게 반도체 집적회로장치 및 그 제조방법
US5573967A (en) * 1991-12-20 1996-11-12 Industrial Technology Research Institute Method for making dynamic random access memory with fin-type stacked capacitor
JP2705476B2 (ja) * 1992-08-07 1998-01-28 ヤマハ株式会社 半導体装置の製造方法
DE4434108A1 (de) * 1994-09-23 1996-03-28 Siemens Ag Verfahren zur Erzeugung eines niederohmigen Kontaktes zwischen einer Metallisierungsschicht und einem Halbleitermaterial
US5710073A (en) * 1996-01-16 1998-01-20 Vanguard International Semiconductor Corporation Method for forming interconnections and conductors for high density integrated circuits
US5736441A (en) * 1996-03-15 1998-04-07 United Microelectronics Corporation High-capacitance dynamic random access memory cell and method for fabricating the same
US5895239A (en) * 1998-09-14 1999-04-20 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts

Also Published As

Publication number Publication date
KR19980071215A (ko) 1998-10-26
DE19705351A1 (de) 1998-08-20
JPH11145473A (ja) 1999-05-28
DE59812312D1 (de) 2005-01-05
EP0859401A2 (de) 1998-08-19
KR100402143B1 (ko) 2004-03-12
EP0859401B1 (de) 2004-12-01
EP0859401A3 (de) 1999-12-15
DE19705351C2 (de) 1998-12-03
US6057199A (en) 2000-05-02

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees