TW350108B - A power-ground plane for a C4 flip-chip substrate - Google Patents
A power-ground plane for a C4 flip-chip substrateInfo
- Publication number
- TW350108B TW350108B TW086108837A TW86108837A TW350108B TW 350108 B TW350108 B TW 350108B TW 086108837 A TW086108837 A TW 086108837A TW 86108837 A TW86108837 A TW 86108837A TW 350108 B TW350108 B TW 350108B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductive plane
- flip
- power
- ground plane
- chip substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/669,620 US5708296A (en) | 1996-06-24 | 1996-06-24 | Power-ground plane for a C4 flip-chip substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
TW350108B true TW350108B (en) | 1999-01-11 |
Family
ID=24687040
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086108837A TW350108B (en) | 1996-06-24 | 1997-06-24 | A power-ground plane for a C4 flip-chip substrate |
Country Status (7)
Country | Link |
---|---|
US (2) | US5708296A (zh) |
AU (1) | AU3504397A (zh) |
DE (2) | DE19781846B4 (zh) |
GB (1) | GB2330235B (zh) |
MY (1) | MY117529A (zh) |
TW (1) | TW350108B (zh) |
WO (1) | WO1997050123A1 (zh) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5708296A (en) * | 1996-06-24 | 1998-01-13 | Intel Corporation | Power-ground plane for a C4 flip-chip substrate |
US5898576A (en) * | 1996-11-12 | 1999-04-27 | Bay Networks Inc. | Printed circuit board including a terminated power plane and method of manufacturing the same |
US9054094B2 (en) | 1997-04-08 | 2015-06-09 | X2Y Attenuators, Llc | Energy conditioning circuit arrangement for integrated circuit |
US7336468B2 (en) | 1997-04-08 | 2008-02-26 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
US7321485B2 (en) | 1997-04-08 | 2008-01-22 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
JPH10303562A (ja) * | 1997-04-30 | 1998-11-13 | Toshiba Corp | プリント配線板 |
US6175161B1 (en) * | 1998-05-22 | 2001-01-16 | Alpine Microsystems, Inc. | System and method for packaging integrated circuits |
US5898217A (en) * | 1998-01-05 | 1999-04-27 | Motorola, Inc. | Semiconductor device including a substrate having clustered interconnects |
US6008534A (en) * | 1998-01-14 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines |
TW383482B (en) * | 1998-02-13 | 2000-03-01 | United Microelectronics Corp | Multi-layered metal wiring structure for reducing simultaneous switching noise |
US6246112B1 (en) | 1998-06-11 | 2001-06-12 | Intel Corporation | Interleaved signal trace routing |
EP1104584A1 (de) * | 1998-07-28 | 2001-06-06 | Siemens Aktiengesellschaft | Leiterbahnrahmen, platine mit leiterbahnrahmen und verfahren zur herstellung eines leiterbahnrahmens |
US6304792B1 (en) * | 1998-11-17 | 2001-10-16 | Advanced Micro Devices, Inc. | Separation of a multi-layer integrated circuit device and package |
JP4246835B2 (ja) * | 1999-03-09 | 2009-04-02 | ローム株式会社 | 半導体集積装置 |
US6127728A (en) * | 1999-06-24 | 2000-10-03 | Lsi Logic Corporation | Single reference plane plastic ball grid array package |
US6225690B1 (en) | 1999-12-10 | 2001-05-01 | Lsi Logic Corporation | Plastic ball grid array package with strip line configuration |
US7247932B1 (en) * | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
US6356453B1 (en) * | 2000-06-29 | 2002-03-12 | Amkor Technology, Inc. | Electronic package having flip chip integrated circuit and passive chip component |
US6546620B1 (en) | 2000-06-29 | 2003-04-15 | Amkor Technology, Inc. | Flip chip integrated circuit and passive chip component package fabrication method |
US6380633B1 (en) * | 2000-07-05 | 2002-04-30 | Siliconware Predision Industries Co., Ltd. | Pattern layout structure in substrate |
US6507118B1 (en) | 2000-07-14 | 2003-01-14 | 3M Innovative Properties Company | Multi-metal layer circuit |
US6970362B1 (en) | 2000-07-31 | 2005-11-29 | Intel Corporation | Electronic assemblies and systems comprising interposer with embedded capacitors |
US6775150B1 (en) | 2000-08-30 | 2004-08-10 | Intel Corporation | Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture |
JP3857042B2 (ja) * | 2000-11-27 | 2006-12-13 | 富士通テン株式会社 | 基板構造 |
US6879492B2 (en) | 2001-03-28 | 2005-04-12 | International Business Machines Corporation | Hyperbga buildup laminate |
US7042084B2 (en) * | 2002-01-02 | 2006-05-09 | Intel Corporation | Semiconductor package with integrated heat spreader attached to a thermally conductive substrate core |
US6680530B1 (en) * | 2002-08-12 | 2004-01-20 | International Business Machines Corporation | Multi-step transmission line for multilayer packaging |
US6803649B1 (en) * | 2003-05-16 | 2004-10-12 | Intel Corporation | Electronic assembly |
JP4195883B2 (ja) * | 2004-02-04 | 2008-12-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 多層モジュール |
CN100367491C (zh) * | 2004-05-28 | 2008-02-06 | 日本特殊陶业株式会社 | 中间基板 |
US7075185B2 (en) * | 2004-09-14 | 2006-07-11 | Hewlett-Packard Development Company, L.P. | Routing vias in a substrate from bypass capacitor pads |
GB2439861A (en) | 2005-03-01 | 2008-01-09 | X2Y Attenuators Llc | Internally overlapped conditioners |
DE102005046450A1 (de) * | 2005-09-28 | 2007-04-05 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip, Verfahren zu dessen Herstellung und optoelektronisches Bauteil |
JP4844080B2 (ja) * | 2005-10-18 | 2011-12-21 | 日本電気株式会社 | 印刷配線板及びその電源雑音抑制方法 |
US8158890B1 (en) * | 2008-02-20 | 2012-04-17 | Altera Corporation | Method and apparatus for low inductive design pattern |
US9565762B1 (en) * | 2013-12-06 | 2017-02-07 | Marvell Israel (M.I.S.L) Ltd. | Power delivery network in a printed circuit board structure |
US20160356842A1 (en) * | 2015-06-02 | 2016-12-08 | Advantest Corporation | Millimeter wave pogo pin contactor design |
US10114067B2 (en) | 2016-02-04 | 2018-10-30 | Advantest Corporation | Integrated waveguide structure and socket structure for millimeter waveband testing |
US10944148B2 (en) | 2016-02-04 | 2021-03-09 | Advantest Corporation | Plating methods for modular and/or ganged waveguides for automatic test equipment for semiconductor testing |
US10393772B2 (en) | 2016-02-04 | 2019-08-27 | Advantest Corporation | Wave interface assembly for automatic test equipment for semiconductor testing |
US10381707B2 (en) | 2016-02-04 | 2019-08-13 | Advantest Corporation | Multiple waveguide structure with single flange for automatic test equipment for semiconductor testing |
US9838076B2 (en) | 2016-03-22 | 2017-12-05 | Advantest Corporation | Handler with integrated receiver and signal path interface to tester |
US10371716B2 (en) | 2016-06-29 | 2019-08-06 | Advantest Corporation | Method and apparatus for socket power calibration with flexible printed circuit board |
US10701794B2 (en) * | 2018-10-26 | 2020-06-30 | Pegatron Corporation | Printed circuit board and power copper surface configuration method thereof |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4667219A (en) * | 1984-04-27 | 1987-05-19 | Trilogy Computer Development Partners, Ltd. | Semiconductor chip interface |
JP3033972B2 (ja) * | 1989-06-15 | 2000-04-17 | 日本特殊陶業株式会社 | アルミナ多層配線基板及びその製造方法 |
US5274337A (en) * | 1991-05-03 | 1993-12-28 | Intel Corporation | Clock speed limiter for a microprocessor by comparing clock signal with a predetermined frequency |
JPH04361559A (ja) * | 1991-06-10 | 1992-12-15 | Ngk Spark Plug Co Ltd | 集積回路用パッケージ |
US5450290A (en) * | 1993-02-01 | 1995-09-12 | International Business Machines Corporation | Printed circuit board with aligned connections and method of making same |
JP3355353B2 (ja) * | 1993-08-20 | 2002-12-09 | ケル株式会社 | 電気コネクタ |
US5708296A (en) * | 1996-06-24 | 1998-01-13 | Intel Corporation | Power-ground plane for a C4 flip-chip substrate |
-
1996
- 1996-06-24 US US08/669,620 patent/US5708296A/en not_active Expired - Lifetime
-
1997
- 1997-06-23 AU AU35043/97A patent/AU3504397A/en not_active Abandoned
- 1997-06-23 GB GB9828348A patent/GB2330235B/en not_active Expired - Fee Related
- 1997-06-23 WO PCT/US1997/011060 patent/WO1997050123A1/en active Application Filing
- 1997-06-23 DE DE19781846A patent/DE19781846B4/de not_active Expired - Lifetime
- 1997-06-23 DE DE19781846T patent/DE19781846T1/de not_active Withdrawn
- 1997-06-24 TW TW086108837A patent/TW350108B/zh not_active IP Right Cessation
- 1997-06-24 MY MYPI97002829A patent/MY117529A/en unknown
- 1997-10-07 US US08/946,415 patent/US5886406A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO1997050123A1 (en) | 1997-12-31 |
MY117529A (en) | 2004-07-31 |
DE19781846B4 (de) | 2005-03-31 |
US5886406A (en) | 1999-03-23 |
US5708296A (en) | 1998-01-13 |
DE19781846T1 (de) | 1999-05-12 |
GB9828348D0 (en) | 1999-02-17 |
GB2330235A (en) | 1999-04-14 |
GB2330235B (en) | 2001-04-11 |
AU3504397A (en) | 1998-01-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |