TW333707B - The method of forming power semiconductor device with controllable integrated buffer - Google Patents

The method of forming power semiconductor device with controllable integrated buffer

Info

Publication number
TW333707B
TW333707B TW086111623A TW86111623A TW333707B TW 333707 B TW333707 B TW 333707B TW 086111623 A TW086111623 A TW 086111623A TW 86111623 A TW86111623 A TW 86111623A TW 333707 B TW333707 B TW 333707B
Authority
TW
Taiwan
Prior art keywords
doping
substrate
semiconductor device
buffer
conductive
Prior art date
Application number
TW086111623A
Other languages
English (en)
Inventor
Anderew Yedinak Joseph
Bhalla Anup
Allen Ewbster Jeffrey
Leonard Cumbo Joseph
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Application granted granted Critical
Publication of TW333707B publication Critical patent/TW333707B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW086111623A 1996-09-05 1997-08-13 The method of forming power semiconductor device with controllable integrated buffer TW333707B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/708,712 US5872028A (en) 1996-09-05 1996-09-05 Method of forming power semiconductor devices with controllable integrated buffer

Publications (1)

Publication Number Publication Date
TW333707B true TW333707B (en) 1998-06-11

Family

ID=24846896

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086111623A TW333707B (en) 1996-09-05 1997-08-13 The method of forming power semiconductor device with controllable integrated buffer

Country Status (7)

Country Link
US (1) US5872028A (zh)
EP (1) EP0828290A3 (zh)
JP (1) JPH1092841A (zh)
KR (1) KR100490801B1 (zh)
CN (1) CN1180924A (zh)
CA (1) CA2213840A1 (zh)
TW (1) TW333707B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5940689A (en) * 1997-06-30 1999-08-17 Harris Corporation Method of fabricating UMOS semiconductor devices using a self-aligned, reduced mask process
JP4904625B2 (ja) * 2001-02-14 2012-03-28 富士電機株式会社 半導体装置
JP4967209B2 (ja) * 2001-08-30 2012-07-04 富士電機株式会社 半導体装置の製造方法
US20050156322A1 (en) * 2001-08-31 2005-07-21 Smith Lee J. Thin semiconductor package including stacked dies
JP5150953B2 (ja) 2008-01-23 2013-02-27 三菱電機株式会社 半導体装置
CN101673673B (zh) * 2009-09-22 2013-02-27 上海宏力半导体制造有限公司 外延片形成方法及使用该方法形成的外延片
US9834860B2 (en) * 2009-10-14 2017-12-05 Alta Devices, Inc. Method of high growth rate deposition for group III/V materials
KR102098297B1 (ko) * 2013-05-24 2020-04-07 엘지이노텍 주식회사 에피택셜 웨이퍼
CN104992969B (zh) * 2015-07-14 2018-05-01 株洲南车时代电气股份有限公司 具有缓冲层的半导体器件及其制作方法
CN105575772A (zh) * 2015-12-25 2016-05-11 河北普兴电子科技股份有限公司 Frd用硅外延片制备方法
CN107785424A (zh) * 2016-08-31 2018-03-09 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
DE102017103782B4 (de) * 2017-02-23 2021-03-25 Infineon Technologies Ag Halbleitervorrichtung mit einer vergrabenen Schicht und Herstellungsverfahren hierfür

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696701A (en) * 1986-11-12 1987-09-29 Motorola, Inc. Epitaxial front seal for a wafer
IT1218200B (it) * 1988-03-29 1990-04-12 Sgs Thomson Microelectronics Procedimento di fabbricazione di un dispositivo semiconduttore mos di poterza a modulazione di conducibilita' (himos) e dispositivi con esso ottenuti
JPH0691263B2 (ja) * 1988-10-19 1994-11-14 株式会社東芝 半導体装置の製造方法
US5237183A (en) * 1989-12-14 1993-08-17 Motorola, Inc. High reverse voltage IGT
JP2555942B2 (ja) * 1993-08-27 1996-11-20 日本電気株式会社 光制御デバイス
EP0683529B1 (en) * 1994-05-19 2003-04-02 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Power integrated circuit ("PIC") structure with a vertical IGBT, and manufacturing process thereof

Also Published As

Publication number Publication date
JPH1092841A (ja) 1998-04-10
KR100490801B1 (ko) 2005-08-29
EP0828290A3 (en) 1999-01-13
EP0828290A2 (en) 1998-03-11
CA2213840A1 (en) 1998-03-05
CN1180924A (zh) 1998-05-06
KR19980024376A (ko) 1998-07-06
US5872028A (en) 1999-02-16

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