TW306045B - The producing method for self-aligned contact hole by spin-coating - Google Patents

The producing method for self-aligned contact hole by spin-coating Download PDF

Info

Publication number
TW306045B
TW306045B TW85114838A TW85114838A TW306045B TW 306045 B TW306045 B TW 306045B TW 85114838 A TW85114838 A TW 85114838A TW 85114838 A TW85114838 A TW 85114838A TW 306045 B TW306045 B TW 306045B
Authority
TW
Taiwan
Prior art keywords
layer
dielectric
contact hole
metal layer
self
Prior art date
Application number
TW85114838A
Other languages
Chinese (zh)
Inventor
Lih-Wei Yan
Miin-Horng Wang
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Priority to TW85114838A priority Critical patent/TW306045B/en
Application granted granted Critical
Publication of TW306045B publication Critical patent/TW306045B/en

Links

Abstract

A producing method for self-aligned layers contact hole by using spin coating. The pattern of stack layer structure on substrate is producing by CVD and etching method. The stack layer structure includes a 1st metal layer on bottom and a 1st dielectric layer on top; Its features are: Coat 2nd dielectric solution on stack layer structure by using spin coatingto form a smooth 2nd dielectric layer and cover with photoresist. Define layers contact hole pattern by using photomask. Proceed etching on 1st and2nd dielectric with related layers contact hole by selectively etching to. Finally, deposit 2nd metal layer by using CVD to produce self-aligned layerscontact hole with photomask error-allowed. The biased part of layerscontact hole is stopped by 2nd dielectric layer, so its operation can keepin normal function.

Description

A7 B7 306045 五、發明説明(1 ) 本發明係有關一種自我對齊層間接觸孔之製作方法, 尤其是上、下金屬層之間的接觸孔製作方法,在金屬層與 介電質層之堆疊結構周邊,以旋轉塗佈法塗佈一阻隔物, 利用阻隔物與介電質層對蝕刻液具不同之選擇性,以製作 自我對齊的層間接觸孔。 現今金屬層間接觸孔之製作,係利用光罩定出層間接 觸孔圖案,再以蚀刻法製作出該圖案,利用加大該區金屬 層之面積,以降低光罩對準誤差對於層間接觸孔所造成的 影響。 參閲圖一’習用金屬層間接觸孔之側视圖。其中包含 有一基層10、第一金屬層n、介電質層12、第二金屬層]3 。圖(a)中層間接觸孔15爲一所需之正確的層間接觸孔, 而圖(b)中層間接觸孔ι6與圖(c )中層間接觸孔丨了爲因光罩 對準誤差所造成的層間接觸孔,其中該層間接觸孔16僅部 份與第一金屬層]1接觸,増加接觸電阻値,降低其性能, 而層間接觸孔〗7則完全不與第一金屬層〗]接觸,故爲一失 效的層間接觸孔。 參閲圖二’習用金屬層間接觸孔之俯视圖。其中第一 金屬層11爲了降低光軍對準誤差對於層間接觸孔所造成的 影響’而將層間接觸孔周圍的第一金屬層n面積,作局部 擴大,形成第一金屬層擴大區14。因該區佔去較大面積, 使得佈局密度無法大幅提高,對於日益講求高体局密 積體電路元件而言,是很大的缺點。 本紙張尺度賴巾關家榡準(CNS ) A4規格(2^297公楚) (請先閱讀背面之注意事項再填寫本頁) 裝. -a 經濟部中央標準局員工消費合作社印製 306045 A7 -----B7 五、發明説明(2) 本發明之主要目的在提供一種自我對齊之層間接觸孔 製作方法’不僅不需加大該區金屬層的面積,同時克服光 軍對準誤差的影響。 圏式之簡單説明: 圖一爲習用金屬層間接觸孔之側視圖。 圖二爲習用金屬層間接觸孔之俯視圖。 圖三爲本發明之製程步驟。 (請先閲讀背面之注意事項再填寫本莨) 經濟部中央標準局員工消費合作社印製 圖式中之參照數號 10基層 11第一金屬層 12介電質層 13第二金屬層 14第一金屬層擴大區 15層間接觸孔 16層間接觸孔 17層間接觸孔 20基層 21第一金屬層 22第一介電質層 23第二金屬層 25層間接觸孔 26層間接觸孔 28層間接觸孔 29第二介電質層 31光阻 茲配合圖式將本發明最佳實施例詳細説明如下。 參閲圖三’本發明之製程步驟。圖(a)中之基層2〇上 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公楚:) A7 A7 經濟部中央標隼局員工消費合作社印製 五、發明説明(3 ) 〜---- 万,以CVD法沉積一第一金屬層a與第一介電質層u ,隨 後利用光阻與蝕刻法,製作出所需的疊層結 勺 底部的第一金屬層2]與其上的第一介電質層以。u 接著利用旋轉塗佈法,將一介電質溶液均句地塗佈在 該疊層結構上,如圖(b)所示,此方法之詳細操作内容, 請參考第八四-〇八七三二號專利。因而得到一平坦性、 覆蓋力佳且與該疊層結構黏貼性強之第二介電質層29。在 第二介電質層29上塗佈-級31,利_刻法定出層間接 觸孔圖案,再用蝕刻法,蝕去未受光阻31保護的第二介電 質區與第—介電質區,利用第一介電質區與第二介^質區 對蚀刻程度的差異,使得相對應的第一介電 較大於第二介電㈣,如圖⑻中斜職域所示。1速度 當第一介電質層22被蝕去而露出第一金屬層21時,第 二介電質層29的相對應部分高於第一金屬層2】。最後,將 第二金屬層23以CVD法沉積上去,如圖(c)所示。 對於光罩對準誤差的影響,如圖(c)中層間接觸孔烈 與28所tf。以一正確的層間接觸孔况爲基 於第-介電質觀内與第一金屬層接觸。層== 與』因光軍對準誤差,偏離了第-介電質層22的中心區 域’而分別向右、向左偏移’使得部分接觸孔接觸到第一 金屬層’部分接觸孔被第二介電質層29阻擒到。因此, 即使層間接觸孔25與28,因光革對準誤差而偏離,其第二 金屬層23未落在第一金屬層2]的部分,仍被第二介電 29阻絕,而不影響該元件之操作。由於本發明容忍光軍^ (請先閱讀背面之注意事項再填寫本頁) .装. 訂 本紙張尺度適财CNS ) A4規格(21Q x297^^~y---------- 306045 Μ Β7 五、發明説明(4 ) ~~~ 準誤差,雖然接觸孔有偏移,但能製作出自哉對齊之層間 接觸孔,因此,不需加大該區之第一金屬層21面積,提高 元件之佈局密度,同時提高該成品之良率。 ^ 综上所述,當知本案發明具有實用性與創作性,且本 發明未見之於任何刊物,當符合專利法規定。 唯以上所述者,僅爲本發明之一較佳實施例而已,當 不能以之限定本發明實施之範圍。即大凡依本發明申請專 利範圍所作之均等變化與修飾,皆應屬本發明專利涵蓋之 範圍内。 --------------¾衣------'玎------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度相中賴家榡CNS ) M規格(2丨Q><297公缝A7 B7 306045 V. Description of the invention (1) The present invention relates to a method for manufacturing self-aligned interlayer contact holes, especially a method for manufacturing contact holes between upper and lower metal layers, in a stacked structure of metal layers and dielectric layers Around the periphery, a barrier is coated by spin coating, and the barrier and the dielectric layer have different selectivities to the etching solution to make self-aligned interlayer contact holes. Nowadays, the production of metal interlayer contact holes is to use the photomask to define the interlayer contact hole pattern, and then to make the pattern by etching, and to increase the area of the metal layer in this area to reduce the photomask alignment error. The impact. See Figure 1 'for a side view of a conventional metal interlayer contact hole. It includes a base layer 10, a first metal layer n, a dielectric layer 12, and a second metal layer] 3. The inter-layer contact hole 15 in FIG. (A) is a required correct inter-layer contact hole, and the inter-layer contact hole ι6 in FIG. (B) and the inter-layer contact hole in FIG. (C) are caused by mask alignment errors. Interlayer contact hole, wherein the interlayer contact hole 16 is only partially in contact with the first metal layer] 1, increasing the contact resistance value, reducing its performance, and the interlayer contact hole is not in contact with the first metal layer at all. Therefore, it is a failed interlayer contact hole. Refer to Figure 2 'for a top view of a conventional metal interlayer contact hole. The first metal layer 11 partially enlarges the area of the first metal layer n around the interlayer contact hole to reduce the effect of the alignment error of the optical army on the interlayer contact hole, thereby forming the first metal layer expansion region 14. Because this area occupies a large area, the layout density cannot be greatly improved, which is a big disadvantage for increasingly demanding high-density circuit components. The size of this paper is Laijinguan Jiajun (CNS) A4 (2 ^ 297) (please read the precautions on the back before filling out this page). -A Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative 306045 A7 ----- B7 V. Description of the invention (2) The main purpose of the present invention is to provide a method for making self-aligned interlayer contact holes' not only does not need to increase the area of the metal layer in this area, but also overcomes the alignment error of the optical army influences. Brief description of the ring type: Figure 1 is a side view of a conventional metal layer contact hole. Figure 2 is a top view of a conventional metal interlayer contact hole. Figure 3 shows the process steps of the present invention. (Please read the precautions on the back first and then fill out this book) The reference number in the printed pattern of the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 10 base layer 11 first metal layer 12 dielectric layer 13 second metal layer 14 Metal layer expansion area 15 Interlayer contact hole 16 Interlayer contact hole 17 Interlayer contact hole 20 Base layer 21 First metal layer 22 First dielectric layer 23 Second metal layer 25 Interlayer contact hole 26 Interlayer contact hole 28 Interlayer contact hole 29 Second The photoresist of the dielectric layer 31 and the pattern of the preferred embodiment of the present invention are described in detail as follows. Refer to Figure 3 'the process steps of the present invention. The paper on the base layer 20 in Figure (a) applies the Chinese National Standard (CNS) Α4 specifications (210X 297 Gongchu :) A7 A7 Printed by the Employee Consumer Cooperative of the Central Standard Falconry Bureau of the Ministry of Economy V. Description of the invention (3) ~ ---- Wan, deposit a first metal layer a and a first dielectric layer u by CVD method, and then use photoresist and etching method to make the first metal layer at the bottom of the required lamination spoon 2] With the first dielectric layer on it. u Then use spin coating to uniformly apply a dielectric solution on the laminated structure, as shown in (b). For the detailed operation content of this method, please refer to Article 84-0087 No. 32 patent. Thus, a second dielectric layer 29 with good flatness, good coverage and strong adhesion to the laminated structure is obtained. Coat the second dielectric layer 29 with a level 31, and then etch out the interlayer contact hole pattern, and then use the etching method to etch away the second dielectric region and the first dielectric that are not protected by the photoresist 31 Area, using the difference in the degree of etching between the first dielectric area and the second dielectric area, so that the corresponding first dielectric is larger than the second dielectric, as shown in the oblique field in FIG. 1 speed When the first dielectric layer 22 is etched away to expose the first metal layer 21, the corresponding portion of the second dielectric layer 29 is higher than the first metal layer 2]. Finally, the second metal layer 23 is deposited by CVD, as shown in (c). For the effect of mask alignment error, as shown in Figure (c), the interlayer contact hole and the tf are 28. Based on a correct interlayer contact hole condition, it contacts the first metal layer in the first-dielectric view. Layer == and 『Due to the alignment error of the optical army, it deviates from the center area of the first dielectric layer 22 ′ and shifts to the right and left respectively ′, so that part of the contact hole contacts the first metal layer’ part of the contact hole is The second dielectric layer 29 is blocked. Therefore, even if the interlayer contact holes 25 and 28 deviate due to the alignment error of the optical leather, the portion of the second metal layer 23 that does not fall on the first metal layer 2] is still blocked by the second dielectric 29 without affecting the Operation of components. Because the present invention tolerates the light army ^ (please read the precautions on the back before filling in this page). Packed. The size of the paper is suitable for CNS) A4 specification (21Q x297 ^^ ~ y ---------- 306045 Μ Β7 V. Description of the invention (4) ~~~ The quasi-error, although the contact holes are offset, but can produce interlayer contact holes from the alignment, so there is no need to increase the area of the first metal layer 21 in this area, Increase the layout density of components and increase the yield of the finished product. ^ In summary, when the invention of this case is known to be practical and creative, and the invention is not seen in any publication, it should meet the provisions of the Patent Law. Only the above The above is only one of the preferred embodiments of the present invention, which should not be used to limit the scope of the implementation of the present invention. That is, all equal changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the patent of the present invention Inside. -------------- ¾ Clothing ------ '玎 ------ ^ (Please read the notes on the back before filling this page) Central Standard of the Ministry of Economic Affairs Bureau consumer consumption cooperative printed this paper in the standard of Lai Jiadu CNS) M specifications (2 丨 Q < 297 male sewing

Claims (1)

-種旋轉塗佈製作自我對齊層間接觸孔之方法,利用 CVD法與蚀刻法’在基體上製作出—疊層結構之圖案, 該眷層結構包含-底部的第—金屬層與其上的第一介電 質層,其特徵在於:利用旋轉塗佈法,將第二介電質溶 液塗佈在該φ層結構上,形成—平坦且_性佳的第二 介電質層’並覆蓋-層練’以光罩定出層間接觸孔圖 案,接著使用對第一介電質層與二介電質層,具有選擇 性蝕刻能力的蝕刻方法,對該層間接觸孔相對應之第一 介電質層與第二介電質層進行蝕刻,最後以CVD法沉積 一層第二金屬層,製作出容許光軍對準誤差的自我對齊 層間接觸孔,該層間接觸孔之偏離部分,被第二介電質 層阻擋到,使得其操作仍保持正常功能。 (請先閱讀背面之注意事項再填寫本頁) 丁 經濟部中央標準局員工消費合作社印策 7 本紙張尺度逋用中國國家揉準(CNS ) A4规格(21〇X 297公釐)-A method of producing self-aligned interlayer contact holes by spin coating, using CVD method and etching method to produce a pattern of a laminated structure on the substrate, the layer structure includes-the first metal layer on the bottom and the first on it The dielectric layer is characterized in that the second dielectric solution is coated on the φ layer structure by a spin coating method to form a flat and excellent second dielectric layer and cover the layer Practise 'Use the photomask to define the interlayer contact hole pattern, and then use the etching method with selective etching ability for the first dielectric layer and the two dielectric layers, and the first dielectric corresponding to the interlayer contact hole The layer and the second dielectric layer are etched, and finally a second metal layer is deposited by CVD method to make a self-aligned inter-layer contact hole that allows optical alignment errors. The deviated part of the inter-layer contact hole is used by the second dielectric The mass layer is blocked, so that its operation remains normal. (Please read the precautions on the back before filling out this page) D. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 7 This paper is based on China National Standard (CNS) A4 (21〇X 297mm)
TW85114838A 1996-12-02 1996-12-02 The producing method for self-aligned contact hole by spin-coating TW306045B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW85114838A TW306045B (en) 1996-12-02 1996-12-02 The producing method for self-aligned contact hole by spin-coating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW85114838A TW306045B (en) 1996-12-02 1996-12-02 The producing method for self-aligned contact hole by spin-coating

Publications (1)

Publication Number Publication Date
TW306045B true TW306045B (en) 1997-05-21

Family

ID=51566050

Family Applications (1)

Application Number Title Priority Date Filing Date
TW85114838A TW306045B (en) 1996-12-02 1996-12-02 The producing method for self-aligned contact hole by spin-coating

Country Status (1)

Country Link
TW (1) TW306045B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447518A (en) * 2020-11-25 2021-03-05 绍兴同芯成集成电路有限公司 Contact hole forming process of IGBT wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447518A (en) * 2020-11-25 2021-03-05 绍兴同芯成集成电路有限公司 Contact hole forming process of IGBT wafer

Similar Documents

Publication Publication Date Title
TW454240B (en) Improved contact and deep trench patterning
KR20040015050A (en) Design of lithography alignment and overlay measurement marks on cmp finished damascene surface
US11621128B2 (en) Capacitor unit
TW306045B (en) The producing method for self-aligned contact hole by spin-coating
TW573323B (en) Method for improving visibility of alignment targets in semiconductor processing
KR100368569B1 (en) Semiconductor device and its manufacturing method
TWI669997B (en) Circuit board structure and manufacturing method thereof
JP2006302992A (en) Semiconductor device and method of manufacturing the same
JPH05226475A (en) Manufacture of semiconductor device
WO2023279545A1 (en) Method for manufacturing semiconductor structure, and semiconductor structure
TWI220055B (en) Structure of preventing mis-alignment in lithography process and method thereof
GB2184606A (en) Method of producing metallic thin film coil
JPH0689895A (en) Flattening method
JP2621579B2 (en) Ceramic substrate
JPS5935165B2 (en) Manufacturing method of multilayer thin film coil
JPH0496254A (en) Thin film multi-layered circuit board an manufacture thereof
JPH01241117A (en) Alignment-mark
KR100564563B1 (en) Semiconductor device having multi-layered overlay key structure
JPH03263855A (en) Multilayer wiring structure
JP2001110893A (en) Semiconductor integrated circuit device and its manufacturing method
JP2023519885A (en) Semiconductor structure and manufacturing method thereof
TW320763B (en) Manufacturing method of inter-metal dielectric and intra-metal dielectric
JPS6235537A (en) Semiconductor device and manufacture thereof
JPS5955038A (en) Formation of multilayer wiring
JPH01194334A (en) Manufacture of semiconductor integrated circuit

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees
MK4A Expiration of patent term of an invention patent