CN112447518A - Contact hole forming process of IGBT wafer - Google Patents
Contact hole forming process of IGBT wafer Download PDFInfo
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- CN112447518A CN112447518A CN202011336884.XA CN202011336884A CN112447518A CN 112447518 A CN112447518 A CN 112447518A CN 202011336884 A CN202011336884 A CN 202011336884A CN 112447518 A CN112447518 A CN 112447518A
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- Prior art keywords
- contact hole
- igbt
- trench gate
- deep trench
- forming process
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims abstract description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 9
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract description 3
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- 239000002184 metal Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention discloses a contact hole forming process of an IGBT wafer, which comprises the following steps: s1, depositing Si on the front surface of the IGBT wafer with the deep trench gate by LPCVD3N4Layer, followed by anisotropic dry etching of Si3N4Si for forming deep trench gate sidewall3N4A gasket; s2, depositing an ILD layer on the front surface of the wafer; s3, dry etching the ILD layer to form a gentle slope contact hole which gradually narrows from top to bottom; and S4, completely filling the thick film Al in the contact hole by sputtering to form the Emittor structure of the IGBT. The invention utilizes Si3N4The sidewall spacer forms perfect insulation protection at the edge of the deep trench gate structure, and can be automatically aligned to form a gentle slope contact hole during contact hole etching, so that the distance between the contact hole and the deep trench gate can be minimized, and simultaneously, the contact hole and the deep trench gate are matchedControlling the sputtering temperature of the Al thick film to form a perfect Emittor structure filled with the Al thick film.
Description
Technical Field
The invention relates to the field of IGBT wafer packaging, in particular to a contact hole forming process of an IGBT wafer.
Background
An Insulated Gate Bipolar Transistor (IGBT) has the advantages of both high input impedance of a MOSFET device and high-speed switching characteristics of a power Transistor (i.e., a Giant Transistor (GTR), and is widely used in the fields of ac motors, frequency converters, switching power supplies, lighting circuits, traction drives, and the like.
The trench gate IGBT chip technology effectively eliminates the JFET effect in a planar gate channel by converting the channel from the transverse direction to the longitudinal direction, so that the channel density is not limited by the surface area of the chip any more, the cell density is improved, the current density of the chip is greatly improved, and the planar gate technology is gradually replaced in the field of medium and low voltage application. In order to further improve the power density of the trench gate IGBT chip, IGBT chip manufacturers push out a fine trench design, and through an advanced photolithography technique and a process, the trench width is reduced, and the trench pitch is reduced, so that the MOS channel density is increased, and the chip current density is improved. However, as the degree of refinement of the trench gate IGBT chip is higher and higher, the size of the metal contact hole is smaller and smaller, so that the difficulty of the metal contact window forming process and the metal hole filling process is higher and higher.
At present, when etching a contact window, the contact hole is too close to the edge of a trench gate to cause the problem of electric leakage, and the contact hole is far away from the edge of the trench gate to cause the low utilization rate of the surface area of a wafer; meanwhile, when the via hole is smaller than 0.2um, voids are easily formed in the via hole during the Al thick film filling (as shown in fig. 5), and the stability of the element electron migration is affected in the operating state where the current is large.
Disclosure of Invention
In order to solve the above mentioned disadvantages in the background art, the present invention provides a contact hole forming process for an IGBT wafer, which uses Si3N4The (silicon nitride) side wall gasket forms perfect insulation protection at the edge of the deep groove gate structure, a gentle slope contact hole can be formed by automatic alignment during contact hole etching, the distance between the contact hole and the deep groove gate can be reduced to the minimum, and a perfect Emittor structure filled with the Al thick film is formed by matching with Al thick film sputtering temperature control.
The purpose of the invention can be realized by the following technical scheme:
a contact hole forming process of an IGBT wafer comprises the following steps:
s1, depositing Si on the front surface of the IGBT wafer with the deep trench gate by LPCVD3N4Layer, followed by anisotropic dry etching of Si3N4Si for forming deep trench gate sidewall3N4A gasket;
s2, depositing an ILD layer on the front surface of the wafer;
s3, dry etching the ILD layer to form a gentle slope contact hole which gradually narrows from top to bottom;
and S4, completely filling the thick film Al in the contact hole by sputtering to form the Emittor structure of the IGBT.
Further preferably, the deposition method of the ILD layer in step S2 is one of LPCVD, APCVD and PECVD.
Further preferably, the bottom ILD layer is an undoped dielectric and the top ILD layer is a P-doped dielectric.
Further preferably, the side wall of the gentle slope-like contact hole is inclined at an angle of 75 to 85 °.
Further preferably, the temperature at which the thick film Al is sputtered in step S4 is 400 ℃.
The invention has the beneficial effects that:
1. the invention utilizes Si3N4The (silicon nitride) sidewall spacer forms perfect insulation protection at the edge of the deep trench gate structure, and can be automatically aligned during contact hole etching, i.e., the distance between the contact hole and the deep trench gate can be minimized and the problem of electric leakage caused by too close contact with the edge of the deep trench gate during the etching of the gentle slope contact hole can be avoided, because of the existence of Si3N4The sidewall spacer and the ILD layer protect the substrate from breakdown even under high current/voltage circuit operation conditions.
2. The present invention forms a gentle slope contact hole and a deep trench gate sidewall Si3N4When the thick film Al filling can be performed after the protection structure of (2) due to the effect of high temperature>At 400 ℃) to naturally form the filling of the contact hole, and can form a perfect Emittor structure filled with the Al plug hole if the structure is perfectWithout sufficient ILD and sidewall Si3N4The structure is easy to generate the problem of electric leakage or breakdown of the insulating layer on the side wall. Wherein the key for forming the gradual slope contact hole is Si3N4The combination of side wall and ILD (undercut + undercut) can make the upper opening of the contact hole wider and the ILD slightly narrower due to the difference of etching rate selectivity and side etching characteristics, while Si3N4The side wall has little etching loss, so that a gentle slope shape can be formed from top to bottom.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic view of the process of step S1 according to the present invention;
FIG. 2 is a schematic view of the process of step S2 according to the present invention;
FIG. 3 is a schematic view of the process of step S3 according to the present invention;
FIG. 4 is a schematic view of the process of step S4 according to the present invention;
FIG. 5 is a schematic diagram of a prior art contact hole Al thick film fill process.
In the figure:
1-wafer, 2-deep trench, 3-Si3N44-undoped ILD layer, 5-P doped ILD layer, 6-contact via, 7-thick Al film, 8-void.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
Example 1
A contact hole forming process of an IGBT wafer comprises the following steps:
s1, depositing Si on the front surface of the IGBT wafer with the deep trench gate by LPCVD3N4Layer, followed by anisotropic dry etching of Si3N4Si for forming deep trench gate sidewall3N4A gasket;
s2, depositing an ILD layer on the front surface of the wafer by one of LPCVD, APCVD and PECVD, wherein the bottom layer of the ILD layer is an undoped dielectric medium, and the upper layer of the ILD layer is a dielectric medium doped with P;
s3, dry etching the ILD layer to form a gentle slope contact hole with a gradually narrowing inclination angle of 75 degrees from top to bottom;
s4, sputtering thick film Al, wherein the temperature is 600 ℃ when the thick film Al is sputtered, and the Al is completely filled in the contact hole to form the Emittor structure of the IGBT.
Example 1
A contact hole forming process of an IGBT wafer comprises the following steps:
s1, depositing Si on the front surface of the IGBT wafer with the deep trench gate by LPCVD3N4Layer, followed by anisotropic dry etching of Si3N4Si for forming deep trench gate sidewall3N4A gasket;
s2, depositing an ILD layer on the front surface of the wafer by one of LPCVD, APCVD and PECVD, wherein the bottom layer of the ILD layer is an undoped dielectric medium, and the upper layer of the ILD layer is a dielectric medium doped with P;
s3, dry etching the ILD layer to form a gentle slope contact hole with a gradually narrowing inclination angle of 85 degrees from top to bottom;
s4, sputtering thick film Al, wherein the temperature is 500 ℃ when the thick film Al is sputtered, and the Al is completely filled in the contact hole to form the Emittor structure of the IGBT.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (5)
1. A contact hole forming process of an IGBT wafer is characterized by comprising the following steps:
s1, depositing Si on the front surface of the IGBT wafer with the deep trench gate by LPCVD3N4Layer, followed by anisotropic dry etching of Si3N4Si for forming deep trench gate sidewall3N4A gasket;
s2, depositing an ILD layer on the front surface of the wafer;
s3, dry etching the ILD layer to form a gentle slope contact hole which gradually narrows from top to bottom;
and S4, completely filling the thick film Al in the contact hole by sputtering to form the Emittor structure of the IGBT.
2. The contact hole forming process for the IGBT wafer according to claim 1, wherein the deposition method of the ILD layer in the step S2 is one of LPCVD, APCVD and PECVD.
3. The contact hole forming process for the IGBT wafer according to claim 1, wherein the ILD layer bottom layer is an undoped dielectric, and the ILD layer upper layer is a P-doped dielectric.
4. The forming process of the contact hole of the IGBT wafer as claimed in claim 1, wherein the inclination angle of the side wall of the gently sloping contact hole is 75-85 °.
5. The contact hole forming process for the IGBT wafer according to claim 1, wherein the temperature for sputtering thick-film Al in step S4 is above 400 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011336884.XA CN112447518A (en) | 2020-11-25 | 2020-11-25 | Contact hole forming process of IGBT wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011336884.XA CN112447518A (en) | 2020-11-25 | 2020-11-25 | Contact hole forming process of IGBT wafer |
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| Publication Number | Publication Date |
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| CN112447518A true CN112447518A (en) | 2021-03-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011336884.XA Pending CN112447518A (en) | 2020-11-25 | 2020-11-25 | Contact hole forming process of IGBT wafer |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW306045B (en) * | 1996-12-02 | 1997-05-21 | Macronix Int Co Ltd | The producing method for self-aligned contact hole by spin-coating |
| EP1387404A2 (en) * | 2002-07-31 | 2004-02-04 | Fujitsu Limited | Semiconductor device and method for fabricating the same |
| CN1617312A (en) * | 2003-11-10 | 2005-05-18 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN102088035A (en) * | 2010-09-21 | 2011-06-08 | 上海韦尔半导体股份有限公司 | Trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and manufacturing method thereof |
| US20190057873A1 (en) * | 2016-03-30 | 2019-02-21 | Mitsubishi Electric Corporation | Semiconductor device, method of manufacturing same, and power converter |
-
2020
- 2020-11-25 CN CN202011336884.XA patent/CN112447518A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW306045B (en) * | 1996-12-02 | 1997-05-21 | Macronix Int Co Ltd | The producing method for self-aligned contact hole by spin-coating |
| EP1387404A2 (en) * | 2002-07-31 | 2004-02-04 | Fujitsu Limited | Semiconductor device and method for fabricating the same |
| CN1617312A (en) * | 2003-11-10 | 2005-05-18 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN102088035A (en) * | 2010-09-21 | 2011-06-08 | 上海韦尔半导体股份有限公司 | Trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and manufacturing method thereof |
| US20190057873A1 (en) * | 2016-03-30 | 2019-02-21 | Mitsubishi Electric Corporation | Semiconductor device, method of manufacturing same, and power converter |
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Application publication date: 20210305 |