CN116741816A - Silicon carbide device with integrated structure and preparation method thereof - Google Patents
Silicon carbide device with integrated structure and preparation method thereof Download PDFInfo
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- CN116741816A CN116741816A CN202310722366.9A CN202310722366A CN116741816A CN 116741816 A CN116741816 A CN 116741816A CN 202310722366 A CN202310722366 A CN 202310722366A CN 116741816 A CN116741816 A CN 116741816A
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 43
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000006185 dispersion Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 238000003892 spreading Methods 0.000 claims description 12
- 230000007480 spreading Effects 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 5
- 230000002441 reversible effect Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
Abstract
The invention relates to a silicon carbide device with an integrated structure and a preparation method thereof, comprising the following steps: comprising the following steps: an N-doped substrate; an N doped drift region is arranged above the N doped substrate; drain electrode metal is arranged below the N doped substrate; an N-epitaxial layer is arranged above the N-doped drift region; a current dispersion layer is arranged above the N-epitaxial layer; the upper left side and the upper right side of the current dispersion layer are provided with P+ doped regions; the inner sides of the P+ doped regions at two sides are provided with an N+ doped region and a P-doped region from top to bottom; the current dispersion layer is provided with a first oxide layer above, and the first oxide layer is of a ladder structure and comprises a first oxide layer first area and a first oxide layer second area. The invention adopts the L-shaped first oxide layer with the ladder structure, improves the gate oxide reliability of the device during the reverse operation, improves the breakdown voltage of the device, and the integrated diode can have quicker recovery time when the device works at the third quadrant.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon carbide device with an integrated structure and a preparation method thereof.
Background
Compared with Si MOSFETs with the same power level, the silicon carbide MOSFETs have the advantages that on-resistance and switching loss of the SiC MOSFETs are greatly reduced, the silicon carbide MOSFETs are suitable for higher working frequency, and in addition, the high-temperature stability is greatly improved due to the high-temperature working characteristic.
However, in the silicon carbide MOS in the prior art, the area of the gate oxide is larger, and the dielectric medium is usually silicon oxide, however, due to factors such as high-density dislocation, extremely poor polarity, grain boundary and the like in the silicon carbide crystal structure, the reliability of the gate oxide is lower, the gate oxide is easily influenced by factors such as voltage gradient and the like, higher stress cannot be born, the reliability of a device is reduced, and the electrical performance of the device is seriously influenced; meanwhile, the silicon carbide crystal structure can influence the over-high starting voltage of the silicon carbide MOSFET, when the starting voltage of the silicon carbide MOSFET is over-high, the device can be completely started only by providing higher grid voltage, the static power consumption of the device can be increased, meanwhile, the efficiency of the device can be reduced, the electric breakdown phenomenon can be caused in the device, the device is damaged or fails, the reliability of the device is reduced, and the device can be completely started or closed only by the over-high starting voltage, so that the switching speed of the device is influenced. There is a need for a silicon carbide device having an integrated structure and a method of fabricating the same to address the above-described problems.
Disclosure of Invention
First, the technical problem to be solved
In view of the above-mentioned drawbacks and shortcomings of the prior art, the present invention provides a silicon carbide device with an integrated structure and a method for manufacturing the same, which solves the technical problems that the gate oxide reliability is low and the switching speed of the device is affected due to the high density dislocation, the extremely poor polarity, the grain boundary and other factors in the silicon carbide crystal structure of the existing silicon carbide MOSFET.
(II) technical scheme
In order to achieve the above purpose, the main technical scheme adopted by the invention comprises the following steps:
a first aspect of an embodiment of the present invention provides a silicon carbide device having an integrated structure, including: an N-doped substrate; an N doped drift region is arranged above the N doped substrate; drain electrode metal is arranged below the N doped substrate; an N-epitaxial layer is arranged above the N-doped drift region; a current dispersion layer is arranged above the N-epitaxial layer; the upper left side and the upper right side of the current dispersion layer are provided with P+ doped regions; the inner sides of the P+ doped regions at two sides are provided with an N+ doped region and a P-doped region from top to bottom; the current dispersion layer is provided with a first oxidation layer above, and the first oxidation layer is of a stepped L-shaped structure and comprises a first oxidation layer first region and a first oxidation layer second region.
Optionally, a second polysilicon is arranged right above the current dispersion layer; the second polysilicon divides the first oxide layer into two L-shaped structures which are bilaterally symmetrical; a second oxide layer is arranged above the second polysilicon; source electrode metal and first polysilicon are arranged on two sides of the second oxide layer from top to bottom.
Optionally, the thickness of the first region of the first oxide layer is 40nm-50nm, and the thickness of the second region of the first oxide layer is 90nm-100nm.
Optionally, the lower surfaces of the first oxide layer second regions of the first oxide layer on the left and right sides are respectively contacted with the p+ doped region and the n+ doped region on the left and right sides.
Optionally, at least a portion of the first oxide layer first region of the first oxide layer on the left and right sides is located directly above the current spreading layer and is in contact with the current spreading layer.
A second aspect of an embodiment of the present invention provides a method for manufacturing a silicon carbide device having an integrated structure, including:
forming an epitaxial wafer with an N-epitaxial layer of N-ions on an N-doped substrate with N+ ions;
etching part of the N-epitaxial layer by an etching process on the basis of the epitaxial wafer, and filling N-ions with higher doping concentration to form a current dispersion layer;
performing ion implantation by using the mask plate to form a P+ doped region, a P-doped region and an N+ doped region;
generating a first oxide layer on the epitaxial wafer;
depositing on the first oxide layer to form first polysilicon as a grid electrode of the device;
depositing in the first oxide layer to form a second polysilicon, connecting the second polysilicon with the source electrode of the device, contacting with the surface of the wafer to form a heterojunction,
depositing a second oxide layer to form a protective passivation layer;
etching the passivation layer until the second polysilicon window is exposed, and depositing metal to form source metal of the device;
carrying out metal deposition on the back of the device to form drain electrode metal of the device;
after a first oxide layer is generated on the epitaxial wafer, etching the first oxide layer to form a first area of the first oxide layer, wherein the thickness of the first area is 40-50 nm;
depositing outside the first region of the first oxide layer to form a second region of the first oxide layer with the thickness of 90-100 nm, and forming a stepped L-shaped structure with the first region of the first oxide layer; .
Optionally, forming an epitaxial wafer with an N-epitaxial layer on an N-doped substrate with n+ ions, comprising: the dosage of the N doped substrate with N+ ions is 1e16cm -3 -1e19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The dosage of the epitaxial wafer with the N-epitaxial layer of N-ions is 1e13cm -3 -1e16cm -3 。
Optionally, an N-doped drift region is present between the N-doped substrate and the N-epitaxial layer.
Optionally, on the basis of the epitaxial wafer, etching part of the N-epitaxial layer by an etching process, filling N-ions with higher doping concentration, and forming a current dispersion layer, including: the dosage of the N-ion with higher doping concentration is 5e12cm -3 -5e15 cm -3 。
(III) beneficial effects
The beneficial effects of the invention are as follows: according to the silicon carbide device with the integrated structure and the preparation method thereof, on one hand, the L-shaped first oxide layer with the ladder structure is adopted, and through the combination of the first area of the first oxide layer and the second area of the first oxide layer in the structure, the gate oxide layer below a channel is ensured to provide smaller starting voltage, the gate oxide reliability of the MOS tube is improved through the thickness of the first oxide layer structure, meanwhile, the gate oxide reliability of the device in reverse operation is also improved, the breakdown voltage of the device is improved, so that the integrated diode device can have quicker recovery time and smaller recovery current in the third quadrant (reverse operation) operation, and the device can operate at higher frequency; on the other hand, the heterojunction diode is integrated in the general MOS tube structure, and compared with the traditional application, the heterojunction diode has more volume advantages.
Drawings
FIG. 1 is a schematic plan view of a silicon carbide device having an integrated structure in accordance with the present invention;
FIG. 2 is a schematic flow chart of a method for fabricating a silicon carbide device with an integrated structure according to the present invention;
FIG. 3 is a first state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention through step S201;
FIG. 4 is a second state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention through step S202;
FIG. 5 is a third state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention, after step S203;
FIG. 6 is a fourth state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention, after step S204;
FIG. 7 is a fifth state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention, after step S205;
FIG. 8 is a sixth state diagram illustrating a method of fabricating a silicon carbide device having an integrated structure according to the present invention, via step S206;
FIG. 9 is a seventh state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention, after step S207;
FIG. 10 is an eighth state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention, after step S208;
FIG. 11 is a ninth state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention through step S209;
FIG. 12 is a tenth state diagram of the method for fabricating a silicon carbide device with integrated structure according to the present invention through step S210;
fig. 13 is an eleventh state diagram of the method for manufacturing a silicon carbide device with an integrated structure according to the present invention through step S211.
Description of the drawings: 101: an N-doped substrate; 102: an N-epitaxial layer; 103: a current dispersion layer; 104: a P+ doped region; 105: a P-doped region; 106: an N+ doped region; 107: a first oxide layer; 108: a first polysilicon; 109: a second polysilicon; 110: a second oxide layer; 111: a source metal; 112: a drain metal; 113: an N doped drift region; 1071: a first oxide layer first region; 1072: the first oxide layer second region.
Detailed Description
The invention will be better explained by the following detailed description of the embodiments with reference to the drawings. Wherein references herein to "upper", "lower", "etc. are made with reference to the orientation of fig. 1.
In order that the above-described aspects may be better understood, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Referring to fig. 1, a silicon carbide device having an integrated structure, comprising: an N-doped substrate 101; an N doped drift region 113 is arranged above the N doped substrate 101; a drain metal 112 is arranged below the N-doped substrate 101; an N-epitaxial layer 102 is arranged above the N-doped drift region 113; a current dispersion layer 103 is arranged above the N-epitaxial layer 102; the upper left and upper right of the current dispersion layer 103 are provided with P+ doped regions 104; the inner sides of the P+ doped regions 104 on the two sides are provided with an N+ doped region 106 and a P-doped region 105 from top to bottom; p-doped region 105 and p+ doped region 104 enclose n+ doped region 106; a first oxide layer 107 is disposed above the current spreading layer 103, where the first oxide layer 107 has a step structure and includes a first oxide layer first region 1071 and a first oxide layer second region 1072.
In this embodiment, the thickness of the first oxide layer first region 1071 of the first oxide layer 107 is 40nm to 50nm, and the thickness of the first oxide layer second region 1072 of the first oxide layer 107 is 90nm to 100nm.
In this embodiment, the first oxide layer 107 is provided with a second polysilicon 109 inside; the lower surface of the second polysilicon 109 contacts with the current dispersion layer 103, and the second polysilicon 109 is additionally arranged to contact with the current dispersion layer 103, so that one diode structure is additionally integrated in the MOS tube structure. The second polysilicon 109 divides the first oxide layer 107 into two L-shaped structures which are symmetrical left and right; a second oxide layer 110 is disposed over the second polysilicon 109; the source metal 111 and the first polysilicon 108 are disposed on two sides of the second oxide layer 110 from top to bottom.
In this embodiment, the lower surface of the first oxide second region 1072 of the left first oxide layer 107 contacts the p+ doped region 104 and the n+ doped region 106 on the left side, respectively, and the lower surface of the first oxide second region 1072 of the right first oxide layer 107 contacts the p+ doped region 104 and the n+ doped region 106 on the right side, respectively. At least a portion of the first oxide layer first region 1071 of the left first oxide layer 107 is located directly above the current spreading layer 103 and is in contact with the current spreading layer 103; at least a portion of the first oxide layer first region 1071 of the right first oxide layer 107 is located directly above the current spreading layer 103 and is in contact with the current spreading layer 103.
Referring to fig. 2 to 13, a method of manufacturing a silicon carbide device having an integrated structure, includes:
s201 forming an epitaxial wafer having an N-epitaxial layer 102 on an N-doped substrate 101 having n+ ions;
in this embodiment, the N-doped substrate has N+ ionsThe dosage is 1e16cm -3 -1e19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The dose of the epitaxial wafer having the N-epitaxial layer 102 of N-ions was 1e13cm -3 -1e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the An N-doped drift region 113 is present between the N-doped substrate 101 and the N-epitaxial layer 102.
S202, on the basis of an epitaxial wafer, etching part of the N-epitaxial layer by an etching process, and filling N-ions with higher doping concentration to form a current dispersion layer 103;
in the present embodiment, the dosage of N-ion with higher doping concentration is 5e12cm -3 -5e15 cm -3 。
S203, performing ion implantation by using a mask plate to form a P+ doped region 104, a P-doped region 105 and an N+ doped region 106;
s204, generating a first oxide layer 107 on the epitaxial wafer;
s205, etching the first oxide layer 107 to form a first oxide layer first region 1071 of the first oxide layer 107, wherein the thickness is 40nm-50nm;
s206, depositing outside the first region of the first oxide layer to form a second region 1072 of the first oxide layer 107, wherein the thickness of the second region is 90-100 nm, and the second region and the first region of the first oxide layer form a stepped L-shaped structure;
in this embodiment, the first oxide layer second region 1072 of the stepped L-shaped gate oxide layer is formed by deposition. With the stepped L-shaped gate oxide layer structure formed in S205 and S206, the leftmost side of the first oxide layer second region 1072 of the left first oxide layer 107 is spaced apart from the n+ doped region 106 by a certain distance (as long as there is a distance), and the rightmost side of the first oxide layer first region 1071 of the left first oxide layer 107 is spaced apart from the leftmost side of the current spreading layer 103 by a certain distance, as is the other side of symmetry. The gate oxide reliability of the device in the reverse working process is improved through the stepped L-shaped gate oxide layer structure, and the breakdown voltage of the device is improved.
S207, depositing on the first oxide layer 107 to form first polysilicon 108 serving as a grid electrode of the device;
s208, depositing in the first oxide layer 107 to form second polysilicon 109, wherein the second polysilicon 109 is connected with the source electrode of the device through the other direction and contacts with the surface of the wafer to form a heterojunction;
in this embodiment, by forming the heterojunction, the heterojunction has a volume advantage compared with the conventional application; the integrated diode will have a faster recovery time and a smaller recovery current when the device is operating in the third quadrant (reverse operation), thereby allowing the device to operate at a higher frequency.
S209, depositing a second oxide layer 110 to form a protective passivation layer;
s210, etching the passivation layer until the second polysilicon 109 window is exposed, and depositing metal to form source metal 111 of the device;
s211, performing metal deposition on the back surface of the device to form drain metal 112 of the device.
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium; may be a communication between two elements or an interaction between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature is "on" or "under" a second feature, which may be in direct contact with the first and second features, or in indirect contact with the first and second features via an intervening medium. Moreover, a first feature "above," "over" and "over" a second feature may be a first feature directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is level lower than the second feature.
In the description of the present specification, the terms "one embodiment," "some embodiments," "examples," "particular examples," or "some examples," etc., refer to particular features, structures, materials, or characteristics described in connection with the embodiment or example as being included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that alterations, modifications, substitutions and variations may be made in the above embodiments by those skilled in the art within the scope of the invention.
Claims (9)
1. A silicon carbide device having an integrated structure, comprising: an N-doped substrate (101); an N doped drift region (113) is arranged above the N doped substrate (101); a drain metal (112) is arranged below the N-doped substrate (101); an N-epitaxial layer (102) is arranged above the N-doped drift region (113); a current dispersion layer (103) is arranged above the N-epitaxial layer (102); the upper left and upper right of the current dispersion layer (103) are provided with P+ doped regions (104); the inner sides of the P+ doped regions (104) at two sides are provided with N+ doped regions (106) and P-doped regions (105) from top to bottom; the current dispersion layer (103) is provided with a first oxide layer (107) above, and is characterized in that the first oxide layer (107) has a step structure and comprises a first oxide layer first region (1071) and a first oxide layer second region (1072).
2. A silicon carbide device with integrated structure according to claim 1, characterized in that the current spreading layer (103) is provided with a second polysilicon (109) directly above; the second polysilicon (109) divides the first oxide layer (107) into two L-shaped structures which are symmetrical left and right; a second oxide layer (110) is arranged above the second polysilicon (109); source metal (111) and first polysilicon (108) are arranged on two sides of the second oxide layer (110) from top to bottom.
3. A silicon carbide device with integrated structure according to claim 1, characterized in that the first oxide layer first region (1071) of the first oxide layer (107) has a thickness of 40nm-50nm and the first oxide layer second region (1072) of the first oxide layer (107) has a thickness of 90nm-100nm.
4. A silicon carbide device according to claim 1, wherein the lower surfaces of the first oxide layer second regions (1072) of the first oxide layer (107) on the left and right sides are respectively in contact with the p+ doped regions (104) and the n+ doped regions (106) on the left and right sides.
5. A silicon carbide device according to claim 1, wherein at least a portion of the first oxide layer first region (1071) of the first oxide layer (107) on the left and right sides is located directly above the current spreading layer (103) and is in contact with the current spreading layer (103).
6. A method of fabricating a silicon carbide device having an integrated structure, comprising:
forming an epitaxial wafer with an N-epitaxial layer of N-ions on an N-doped substrate with N+ ions;
etching part of the N-epitaxial layer by an etching process on the basis of the epitaxial wafer, and filling N-ions with higher doping concentration to form a current dispersion layer;
performing ion implantation by using the mask plate to form a P+ doped region, a P-doped region and an N+ doped region;
generating a first oxide layer on the epitaxial wafer;
depositing on the first oxide layer to form first polysilicon as a grid electrode of the device;
depositing in the first oxide layer to form a second polysilicon, connecting the second polysilicon with the source electrode of the device, contacting with the surface of the wafer to form a heterojunction,
depositing a second oxide layer to form a protective passivation layer;
etching the passivation layer until the second polysilicon window is exposed, and depositing metal to form source metal of the device;
carrying out metal deposition on the back of the device to form drain electrode metal of the device;
the method is characterized in that after a first oxide layer is generated on an epitaxial wafer, the first oxide layer is etched to form a first region of the first oxide layer, wherein the thickness of the first region is 40-50 nm;
and depositing outside the first region of the first oxide layer to form a second region of the first oxide layer with the thickness of 90-100 nm, and forming a stepped L-shaped structure with the first region of the first oxide layer.
7. The method of fabricating a silicon carbide device with integrated structure according to claim 6, wherein forming an epitaxial wafer with an N-epitaxial layer on an N-doped substrate with n+ ions comprises: the dosage of the N doped substrate with N+ ions is 1e16cm -3 -1e19cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The dosage of the epitaxial wafer with the N-epitaxial layer of N-ions is 1e13cm -3 -1e16cm -3 。
8. The method of manufacturing a silicon carbide device having an integrated structure according to claim 6 wherein an N doped drift region is present between the N doped substrate and the N-epitaxial layer.
9. The method of manufacturing a silicon carbide device having an integrated structure according to claim 6, wherein forming a current spreading layer by etching a portion of the N-epi layer on the basis of the epi-wafer and filling N-ions having a higher doping concentration by an etching process, comprises: the dosage of the N-ion with higher doping concentration is 5e12cm -3 -5e15cm -3 。
Priority Applications (1)
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