TW301780B - - Google Patents
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- Publication number
- TW301780B TW301780B TW084110353A TW84110353A TW301780B TW 301780 B TW301780 B TW 301780B TW 084110353 A TW084110353 A TW 084110353A TW 84110353 A TW84110353 A TW 84110353A TW 301780 B TW301780 B TW 301780B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate structure
- region
- conductive
- layer
- source
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
- H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/298,018 US6200871B1 (en) | 1994-08-30 | 1994-08-30 | High performance self-aligned silicide process for sub-half-micron semiconductor technologies |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW301780B true TW301780B (enExample) | 1997-04-01 |
Family
ID=23148649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW084110353A TW301780B (enExample) | 1994-08-30 | 1995-10-04 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6200871B1 (enExample) |
| EP (1) | EP0700081A3 (enExample) |
| JP (1) | JPH08111527A (enExample) |
| KR (1) | KR100372675B1 (enExample) |
| TW (1) | TW301780B (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4027447B2 (ja) * | 1996-04-24 | 2007-12-26 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| US6175147B1 (en) * | 1998-05-14 | 2001-01-16 | Micron Technology Inc. | Device isolation for semiconductor devices |
| KR100294637B1 (ko) * | 1998-06-29 | 2001-10-19 | 박종섭 | 모스펫의폴리사이드게이트형성방법 |
| KR100335525B1 (ko) * | 1998-06-30 | 2002-05-08 | 마찌다 가쯔히꼬 | 반도체장치 및 그의 제조방법 |
| US6391767B1 (en) * | 2000-02-11 | 2002-05-21 | Advanced Micro Devices, Inc. | Dual silicide process to reduce gate resistance |
| JP3485103B2 (ja) * | 2001-04-19 | 2004-01-13 | セイコーエプソン株式会社 | Mos型トランジスタ及びその製造方法 |
| US6743666B1 (en) * | 2001-04-27 | 2004-06-01 | Advanced Micro Devices, Inc. | Selective thickening of the source-drain and gate areas of field effect transistors |
| US6403485B1 (en) * | 2001-05-02 | 2002-06-11 | Chartered Semiconductor Manufacturing Ltd | Method to form a low parasitic capacitance pseudo-SOI CMOS device |
| US6894328B2 (en) * | 2002-08-13 | 2005-05-17 | Newport Fab, Llc | Self-aligned bipolar transistor having recessed spacers and method for fabricating same |
| US7183187B2 (en) * | 2004-05-20 | 2007-02-27 | Texas Instruments Incorporated | Integration scheme for using silicided dual work function metal gates |
| KR100602122B1 (ko) * | 2004-12-03 | 2006-07-19 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조방법 |
| CN101548387B (zh) * | 2007-08-07 | 2012-03-21 | 松下电器产业株式会社 | 碳化硅半导体元件及其制造方法 |
| CN106409842A (zh) * | 2016-11-08 | 2017-02-15 | 深圳市华星光电技术有限公司 | 顶栅薄膜晶体管的制作方法及顶栅薄膜晶体管 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2578100B1 (fr) * | 1985-02-26 | 1987-04-10 | Efcis | Circuit integre a transistors mos a electrodes en siliciure metallique et procede de fabrication |
| US4920071A (en) * | 1985-03-15 | 1990-04-24 | Fairchild Camera And Instrument Corporation | High temperature interconnect system for an integrated circuit |
| US4933295A (en) * | 1987-05-08 | 1990-06-12 | Raytheon Company | Method of forming a bipolar transistor having closely spaced device regions |
| NL8800222A (nl) * | 1988-01-29 | 1989-08-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op zelfregistrerende wijze metaalsilicide wordt aangebracht. |
| US4877755A (en) * | 1988-05-31 | 1989-10-31 | Texas Instruments Incorporated | Method of forming silicides having different thicknesses |
| KR930004295B1 (ko) * | 1988-12-24 | 1993-05-22 | 삼성전자 주식회사 | Vlsi 장치의 n+ 및 p+ 저항영역에 저저항 접속방법 |
| US5084417A (en) * | 1989-01-06 | 1992-01-28 | International Business Machines Corporation | Method for selective deposition of refractory metals on silicon substrates and device formed thereby |
| JPH0758773B2 (ja) * | 1989-07-14 | 1995-06-21 | 三菱電機株式会社 | 半導体装置の製造方法及び半導体装置 |
| US5130266A (en) * | 1990-08-28 | 1992-07-14 | United Microelectronics Corporation | Polycide gate MOSFET process for integrated circuits |
| US5352631A (en) * | 1992-12-16 | 1994-10-04 | Motorola, Inc. | Method for forming a transistor having silicided regions |
-
1994
- 1994-08-30 US US08/298,018 patent/US6200871B1/en not_active Expired - Lifetime
-
1995
- 1995-08-29 KR KR1019950027109A patent/KR100372675B1/ko not_active Expired - Fee Related
- 1995-08-29 EP EP95113564A patent/EP0700081A3/en not_active Withdrawn
- 1995-08-30 JP JP7222263A patent/JPH08111527A/ja active Pending
- 1995-10-04 TW TW084110353A patent/TW301780B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960009022A (ko) | 1996-03-22 |
| EP0700081A2 (en) | 1996-03-06 |
| US6200871B1 (en) | 2001-03-13 |
| KR100372675B1 (ko) | 2003-05-09 |
| EP0700081A3 (en) | 1997-07-02 |
| JPH08111527A (ja) | 1996-04-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |