TW293166B - The bonding method of lead frame and die - Google Patents

The bonding method of lead frame and die Download PDF

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Publication number
TW293166B
TW293166B TW85104284A TW85104284A TW293166B TW 293166 B TW293166 B TW 293166B TW 85104284 A TW85104284 A TW 85104284A TW 85104284 A TW85104284 A TW 85104284A TW 293166 B TW293166 B TW 293166B
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Taiwan
Prior art keywords
lead frame
chip
wafer
double
lead
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TW85104284A
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Chinese (zh)
Inventor
Jonq-Juh Wey
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Fujiter Technical Co Ltd
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Publication of TW293166B publication Critical patent/TW293166B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Die Bonding (AREA)

Abstract

The bonding method of lead frame and die includes: (1) Manufacturing the lead frame: Punch the Cu, Al or alloy sheet into several lead frames; (2) Bonding lead frame and die: Heat two sides tape in 320-340 deg.C about 0.5 sec, then bond it on a pre-heated lead frame. Bond die on the other side of tape with temp. 320-380 deg.C for 0.5 sec; (3) Wire bonding: Bond the inner lead of lead frame with bond pad of die; (4) Molding: Put the lead frame inside molding die then pour with black resin; (5) Trim: Trim into single independent IC.

Description

經濟部中央標準局—工消费合作社印装 發明説明( 1 ΐϊΞί指其提供—種藉由熱膠著雙轉料< i e if 於導縣上,以達職速結合、降低製程成 本及傳輪速度增快之目的。 降成 +由於人類電子科技的日新月異,習式必須由許 电子電路結合才能完成之工作已漸漸由積體電路 grated circuit,簡稱! c )所取代,j 〇其最顯著 在於㈣體積比用分_元件做成的轉體構造小 品體積縮小許多,合乎人類使用的原則; 冗成時為-切割為若干晶片(die)之晶圓,必須將晶片 貼5於導線架上並經务干製.程始成為一般設計者所使用之 1C,現茲配合其製作流程圖(請參閲第—圖)將其加工 之程序詳述如下: 1 .導線架之製造(Lead Frame):請參閲第二圖,其係 在一片體上以機械沖壓方式開設若干可與晶片結合之 導線架1 1 (該片體之材質可為銅(Cu)、鋁(A1) 或合金(Alloy )),且於導線架1 1中間設一承載 晶片之基座1 2,而導線架1 1周緣二侧則向内延伸 若干接腳1 3,並在其上鍍銀,以便與晶片内之電路 連結。 2 ·導線架與晶片之結合(Die B〇nciing):請參閲第三 圖,當導線架製作完成欲與晶片結合時,則必須先在 導線架1 1基座1 2上點上銀膠,使晶片2 〇藉由銀 膠黏合於導線架1 1上,完成導線架與晶片之結合。 本纸張尺度適用中囷囷家榡準(CMS ) A4说格(210x297公釐> 83, 3.10,000 (碕先閲讀背面之注意事項再填寫本頁) •訂' 曰曰 以 的 、發明説明(>) .烘烤(Cure):由於銀膠為點 片結合後之導線架送入洪烤壚内妙烤,此必須將與 使銀膠乾燥硬化,達到晶片與導線架緊密】= 2: ^ timrm 中姆應之電路連結,使晶片可3内端與晶片 腳1 3將訊號傳入晶片電路内^理了於外之I C接 ^膠成型⑽ding):料線架 麦二必須置人模型内以黑色樹脂灌注,片^〜二 顯露於外,且將黑色樹脂加溫至3 固體,黑色樹脂即成型為—般常見之i C外型。為 •切割(Tnm):完成上述之步驟後, ㈣成各個1 C個體,以符合各電路之不同設計需要 然而,以上之Ic製程卻存在下列之缺失: ,於銀膠係為特殊之化合接著劑,因此其講置成本較 鬲,連帶整個加工成本亦提高。 在導線架與晶片結合後,必須將其送入供烤爐内花費 4 - 8個小時烘烤,不但拖長其整個製程所需之時間 ,,同時增加烘烤所必須之成本。 由於銀膠為黏稠狀之接著劑,因此在導線架點上銀膠 之過程中,容易有氣泡附著在銀膠上,使得導線架與 晶片之接合面中亦有氣泡存在,該氣泡内之空氣則成 -------^II (請先閲讀背面之注意事項再填寫本頁) 訂- 經濟部中央標準局負工消費合作社印製 本纸财g S家樣準(CNS ) A4iUM 210X297公羞) 83. 3.10.000 經 部 中 央 標 準 % Μ 工 消 費 合 作 社 印 t 五 、發明說明(令) Α7 Β7 為導線架與晶片間之導體,使晶 .並產生1C特性不良等缺點。彳内4路文干擾, 4 im内端與晶片内之電路焊接長度達18 〇 ^孕义大,涊I c足傳輸速度亦因而較慢。 研私,此’本發明人遂以其多年執此業之工作經驗,終究 —種導線架與晶片之快速結合方法,並係利用娜 膠生之黏著性使晶==品質,此即為本發“ 過程快速五提高產品 熱膠著雙面膠衫娜合—晶片,而導 鍍銀處則與晶片上對應之電路焊合, 端 =尸體;藉_解著雙面膠帶可 ,輯到降= (請先閲讀背面之注意事項再填穹表良)The Central Bureau of Standards of the Ministry of Economic Affairs-Industry and Consumer Cooperatives printed and invented invention instructions (1 refers to its provision)-a kind of double transfer material by hot glue < ie if on Daoxian County, to achieve the combination of professional speed, reduce process cost and transmission speed The purpose of increasing speed is reduced to + due to the rapid development of human electronic technology, the work that must be completed by the combination of electronic circuits has gradually been replaced by integrated circuit (abbreviated! C)), j 〇The most significant lies in (iv) The volume is smaller than the size of the rotating structure made of parts_components, which is in line with the principle of human use; when it is redundant-the wafer is cut into several die (die), the chip must be pasted on the lead frame 5 and passed Business Dry Process. The process became the 1C used by general designers. Now, in conjunction with its production flow chart (please refer to the first figure), its processing procedures are detailed as follows: 1. Lead frame manufacturing (Lead Frame): Please refer to the second picture, which is to open a number of lead frames 1 1 that can be combined with the wafer by mechanical stamping on a body (the material of the body can be copper (Cu), aluminum (A1) or alloy (Alloy)) ), And on the lead frame 1 1 A susceptor disposed between the carrier wafer 12, the lead frame 11 and the periphery of two sides of the plurality of inwardly extending pins 13, and on which silver, so connected to the circuitry within the chip. 2 · Combination of lead frame and chip (Die B〇nciing): Please refer to the third figure. When the lead frame is completed and you want to combine with the chip, you must first apply silver glue on the lead frame 1 1 base 1 2 Then, the chip 20 is adhered to the lead frame 11 by silver glue to complete the combination of the lead frame and the chip. The size of this paper is applicable to CMS A4 (210x297mm> 83, 3.10,000 (read the precautions on the back before filling out this page) Description (>). Baking (Cure): Since the silver glue is the lead frame after the combination of the dots, it is sent to the Hong roasting Miao roasting. This must be dried and hardened to make the silver glue tight to the wafer and the lead frame] = 2: ^ Timing circuit connection in timrm, so that the chip can be connected to the inner end of the chip and the chip pin 1 3. The signal is transferred into the chip circuit ^ The IC connection is handled externally ^ Glue molding ⑽ding): the wire frame must be placed The human model is infused with black resin, the film ^ ~ 2 is exposed, and the black resin is heated to 3 solids, and the black resin is molded into a common i C shape. For • Cutting (Tnm): After completing the above steps, (1) into individual 1 C units to meet the different design needs of each circuit. However, the above Ic process has the following deficiencies:, special bonding in silver glue system Agent, so its cost of installation is lower, and the overall processing cost is also increased. After the lead frame and the wafer are combined, it must be sent into the baking oven for 4-8 hours to bake, which not only prolongs the time required for the entire process, but also increases the cost of baking. Since the silver glue is a viscous adhesive, it is easy to have bubbles adhere to the silver glue during the process of applying the silver glue on the lead frame, so that there are also bubbles in the bonding surface of the lead frame and the wafer, and the air in the bubbles Zecheng ------- ^ II (please read the precautions on the back before filling in this page) Order-Printed paper money by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs g S Home Sample Standard (CNS) A4iUM 210X297 Public shame) 83. 3.10.000 Central Standard of the Ministry of Economic Affairs printed by the Min-consumer Cooperative Society V. Description of the Invention (Order) Α7 Β7 is a conductor between the lead frame and the wafer, which causes defects such as poor 1C characteristics. There are 4 inter-text interferences in the internal circuit, the length of the soldering of the circuit between the internal end of the 4 im and the chip reaches 18 ^^, which makes the transmission speed of the Ic foot slower. Research, this inventor's years of work experience in this industry, after all-a rapid combination of lead frame and chip method, and the use of Najiaosheng's adhesion makes crystal == quality, which is based on "Fast process" to improve the product's thermal bonding with double-sided adhesive shirts and wafers, and the silver-plated parts are soldered to the corresponding circuits on the wafers, end = corpse; borrow _ to solve double-sided tape, edit to drop = (Please read the precautions on the back before filling the dome form)

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-------------K 線一------- 本發明之另—目_在於提供—種導線架與晶片 之結 本纸乐纽it财關 83- 3. 10,000 五 、發明説明(屮) A7 B7 經濟部中央標準局負工消費合作社印製 第二圖 第三圖 第四圖 第五圖 第六圖 第七圓 弟八圖 第九圖 第十圖, 合t法其中,導線架與晶片結合時,係將晶片從上而下 擺=於導線架貼合熱膠著雙面膠帶處,避免晶片由下拉上 ,、占a時,印片掉落於機台上造成破損,以降低導架與晶 片結合過程中之耗損率。 人本發明之再一目的係在於提供一種導線架與晶对之結 曰方^ ’、中,熱膠著雙面膠帶係貼合於導線架上與ί c 晶片焊合處2面,以提高烊合處之敎性。 ’ 為使貴審查委員對本發明能有更進一步認識诳暸解 ,下列兹舉-錄實關,並配合圖錢明如后/ 罘—圖,係為習式之製法流程圖。 ,係為習式I C·導線架之放大平面圖。 ,係為習式導線架與晶片之結合示意圖。 ’係為習式焊線之示意圖。 ,係為本發明之製法流程圖。 ,係為本發明1c導線架之放大平面圖。 係為本發明導線架貼上熱膠著雙面膠帶之系 意圖。 係為本發明晶片與導線架結合之示意圖。 係為習式與本發明之導線架與晶片結合所需 花費步驟與時間比較表。 第十/Τίΐ與本發明之坪線長度比較示意圖。 圖,發明結合面氣泡密度與結合溫度之 貫驗曲線圖。 “閱弟五及^圖’其係為本發明之製法流程圖, t iiSiJcNS ) ---------^-I 装-- 务 f I n n n - - - - n n - I I n 83.3.10,000 s;------------- K 线 一 ------- Another aspect of the present invention-the purpose is to provide-a kind of lead frame and wafer knot paper paper Newton it financial customs 83- 3 . 10,000 V. Description of Invention (呮) A7 B7 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs of the Negative Labor Consumer Cooperative. The second picture, the third picture, the fourth picture, the fifth picture, the sixth picture, the seventh circle, the eighth picture, the ninth picture, the tenth picture In the t method, when the lead frame and the wafer are combined, the wafer is swung from top to bottom = the lead frame is attached to the double-sided adhesive tape with hot glue, to avoid the wafer from being pulled down, and when the a is occupied, the print falls on the machine. It will cause damage to reduce the wear rate in the process of bonding the guide frame to the wafer. A further object of the present invention is to provide a combination of a lead frame and a crystal pair. In the middle, the hot-adhesive double-sided adhesive tape is attached to the lead frame and the two sides of the welding place of the wafer to improve the closing rate. The goodness of fit. In order for your reviewing committee to have a better understanding of the present invention, the following are the following-record the actual relationship, together with the figure Qian Mingruhou / she-figure, is a flow chart of the manufacturing method of the conventional style. , Is an enlarged plan view of Xi-style IC lead frame. , Is a schematic diagram of the combination of conventional lead frame and chip. 'Is a schematic diagram of a conventional bonding wire. Is a flow chart of the manufacturing method of the present invention. Is an enlarged plan view of the 1c lead frame of the present invention. It is the intention that the lead frame of the present invention is pasted with double-sided adhesive tape. It is a schematic diagram of the combination of the chip and the lead frame of the present invention. This is a comparison table of the steps and time required for combining the conventional lead frame with the chip of the present invention. Tenth / ΤΙ and the present invention is a schematic comparison of the length of the flat line. Figure, the penetration curve of the bubble density and bonding temperature of the bonding surface of the invention. "Yuediwu and ^ Picture" is the flow chart of the manufacturing method of the present invention, t iiSiJcNS) --------- ^-I installation-service f I nnn----nn-II n 83.3. 10,000 s;

、發明説明(j) 、结合之導線Stί體~^^設若干可與晶片3 腳…各IC接腳“另端職接 =二側42、43及導線架上、下段= 導線架4。置於38『C高溫中= 2 導線架4 〇表面之水氣、氣化物筌故所、·、’、原去除 1C接腳4 1另端鍍銀處4 2、〇 =各貼上適當長度之熱膠著雙面膠帶= ^鱗轉導帶5 〇在貼合於導转4 q之前亦 必心、置於3 2 0 — 3 4 (TC高溫中〇 . 5秒加 才貼合至導線架4 0上,熱膠著雙面膠帶5 〇另面^以’ 3 2 0 — 3 8 0 °C之黏合溫度黏上—晶片3 二圖),以完成導線架40與晶片3q之結合, 片3 〇結合後之導線架4 0 1 ◦接腳另端錄銀處4 2 、4 4、4 5與晶片内之相對應電路焊接,由於 、 於導線架4川接腳41另端鍵: 另^因此在晶片3 0與導線架2 〇 j c接腳2 i另端鍍 j 42、43、44、45谭合時,细熱膠著雙面膠 π4 0做支擇=使焊合處之穩定性高,不易折斷且焊線 長度縮短,而灌>王黑色樹脂成型及切割等步驟因愈習式 法相同,故此不再贅述。請參閱第九圖,習式導線架 片在結合時所需花費的步驟順序為在導線架上點上銀膠、 貼合晶片以及送入烘烤爐内乾燥硬化,使晶片固定於^線 本纸伕尺度適用中國國家榇準(CNS ) Α4说格(210X297公釐 裝— (請為閲姊背面之注意事項再填寫本頁) -訂· it--------- 83. 3· 1〇,〇〇〇 ‘發明説明(4 ) 寺·^外,必須加上點銀膠、 曰 間,因此習式導線架與晶片之社人時 曰曰片之寺 小β每,a 士⑴从、诗 开〜口啤間必項多於4 — 8個 】、時,而本創料綠架與日日日片在結合時所 序為導線架、熱膠著雙面膠帶熱還原及貼合與晶片貼合二 =序步驟,即可使晶片固定於導線架上,花費的時^ f貼合至導線架之時間〇.5秒,其導線‘晶^ = :|:取二?、6!,較習式之4—8個小時減少許多, 相對的,同-雜時間内的產量亦可㈣式提高畔多 ,產業大量生產之目的。請㈣針w,由於習式導線架 上〈IC接腳另端與晶片上相對應電路係為兩側連接焊人 ,距離較長,因此焊線之長度L1必須達1 8 〇mil,而本口 f明之晶片則因以熱膠著雙面膠帶直接貼合在!c接腳另 端上,因此在IC接腳另端與晶片上相對應之電路連接時 距離較短,其所需之焊線長度L2即較短,約為在i 〇 〇mii 以下,相對的,傳輸速度亦因焊線長度縮短、阻抗減少的 緣故而增加,使Ic的反應速度加快;請參閲第十一圖, 其係為導線架與晶片藉由熱膠著雙面膠帶結合時,結合面 於各種溫度產生氣泡密度之曲線,由曲線上即可明顯看出 ,在溫度3 2 0,一 3 8 0 Ό時,產生的氣泡之密度均少於 5 /6,尤其在3 4 0 °C時,其氣泡密度趨近於零,相對地 ,氣泡内的空氣成為導體的機會亦減少,避免晶片内的電 路受到干擾產生誤動作,以提高IC之產品品質,另由於 本纸張尺度逋用中國國家梂率(CNS > A4说格(210X297公釐) (請先閔讀背面之注意事項再填寫本X) •裝. 訂 經濟部中央梯準局員工消費合作社印製 83.3. 10,000 五 、發明説明(7) 輪之訊號係由ί C之接腳傳 合面,抗必須愈大,離絕導綠二^ ί ΓίΓό=作结合面所能產生之阻技為每: a面之續丄ί絕緣常數為3 . 1,顯示本創作择 緣賴佳,《接提高了 I C:之產。。 據此,本發明所能達成之效益如下· 、 卜由於習核晶片貼合於導線架上時所朗之接 Ί,而本創作為熱膠著雙面膠帶,熱膠著雙面膠 = 《成本約比銀膠之驢成本節省3 G %,因此= 降低整個製程之成本。 大巾田 2 ·較習式導縣與糾之結合製賴少了烘烤過程 此在製程所需之時間上亦減少4 — 8個小時,同 烤時所需之成本亦可減少,相同單位時間内之目、 相對提高。 3 . 1於導線架與晶片係利用熱膠著雙面膠帶結合,而熱 膠著雙面膠帶係在3 4 (TC高溫、為還原狀態時,才 可貼合導線架與晶片,因此在接合面產生的氣泡減少 ,以避免氣泡成為導線架與晶片之導體,亦即減少工c 特性不良的情形產生。 4由於導線架與晶片在結合之過程中係採導線架置於下 万、晶片從上往下貼合之方式結合,因此當晶片不愼 掉落時’晶片仍只會掉落於導線架上,不致掉落在機 台上造成破損情形,以降低損耗率。 5.由於結合在導線架上之晶片必須以大於1公斤之拉力 ( CNS ) A4im ( 210X297^* ) f-----4. (請先閲讀背面之注意事) 經濟部中央標準局員工消f合作社印製 83. 3.10,000 A7 五、發明説明(y ) 閲 讀 背 Sj 之 注 意 事 再 拉扯,才能將晶片由導線架上拔除,代表二者之結合 強度夠大,確實達到導線架與晶片緊密結合之目的。 6 ’由於熱膠著雙面膠帶係貼合於導線架上IC接腳另端 處^另面,因此當IC接腳另端與晶片中相對應之電 路T合時’藉由熱膠著雙面膠帶形成IC接腳另端之 =’@免1(:接_於綱產生折損的現 $於本發明之導線架架構使其與晶片之焊線長度由習 8 Omil縮短至i 〇 〇mil以下,因此焊線中的 阻柷亦因而變小,加快傳輸之速度。 訂 故允符;明==破==品品質, 經濟部中央樣準局貞工消費合作社印犁, Description of the invention (j), the combined wire St ~~ ^^ set a number of pins with the chip 3 ... Each IC pin "the other end is connected = two sides 42, 43 and the upper and lower sections of the lead frame = lead frame 4. At 38 "C high temperature = 2 Lead frame 4 〇 Surface moisture, vaporization cause, ...,", the original removal 1C pin 4 1 the other end of the silver plating place 4 2, 〇 = each paste the appropriate length Hot glued double-sided tape = ^ scale transfer tape 5 〇Before attaching to the guide transfer 4 q, it must also be placed in 3 2 0-3 4 (TC high temperature 0.5 seconds plus before attaching to the lead frame 4 0, hot glued double-sided tape 5 〇 the other side ^ adhered to the '3 2 0-3 8 0 ° C bonding temperature-wafer 3 two pictures) to complete the combination of lead frame 40 and wafer 3q, piece 3 〇 The combined lead frame 4 0 1 ◦The other end of the pin is at the silver recording point 4 2, 4 4, 4 5 and the corresponding circuit in the chip is soldered, because, at the lead frame 4 Sichuan pin 41 another end key: another ^ so When the chip 30 and the lead frame 2 ojc pin 2 i are plated with j 42, 43, 44, 45 at the other end, fine hot glue is applied with double-sided tape π 4 0 to make the selection = the stability of the welded joint is high and it is not easy to break And the length of the welding wire is shortened, while pouring > king black The steps of forming and cutting the grease are the same as the conventional method, so they will not be repeated here. Please refer to the ninth figure. The sequence of steps required for the conventional lead frame pieces to be combined is to apply silver glue on the lead frame and attach them. The wafers are put into the baking oven to dry and harden, so that the wafers are fixed in the ^ line paper. The paper size is suitable for China National Standard (CNS) Α4 said grid (210X297 mm)-(please fill out this for the precautions on the back of the reading sister) Page)-Order · it --------- 83. 3 · 1〇, 〇〇〇 'Invention Description (4) Temple · ^ outside, you must add some silver glue, day, so the traditional wire The society of the shelf and the chip is that the temple of the film is small β each, a person ⑴ from the poem, the poem must be more than 4-8 items in the beer room, the original green frame and the daily film are in The order of bonding is lead frame, thermal reduction with double-sided adhesive tape, bonding and wafer bonding = sequence step, the chip can be fixed on the lead frame, the time it takes to attach to the lead frame. .5 seconds, its wire 'crystal ^ =: |: take two ?, 6 !, which is much less than the 4-8 hours of the traditional formula. Relatively, the output in the same-mixed time can also be ㈣ type To improve the production capacity, the purpose of mass production in the industry. Please pin ∣ pin w, because the corresponding circuit on the other side of the conventional lead frame and the corresponding circuit on the chip are connected to the solder on both sides, the distance is longer, so the length of the solder wire L1 must be 18 mils, and the chip with the f port is directly attached to the other end of the c pin due to the hot glue with double-sided tape, so when the other end of the IC pin is connected to the corresponding circuit on the chip The shorter the distance, the shorter the required wire length L2 is, which is less than i 〇〇mii. Relatively, the transmission speed is also increased due to the shortened wire length and reduced impedance, which speeds up the reaction speed of Ic ; Please refer to the eleventh figure, which is the curve of the bubble density generated by the bonding surface at various temperatures when the lead frame and the chip are bonded by hot-adhesive double-sided tape. It can be clearly seen from the curve that the temperature 3 2 At 0, a 3 8 0 Ό, the density of the generated bubbles is less than 5/6, especially at 3 4 0 ° C, the bubble density tends to zero, relatively, the air in the bubble has the chance to become a conductor Reduce to avoid malfunction caused by interference of the circuits in the chip, to Improving the quality of IC products is also due to the use of the Chinese paper frame rate (CNS & A4) (210X297mm) (please read the precautions on the back and then fill in this X) • Install. Order the Ministry of Economic Affairs Printed by the Central Escalation Bureau Staff Consumer Cooperative 83.3. 10,000 V. Description of the invention (7) The signal of the round is transmitted by the pin of ί C, the resistance must be greater, and the guide will be isolated ^ ί ΓίΓό = as the joint The resistance technology that can be produced is: the insulation constant of the continuous surface of a is 3.1, which shows that this creative choice is based on Lai Jia, "The IC has improved its production. . According to this, the benefits achieved by the present invention are as follows · 、 Because the Si core chip is attached to the lead frame, the original is made of hot-adhesive double-sided tape, hot-adhesive double-sided tape = "cost about Save 3 G% than the cost of silver donkey, so = reduce the cost of the entire process. Dajintian 2 · Compared with the combination of Xizhi County and Jiaojiu, the baking process is less, and the time required for the process is also reduced by 4-8 hours. The cost of the same baking can also be reduced, the same unit The purpose of the time is relatively improved. 3.1 The lead frame and the wafer are combined with hot-adhesive double-sided tape, and the hot-adhesive double-sided tape is only at 3 4 (TC high temperature, in a reduced state before the lead frame and the wafer can be bonded, so it is generated on the bonding surface The bubbles are reduced to avoid the bubbles becoming the conductors of the lead frame and the wafer, which reduces the occurrence of poor performance characteristics. 4 Because the lead frame and the wafer are combined during the bonding process, the lead frame is placed under the 10,000, the wafer is from the top It is combined by the next bonding method, so when the chip is not dropped, the chip will only fall on the lead frame, and will not fall on the machine to cause damage, so as to reduce the loss rate. 5. Because it is bonded to the lead frame The chip on the board must be printed with a pull force of more than 1 kg (CNS) A4im (210X297 ^ *) f ----- 4. (Please read the notes on the back side first) Printed by the Staff Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 83. 3.10 .000 A7 V. Description of invention (y) Read the notes on the back of Sj and then pull to remove the chip from the lead frame, which means that the bonding strength of the two is strong enough to achieve the purpose of tightly bonding the lead frame and the chip. 6 ' Due to hot glue on both sides The tape is attached to the other end of the IC pin on the lead frame ^ the other side, so when the other end of the IC pin is combined with the corresponding circuit T in the chip, the other end of the IC pin is formed by hot-gluing the double-sided tape = '@ 免 1 (: 接 _Yu Gang has a broken wire. The lead frame structure of the present invention shortens the length of the bonding wire between it and the chip from Xi 8 Omil to less than i 〇mil, so the resistance in the bonding wire As a result, it becomes smaller and speeds up the transmission. The reason for this is to permit; Ming == Break == Quality, the Central Sample Bureau of the Ministry of Economic Affairs Zhengong Consumer Cooperatives Yinli

line

Claims (1)

經濟部中央標準局;3:工消费合作社印¾ .—種導線架與晶片之結合方法,其係包括: (1) 製造導線架:係於一銅、鋁或合金之片體上以沖壓 方式開設若干可與晶片結合之導線架; (2) 導線架與晶片結合:係將經過0 . 5秒3 2 0 — 3 4 0°C高溫還原之熱膠著雙面膠帶貼合至亦經i 5 和3 8 0 C鬲溫還原之導線架上,而熱膠著雙面膠 ,另面則以〇 . 5秒3 2 0 — 3 8 (TC高溫貼合二 晶片,使晶片與導線架舉由熱膠著雙面膠帶結合; (3) 焊線:其係將導線架上I C接腳另端鍍銀處與晶片 上相對應之電路焊合; (4) 灌膠成型:結合晶片後之導線架必須置入模型内以 黑色樹脂灌注,並將IC接腳顯露於外,黑色樹脂 並加溫至3 0 (TC以上成為固體狀; (5) 切割:由於片體上開設有若干導線架,因此必須加 以切割,以成為各個獨立之IC。 如申凊專利範圍第1項所述之導線架與晶片之結合方 法其中’導線架與晶片結合時,係將晶片從上而下 擺設於導線架貼合熱膠著雙面膠帶處。 ^申清專利範15第丨項所述之導線架與晶片之結合方 ^,其中,熱膠著雙面膠帶係貼合於導線架上與工c 晶片烊合處另面,以提高烊合處之穩定性。 =申=專利範圍第工項所述之導線架與晶片之結合方 ; 中’導線架之結構係在二側各延伸出若干j c 要腳’各IC接腳另端則集中於導線架中段開二 (請先閱讀背面之注意事邛再項、寫本頁〕 裝。 -ι»τ. 線 ABCD 六、申請專利範圍()) 側及導線架上、下段,並在其上鍍銀,以縮短與晶片 焊合時之焊線長度,增加傳輸速度。 (.請先閲讀背面之注意事項再填寫本頁) 裝1 、1T 線 經濟部中央標準局员工消t合作社印51 本纸張尺度適用中a网家柊辛(CNS)A4規格(210X 297公发)Central Bureau of Standards of the Ministry of Economic Affairs; 3: Printed by the Industrial and Consumer Cooperative Society-a method of combining lead frames and wafers, which includes: (1) Manufacturing lead frames: attached to a copper, aluminum or alloy sheet by stamping Open a number of lead frames that can be combined with the chip; (2) The lead frame and the chip are combined: the hot-glued double-sided tape that has been reduced at a high temperature of 0.5 seconds 3 2 0-3 4 0 ° C is pasted to i 5 And 3 8 0 C on the lead frame of the temperature reduction, and the hot glue is attached with double-sided tape, and the other side is bonded to the two chips in 0.5 seconds 3 2 0-3 8 (TC high temperature, so that the chip and the lead frame are lifted by heat Bonded with double-sided adhesive tape; (3) Bonding wire: it is to solder the silver plating on the other end of the IC pin on the lead frame to the corresponding circuit on the chip; (4) Pouring molding: the lead frame after bonding the chip must be Place in the model and infuse with black resin, and expose the IC pins to the outside. The black resin is heated to 30 (above TC becomes solid; (5) Cutting: Because there are a number of lead frames on the sheet, it must be Cut it to become each independent IC. The junction between the lead frame and the chip as described in item 1 of Shinshin ’s patent scope In the combination method, when the lead frame and the wafer are combined, the wafer is placed on the lead frame from the top to the bottom where the hot-glued double-sided tape is attached. ^ Shenqing Patent Range 15 Item 丨^, Where the hot-adhesive double-sided tape is attached to the lead frame and the other side of the wafer junction to improve the stability of the junction. = Application = the lead frame and the chip described in the patent scope item The combination of the middle; the structure of the lead frame extends a number of jc pins on the two sides. The other ends of the IC pins are concentrated in the middle of the lead frame. (Please read the notes on the back side first. Page] Installation. -Ι »τ. Wire ABCD 6. Patent application scope ()) The side and the upper and lower sections of the lead frame, and silver plating on it, in order to shorten the wire length when welding with the wafer and increase the transmission speed. (Please read the precautions on the back and then fill out this page) Pack 1, 1T Line Ministry of Economic Affairs Central Standards Bureau Staff Consumer Cooperative Printed 51 This paper standard is applicable to the Chinese netizen ZX (A4) specification (210X 297 hair)
TW85104284A 1996-04-11 1996-04-11 The bonding method of lead frame and die TW293166B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI385773B (en) * 2008-05-21 2013-02-11 Lefram Technology Corp Lead frame carrier and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI385773B (en) * 2008-05-21 2013-02-11 Lefram Technology Corp Lead frame carrier and method of manufacturing the same

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