TW480695B - Method of bonding lead fingers of a lead frame and a substrate - Google Patents

Method of bonding lead fingers of a lead frame and a substrate Download PDF

Info

Publication number
TW480695B
TW480695B TW90107583A TW90107583A TW480695B TW 480695 B TW480695 B TW 480695B TW 90107583 A TW90107583 A TW 90107583A TW 90107583 A TW90107583 A TW 90107583A TW 480695 B TW480695 B TW 480695B
Authority
TW
Taiwan
Prior art keywords
substrate
lead
tape
finger
fingers
Prior art date
Application number
TW90107583A
Other languages
Chinese (zh)
Inventor
Spencer Su
James Lai
Chien-Tsun Lin
Chao-Chia Chang
Original Assignee
Walsin Advanced Electronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Walsin Advanced Electronics filed Critical Walsin Advanced Electronics
Priority to TW90107583A priority Critical patent/TW480695B/en
Application granted granted Critical
Publication of TW480695B publication Critical patent/TW480695B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

A method of bonding lead fingers of a lead frame and a substrate, it includes: (a) providing at least a substrate, its electrically bonding surface has a plurality of connection pads; (b) providing a lead frame, which possesses a plurality of lead fingers and some lead fingers attach a tape; (c) thermally compressing the lead fingers of the lead frame, wherein a solder material between the inner lead of a lead finger and the corresponding connection pad is limited by the tape while thermal compression. As a result, a plurality of lead fingers are bonded to a substrate strongly mechanically and electrically by one thermal compression.

Description

480695480695

【發明領域】 本發明係有關於一種導線架引指與基板之結合方法 〔inner lead bonding method〕,特別係有關於一種導 ,架引指與基板之結合方法,其中該導線架黏貼有一膠 帶,用以固定導線架引指並阻擋焊料之不當流動。 【先前技術】 習知半導體晶片係以一封裝體〔package body〕密 =,用以保護晶片免於外界環境之侵害,並以導線架〔引 指〕作為該半導體封裝之晶片與印刷電路板之電性連接, 如外接腳〔outer 1 ead〕在封裝體四周邊之四方扁平封裝 i Quad Flat Package,QFP〕或外接腳在封裝體其中兩側 之】外型封裝〔Small Outline Package,S0P〕。 、導線架之引指與晶片之内部電性連接,習知係以打線 方式〔wire-bonding〕將焊線電性連接引指與晶片,但其 缺點為必須逐一打線,以形成每一焊線,效率較差。 為了縮短製造時間’特別是在引指與晶片之内部電性 連接過程,美國專利第6, 〇8〇, 60 4號「具有TAB引指之半導 體裝置及其製造方法」揭示一種内引指結合方法〔丨nner lead bonding〕’其係以熱壓合方式〔thermal compression〕達到一次完成多個内引指與晶片電性連接 之目的,如第1及2圖所示,一半導體封裝1〇〇包含有一晶 片1 1 0 ’晶片11 0具有一電性結合面1 1 1,在電性結合面j j 1 上形成有複數個凸塊11 2,並在電性結合面丨丨1上以第一次 熱壓合方式黏貼上一TAB膠帶150〔TAB係為捲帶自動結合[Field of the Invention] The present invention relates to an inner lead bonding method of a lead frame and a substrate, and particularly to a method of bonding a lead and a frame to a substrate, wherein the lead frame is adhered with an adhesive tape, It is used to fix the lead of the lead frame and block the improper flow of solder. [Prior art] It is known that a semiconductor chip is packaged with a package body to protect the chip from the external environment, and a lead frame is used as the semiconductor package chip and the printed circuit board. For electrical connection, such as outer quadratic package [I Quad Flat Package, QFP] on the four perimeters of the package or external pins on both sides of the package] [Small Outline Package, S0P]. 2. The lead fingers of the lead frame are electrically connected to the internal chip. The conventional method is to wire the leads to the chip electrically by wire-bonding, but the disadvantage is that they must be wired one by one to form each wire. , The efficiency is poor. In order to shorten the manufacturing time, especially during the internal electrical connection process between the index finger and the wafer, US Patent No. 6,008,604, "Semiconductor Device with TAB Index and Manufacturing Method" discloses an internal index finger combination Method [丨 nner lead bonding] 'This is to achieve the purpose of electrically connecting a plurality of internal lead fingers to the chip at a time by thermal compression. As shown in Figures 1 and 2, a semiconductor package 100 It includes a wafer 1 1 0 'wafer 11 0 has an electrical bonding surface 1 1 1, a plurality of bumps 11 2 are formed on the electrical bonding surface jj 1, and a first Sub-heat pressing method is used to attach a TAB tape 150 (TAB is automatically reeled by tape

480695 五、發明說明(2)480695 V. Description of Invention (2)

Tape Automated Bonding 之簡稱〕,TAB 膠帶150 係為一軟 質之聚醯亞胺膠帶並形成有一開口 1 5 1,該開口 1 5 1係須小 於晶片1 1 0之電性結合面1 1 1並顯露出晶片電性結合面1 1 1 上之凸塊112,且TAB膠帶150上承載並固定有複數個tab引 指140,以第二次熱壓合一次將多個TAB引指140之内端結 合至對應凸塊11 2 ’再以第三次熱壓合將多個τ A B引指1 4 0 · 之外結合至對應導線架引指1 3 〇,在經模封 〔molding〕、灌膠〔injecti〇n〕及切割〔cutting〕 後’得到如第1及2圖所示之半導體封裝1〇〇,但由於具丁八^ 引指140之TAB膠帶150係為韌性,以供捲收於一捲輪 φ 〔reel〕,TAB引指140在灌膠時並無法提供足夠之機械強 / 度’導致在射出灌膠時〔encapSulant jecti 〇n〕,晶 厂 片11 0在封裝體1 20内之偏移及傾斜,此外,在製程中每一 半導體封裝1 0 〇必須以三次熱壓合方能製得,封裝過 ‘: 然顯得繁項。 【發明目的及概要】 本發明之主要目的在於提供一種導線架引指與基板 結合方法,利用導線架引指以熱壓合方式直接結合至基The abbreviation of Tape Automated Bonding], TAB tape 150 is a soft polyimide tape and is formed with an opening 1 51. The opening 1 5 1 must be smaller than the electrical bonding surface 1 1 1 of the wafer 1 1 1 and exposed. The bumps 112 on the electrical bonding surface 1 1 1 of the wafer are ejected, and a plurality of tab fingers 140 are carried and fixed on the TAB tape 150, and the inner ends of the plurality of TAB fingers 140 are bonded by a second heat compression. To the corresponding bumps 11 2 ′, a plurality of τ AB fingers 1 4 0 · are bonded to the corresponding lead frame fingers 1 3 0 by the third thermal compression, and are subjected to molding [molding], potting [ [injecti〇n] and cutting [cutting] to get the semiconductor package 100 as shown in Figures 1 and 2, but because of the TAB tape 150 with Ding ^ leading 140 is tough, for winding up in one Reel φ [reel], TAB index finger 140 does not provide sufficient mechanical strength / degree when pouring glue, resulting in [encapSulant jecti 〇n] when pouring glue, wafer chip 1 10 is within package 1 20 Offset and tilt, in addition, each semiconductor package 100 in the manufacturing process must be made by three thermal compression bonding, package over ': It seems complicated. [Objective and Summary of the Invention] The main object of the present invention is to provide a method for combining a lead frame finger and a substrate, and the lead frame finger is directly bonded to the substrate by thermocompression bonding.

5連31同呀在引指與基板連接墊之間形成有足量之 带、、i、’ ί二板周邊有一黏附於引指之膠帶,以阻擋焊料 1.2 ^ :料能在引指與基板連接墊之間提供一穩固之 械強度’達到快速而穩固之結合。 ㈣之 本發明之次一目的在於提供一種半導體封裝,盆 焊料直接結合導線架引指與基板之連接塾,並在基板^5th and 31th, a sufficient amount of tape is formed between the index finger and the substrate connection pad. There is an adhesive tape attached to the index finger around the second board to block the solder. 1.2 ^: The material can be between the index finger and the substrate. The connection pads provide a solid mechanical strength to achieve a fast and stable bond. The second objective of the present invention is to provide a semiconductor package. The solder is directly combined with the lead of the lead frame and the substrate.

固之機械性及 依本發明 有:提供至少 電性結合面形 架具有複數個 該複數個引指 指接近内指部 引指具膠帶之 應之基板連接 之間形成有一 以焊接引指之 近基板之電性 【發明詳細說 有一黏附於引指之膠帶, 電性連接之 之導線架引 一基板,該 成有複數個 框孑L,每一 之内指部係 處枯貼一膠 表面朝向基 墊,其中引 焊料,當該 内指部與對 結合面。 明】 以阻擋焊料之溢流,達 結合以及修正模流之功 指與基板之結合方法, 基板具有一電性結合面 連接墊;提供一導線架 框孔内形成有複數個引 對應於該基板之連接墊 帶;及熱壓合導線架之 板之方向將引指之内指 指之内指部與對應之基 焊料熔融時係被該膠帶 應之基板連接墊,且該 到一次穩 效。 其步驟 ’並在該 ’該導線 指,其中 ’並在引 引指,以 部壓迫對 板連接墊 所限制, 膠帶係鄰 «月參閱所附圖式’本發明將列舉以下之實施例說明: ^ 如第3至5圖所示係為本發明之第一具體實施例,一種 導線架引指與基板之結合方法,如第4圖所示,首先提供 二導線架250〔 1 ead frame〕,該導線架25〇係以習知之沖 壓〔stamping〕或蝕刻〔etching〕方法由一銅、鐵或其 ^金〔合金4 2,其含鎳42 %及鐵58 %〕等金屬板製得,在本 貫施例中’以具有較良好導熱性之銅板為較佳,該導線架 250具有複數個框孔251〔 frame h〇ie〕,每一框孔251内 形成有複數個引指230〔 lead finger〕,其中該複數個引 指230之内端係對應於一基板21〇之連接墊213而延伸形成 480695 五、發明說明(4) 一内指部231 〔 i nner lead〕,並在引指230接近内指部 231處枯貼一窗口膠帶240〔window tape〕,使該複數個 引指230不易偏移且共平面,其中窗口膠帶24〇較佳為一具 單面黏性之聚醯亞胺膠帶〔polyimide tape〕,窗口膠帶 2 4 0具有一開口 2 41,開口 2 4 1係略大於基板21 〇,以容置基 板210〔如第3圖所示〕。 在本實施例中,基板210係為一矽基板〔siiicon substrate〕,如半導體晶片等,該基板21〇具有複數個連 接塾21 3〔connection pad〕,如鋁墊,其形成於基板21〇 電性結合面211〔electrically bonding surface〕之周 邊,並在該電性結合面211處形成有積體電路元件 〔integrated circuit element〕,而構成適當之微處理 Is、5己憶體或邏輯晶片’在本實施例中,預先以電_、蒸 鍵、結線或印刷方法在連接塾2 1 3上形成有焊料2 1 2 ' 〔solder material,即所謂的凸塊〕,如金或鉛錫凸 塊0According to the invention, there is provided: at least an electrical bonding surface frame having a plurality of the plurality of finger fingers close to the inner finger finger tape with a tape connection between the substrate connection should be formed with a welding finger Electrical properties of the substrate [Detailed description of the invention is an adhesive tape adhered to a lead, and a lead frame electrically connected to lead a substrate, which is formed into a plurality of frames, L, and an inner surface of each finger is affixed with an adhesive surface. The base pad, which leads the solder, when the inner finger is in contact with the pair of bonding surfaces. Ming] The method of combining the finger and the substrate by blocking the solder overflow, achieving bonding and correcting the mold flow. The substrate has an electrical bonding surface connection pad; a lead frame frame hole is provided with a plurality of leads corresponding to the substrate. Connection pads; and the direction of the plate of the thermocompression lead frame, the inner finger of the inner finger and the corresponding base solder are melted by the substrate connection pad to which the tape should be applied, and it is stable once. The steps are “in” the “wire guide” and “in the guide”, and the pressure is limited to the board connection pad by partial pressure. The tape is adjacent to the “drawings”. The present invention will enumerate the following examples: ^ As shown in FIGS. 3 to 5 is a first embodiment of the present invention, a method for combining a lead frame finger and a substrate, as shown in FIG. 4, firstly providing two lead frames 250 [1 ead frame], The lead frame 25 is made by a conventional stamping or etching method from a metal plate such as copper, iron, or gold [alloy 42, which contains 42% nickel and 58% iron]. In the present embodiment, it is better to use a copper plate with better thermal conductivity. The lead frame 250 has a plurality of frame holes 251, and each frame hole 251 has a plurality of lead fingers 230. finger], wherein the inner end of the plurality of lead fingers 230 corresponds to a connection pad 213 of a substrate 21 and extends to form 480695 V. Description of the invention (4) An inner finger 231 [inner lead] 230 near the inner finger 231 with a window tape 240 [window tape] Several index fingers 230 are not easy to shift and are coplanar. The window tape 24 is preferably a polyimide tape with single-sided adhesiveness. The window tape 2 4 0 has an opening 2 41 and an opening 2 4 1 is slightly larger than the substrate 21 0 to accommodate the substrate 210 [as shown in FIG. 3]. In this embodiment, the substrate 210 is a silicon substrate, such as a semiconductor wafer. The substrate 210 has a plurality of connection pads 21 3 [connection pads], such as aluminum pads, which are formed on the substrate 21. Around the electrical bonding surface 211, and an integrated circuit element is formed at the electrical bonding surface 211, and constitutes an appropriate micro-processing Is, 5 memory or logic chip. In this embodiment, solder 2 1 2 ′ [solder material, ie, so-called bump] is formed on the connection 塾 2 1 3 in advance by electrical, steam bonding, wire bonding, or printing methods, such as gold or lead-tin bump 0

如第5圖所示,當導線架250移動定位,此時,窗口膜 帶240位於引指2 30之下表面,將上述基板2 1〇以一載台4^ j 輸送上升,使引指230黏貼有窗口膠帶24〇之表面〔即下表錢 面〕朝向基板210之電性結合面2 11,引指23〇之内指部23\ 係對應於基板210之連接墊213,並以一壓合頭々iq 〔compression head〕由上往下壓迫引指23〇之内指 2 3 1 ’該壓合頭4 1 0具有攝氏數百度之溫度,使得在引扑 230之内指部231與對應之基板210連接墊213之間的焊料As shown in FIG. 5, when the lead frame 250 is moved and positioned, at this time, the window film strip 240 is located on the lower surface of the index finger 2 30, and the substrate 2 10 is transported and raised by a carrier 4 ^ j to make the index finger 230 The surface on which the window tape 24 is attached (that is, the lower surface of the table) faces the electrical bonding surface 2 11 of the substrate 210, and the finger portion 23 within the lead 23 is a connection pad 213 corresponding to the substrate 210, and a pressure 々Iq [compression head] presses the finger from the top to the bottom within 23 ° and refers to 2 3 1 'The compression head 4 1 0 has a temperature of several hundred degrees Celsius, so that the finger 231 and the corresponding part within the flutter 230 Solder between the substrate 210 and the connection pad 213

480695 五、發明說明(5) 212义熱里及壓力而炫融’進而能以一次敎麼人 引指230之内指部⑶與對應之基板21G連接i 接並夕且個在 熱壓合時,由於窗口膠帶24 0係鄰近基板21〇之電性結合面 2 11,烊料2 1 2係被窗口膠帶2 4 0所限制或阻擔,焊料2 1 2對 金屬類之引指23 0内指部231與連接墊213具有較佳之結合 性,同時在焊料2 1 2自身之表面張力作用下,焊料2丨2能平 均地形成於内指部231與對應連接墊213之間,最後,在封 膠固化及切割後可得到如第3圖所示之半導體封裝2〇〇。 因此,本發明之導線架引指與基板之結合方法具有以 下之功效: 第一、以一次熱壓合能快速地完成導線架引指2 3 0與 基板21 0之結合; 第二、焊料212在窗口膠帶240之限制下,能以足量焊 料212在不溢流之狀況下提供在引指與基板之間之穩固的 機械結合強度;480695 V. Description of the invention (5) 212 The heat and pressure of 212 will be dazzled and melted, and then one person can refer to the inner part of the finger 230 and connect to the corresponding substrate 21G i. Since the window tape 24 0 is adjacent to the electrical bonding surface 2 11 of the substrate 21 0, the material 2 1 2 is restricted or hindered by the window tape 2 4 0. The solder 2 1 2 refers to the metal within 23 0 The finger 231 and the connection pad 213 have a good combination. At the same time, under the surface tension of the solder 2 1 2, the solder 2 丨 2 can be evenly formed between the inner finger 231 and the corresponding connection pad 213. Finally, in the After the sealant is cured and cut, the semiconductor package 200 shown in FIG. 3 can be obtained. Therefore, the method of combining the lead frame finger and the substrate of the present invention has the following effects: First, the combination of the lead frame finger 2 3 0 and the substrate 2 0 can be completed quickly with a single thermal compression; second, solder 212 Under the restriction of the window tape 240, a sufficient amount of solder 212 can provide a stable mechanical bonding strength between the index finger and the substrate without overflowing;

第二、引指230在窗口膠帶240之限制下,在製程中具 有引指共平面且不易偏移之優點,在封膠後,不須修剪支 撑肋〔dam bar〕 弟四、窗口勝帶240係位於基板210鄰近週邊,在適當 之形狀下具有修正模流之功效。 依上述之導線架引指與基板之結合方法,如第3圖所 示’ 一半導體封裝20 0係包含有一基板210,該基板210具 有一電性結合面21 1,並在該電性結合面2 11形成有複數個 連接墊213 ;複數個引指2 30,其中該複數個引指23〇具有Second, the index finger 230 has the advantage that the index finger is coplanar and is not easy to shift during the process under the limitation of the window tape 240. After sealing, there is no need to trim the support rib (dam bar). It is located near the periphery of the substrate 210, and has the effect of correcting the mold flow in a proper shape. According to the above-mentioned method of combining the lead frame finger and the substrate, as shown in FIG. 3, a semiconductor package 200 includes a substrate 210, and the substrate 210 has an electrical bonding surface 21 1 on the electrical bonding surface. 2 11 is formed with a plurality of connection pads 213; a plurality of fingers 2 2 30, wherein the plurality of fingers 23 have

第9頁 五、發明說明(6) 在内^之内4曰部231及在封裝體220外之外接腳232,其中 内‘部2 3 1係對應於該基板2 1 〇之連接墊2 1 3 ;複數個焊料 212 ’形成於内指部231與連接墊213之間,以電性連接並 機械結合引指23 0與基板21 0 ; —窗口膠帶24〇,點貼於引 指230朝向基板2 10電性結合面211之一表面,並鄰近基板 210之電性結合面211,用以固定引指23〇以及限制焊料 212,及一封裝體220,用以保護基板21〇,因此,該半導 體封裝20 0具有快速封裝、穩固的機械結合強度以及修正 上下模流之功效。 與基板之結合方法 …等等,特再列舉第 為使瞭解在本發明之導線架引指 中,不局限基板之種類、膠帶之形狀 '一具體貫施例。 一印斤示,首先提供—基板310,該基板310係為 二印'電路板或陶兗電路基板,其具有一電性結合面 釣墊箄二-性結合面311形成有複數個連接墊313,如 手指〔gold finger〕,而报# & ε係為電路基板31〇之^ 弈承恭古$奴7 而$成為長指狀,該基板3 10可予 先承載有複數個晶片35G〔如第9圖所示〕。 導線Π7有圖複所二二後提供—導線架〔圖未緣出〕,該 部如係對應於該基板31 〇之連接中塾=數:^旨33匕内养 之-表面電鍍形成有焊料 “:在内心抑1 等導電焊接材, 1如鎳、鈀、鉛錫、金、銀 處枯貼-條狀膠帶34〇。°側之引指330接近内指部331 480695 五、發明說明(7) 如第8圖所示’熱壓合該複數個引指3 3 〇,以引指3 3 〇 具膠帶340之表面朝向基板31〇之方向將引指33〇之内指部 310壓迫對應之基板連接墊313,其中引指330之内指部331 與對應之基板連接墊3 1 3之間之焊料3 1 2係熔融並被鄰近基 板310之膠帶340所限制,有效保留足量焊料312以焊接引 指3 3 0之内指部3 3 1與對應之基板連接墊3丨3,最後在模封 灌膠固化及切割後,得到一多晶片之半導體封裝3〇〇,同 樣地,依本發明之導線架引指與基板之結合方法,該 二:J3:0亦具有可供快速封裝製得、穩固的機械結: 度以及修正上下模流之功效。 ^ 故本發明之保護範圍當視後附之申請專利 者為準,任柯孰土 μ苔姑藏i 圍所界疋 4 1千仕何热知此項技蟄者,在不脫離本發〜 範圍内所作之任何變化與修改,均屬於,二之精神和 圍。 ♦七明之保護範 480695 圖式簡單說明 【圖式說 第1圖: 第2 圖: 第3圖: 第4圖: 第5圖: 第6圖: 第7圖: 第8圖: 第9圖: 【圖號說 100 半導 II 0晶片 III 電性 明】 美國專利 裝置及其 美國專利 裝置及其 視圖; 依本發明 導體封裝 依本發明 供之導線 依本發明 供之導線 依本發明 提供之基 依本發明 提供之導 依本發明 所提供之 依本發明 半導體封 明】 體封裝 結合面 第 6, 0 8 0, 6 04 號「具有TAB 製造方法」之半導體封裝 第 6, 0 80, 604 號「具有TAB 製造方法」之半導體封裝 引指之半 結構截面 引指之半 結構之頂 導體 圖, 導體 面透 之導線 結構截 之導線 架示意 之導線 架與基 之導線 板仰視 之導線 線架仰 之導線 導線架 之導線 裝結構 架引指與基板之結合方法,一半 面圖; 架引指與基板之結合方法,所提 圖; 架引指與基 板之結合示 架引指與基 不意圖, 架引指與基板之結合方法,另一 視示意圖; 架引指與基 與基板之結 架引指與基 截面圖;。 板之結合方法,所提 意圖; 板之結合方法,另一 板之結 合示意 板之結 合方法 圖;及 合方法 另一 另 112凸塊Page 9 V. Description of the invention (6) Within the inner part 4 is the part 231 and the pin 232 is outside the package 220, wherein the inner part 2 3 1 is the connection pad 2 1 corresponding to the substrate 2 1 0 3; A plurality of solders 212 'are formed between the inner finger portion 231 and the connection pad 213, and are electrically connected and mechanically combined with the finger 23 0 and the substrate 21 0;-the window tape 24o, point on the finger 230 toward the substrate 2 10 One surface of the electrical bonding surface 211, which is adjacent to the electrical bonding surface 211 of the substrate 210, is used to fix the finger 23o and the limiting solder 212, and a package 220 to protect the substrate 21o. Therefore, this The semiconductor package 200 has the advantages of fast packaging, stable mechanical bonding strength, and correction of upper and lower mold flow. The method of combining with the substrate… etc., in order to understand that in the lead frame index of the present invention, the type of the substrate and the shape of the tape are not limited. A printed substrate is first provided-a substrate 310, which is a two-printed circuit board or a ceramic circuit board, which has an electrical bonding surface and a mating surface 311, and a plurality of connection pads 313. For example, as a finger [gold finger], the report # & ε is a circuit board 31〇 ^ 承承公 古 $ 奴 7 and $ becomes a long finger, the substrate 3 10 can be pre-loaded with a plurality of wafers 35G [ As shown in Figure 9]. The wire Π7 is provided after the second copy of the picture—the lead frame [not shown in the figure]. If the part corresponds to the connection of the substrate 31 塾 = number: ^ Purpose 33 内 内 之 之-the surface is formed with solder ": Inner core 1 and other conductive welding materials, 1 such as nickel, palladium, lead-tin, gold, and silver are affixed-strip tape 34 °. The index finger 330 on the side is close to the inner finger 331 480695 5. Description of the invention ( 7) As shown in FIG. 8, the plurality of fingers 3 3 〇 are hot-pressed, and the finger 310 within the finger 33 is pressed in correspondence with the surface of the finger 3 3 〇 with the tape 340 toward the substrate 31 〇 For the substrate connection pad 313, the solder 3 1 2 between the inner finger portion 331 of the lead 330 and the corresponding substrate connection pad 3 1 3 is melted and restricted by the tape 340 adjacent to the substrate 310, effectively retaining a sufficient amount of solder 312 The inner finger 3 3 1 of the soldering lead 3 3 0 and the corresponding substrate connection pad 3 3 and 3 are finally cured and cut after molding, to obtain a multi-chip semiconductor package 300. Similarly, according to According to the method for combining the lead frame finger and the substrate of the present invention, the second: J3: 0 also has a stable mechanical junction which can be obtained by rapid packaging: Degree and the effect of correcting the upper and lower mold flow. ^ Therefore, the scope of protection of the present invention shall be subject to the patent applicant attached hereto. Those who do not depart from the scope of the present ~ are all within the spirit and scope of the second. ♦ Qiming's protection range 480695 Schematic description of the diagram [Schematic diagram No. 1: Picture 2: No. Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: [Figure says 100 semiconducting II 0 chip III electrical properties] US patent device and US patent device And a view thereof; a conductor package according to the present invention; a conductor provided according to the present invention; a conductor provided according to the present invention; a base provided according to the present invention; a guide provided according to the present invention; a semiconductor seal according to the present invention; No. 6, 0 8 0, 6 04 "Semiconductor package with TAB manufacturing method" No. 6, 0 80, 604 "Semiconductor package with TAB manufacturing method" Reference semi-structured top conductor Figure, conductor knot through the conductor The lead frame shown in the cut-off lead frame and the base lead plate are viewed from the bottom. The lead frame is supported by the lead frame of the lead frame. The illustration of the combination of the frame index and the substrate shows the intention of the frame index and the base, the method of combining the frame index and the substrate, another schematic view; the cross section of the frame index and the base and the substrate; . Board bonding method, the proposed intention; board bonding method, another board bonding diagram, board bonding method diagram; and bonding method another 112

第12頁 480695 圖式簡單說明 120 封 裝 體 130 引 指 140 TAB引指 150 TAB膠帶 151 開 σ 200 半 導 體 封 裝 210 基 板 211 電 性 結 合 面 212 焊 料 213 連 接 塾 220 封 裝 體 230 引 指 231 内 指 部 232 外 接腳 240 窗 σ 膠 帶 241 開 V 250 導 線 架 251 框 子L 300 半 導 體 封 裝 310 基 板 311 電 性 結 合 面 312 焊 料 313 連 接 墊 320 封 裝 體 330 引 指 331 内 指 部 340 膠 帶 350 晶 片 410 壓 合 頭 420 載 台Page 12 480695 Brief description of the diagram 120 Package 130 Lead 140 TAB Lead 150 TAB Tape 151 Open σ 200 Semiconductor package 210 Substrate 211 Electrical bonding surface 212 Solder 213 Connection 塾 220 Package 230 Lead 231 Inner finger 232 External pin 240 window σ tape 241 open V 250 lead frame 251 frame L 300 semiconductor package 310 substrate 311 electrical bonding surface 312 solder 313 connection pad 320 package 330 lead 331 inner finger 340 tape 350 chip 410 compression head 420 load station

第13頁Page 13

Claims (1)

480695 六、申請專利範圍 1、一種導線架引指與基板之結合方法,其包含之步驟 有: 提供至少一基板,該基板具有一電性結合面,並在該 電性結合面形成有複數個連接墊; 提供一導線架,該導線架具有複數個框孔,每一框孔 内形成有複數個引指,其中該複數個引指之内指部係對 應於該基板之連接墊,並在引指接近内指部處粘貼一膠 帶;及 熱壓合導線架之引指,以引指具勝帶之表面朝向基板 之方向將引指之内指部壓迫對應之基板連接墊,其中引 指之内指部與對應之基板連接墊之間形成有一焊料,當 該焊料溶融時係被該膠帶所限制,以焊接引指之内指部 與對應之基板連接墊,且該膠帶係鄰近基板之電性結合 面。 、如申請專利範圍第1項所述之導線架引指與基板之結 合方法,其中該基板係為一晶片。 、如申請專利範圍第1項所述之導線架引指與基板之結 I方法,其中該基板係為一電路基板。 4、 如申請專利範圍第1項所述之導線架引指與基板之結 合方法,其中該基板之連接墊係呈長指狀。 5、 如申請專利範圍第1項所述之導線架引指與基板之結 合方法,其中該膠帶係為一窗口膠帶,其具有一開口, 該開口係略大於基板之電性結合面。 6、 如申請專利範圍第1項所述之導線架引指與基板之結480695 VI. Application Patent Scope 1. A method for combining a lead frame finger and a substrate, comprising the steps of: providing at least one substrate, the substrate having an electrical bonding surface, and a plurality of electrical bonding surfaces being formed on the electrical bonding surface Connection pad; providing a lead frame, the lead frame has a plurality of frame holes, a plurality of lead fingers are formed in each frame hole, wherein the inner fingers of the plurality of lead fingers correspond to the connection pads of the substrate, and A tape is affixed near the inner finger of the lead; and the lead of the thermocompression lead frame is pressed against the corresponding substrate connection pad with the surface of the lead with the leading tape facing the substrate, where the lead is A solder is formed between the inner finger and the corresponding substrate connection pad. When the solder is melted, it is restricted by the tape. The inner finger of the index finger is soldered to the corresponding substrate connection pad, and the tape is adjacent to the substrate. Electrical bonding surface. The method for combining a lead frame lead and a substrate as described in item 1 of the scope of patent application, wherein the substrate is a wafer. The method of connecting a lead frame finger to a substrate as described in item 1 of the scope of patent application, wherein the substrate is a circuit substrate. 4. The method of combining the lead frame finger and the substrate as described in item 1 of the scope of the patent application, wherein the connection pads of the substrate are long fingers. 5. The method for joining the lead frame finger and the substrate as described in item 1 of the scope of the patent application, wherein the tape is a window tape having an opening slightly larger than the electrical bonding surface of the substrate. 6. The lead frame lead as described in item 1 of the scope of the patent application, and the substrate 480695 六、申請專利範圍 合方法,其中該膠帶係呈條狀 7、 一種半導體封裝,其包含有: 一基板,該基板具有一電性結合面,並在該 面形成有複數個連接墊; 複數個引指,其中該複數個引指之内指部係 基板之連接墊; μ 複數個焊料,形成於内指部與連接墊之間; 至少一膠帶,粘貼於引指朝向基板電性結合 面’並鄰近基板之電性結合面;及 一封裝體。 8、 如申請專利範圍第7項所述之半導體封穿, 板係為一晶片。 9、 如申睛專利範圍第7項所述之半導體封裝, 板係為一電路基板。 、 1 〇、如申請專利範圍第9項所述之半導 電路基板承載有至少一晶片。 封裝 11、如申請專利範圍第7項所述之半 基板之連接塾係呈長指狀。 封裝 1 2如申睛專利範圍第7項所述之半導 夥帶係為—窗口膠帶,其具有-開口,該ί 於基板之電性結合面。 該開 13 π如申晴專利範圍第7項所述之半導體封# 膠帶係呈條狀。 封裝 電性結合 對應於該 面之一表 其中該基 其中該基 ,其中該 ,其中該 ,其中該 口係略大 ,其中該480695 VI. Method for applying patent scope, wherein the adhesive tape is strip-shaped 7. A semiconductor package includes: a substrate having an electrical bonding surface, and a plurality of connection pads formed on the surface; Fingers, in which the inner fingers of the plurality of fingers are the connection pads of the substrate; μ a plurality of solders are formed between the inner fingers and the connection pads; at least one tape is affixed to the electrical bonding surface of the fingers toward the substrate 'And adjacent to the electrical bonding surface of the substrate; and a package. 8. According to the semiconductor package mentioned in item 7 of the scope of patent application, the board is a wafer. 9. As in the semiconductor package described in item 7 of the Shenjing patent scope, the board is a circuit substrate. 10. The semiconductor substrate described in item 9 of the scope of patent application carries at least one wafer. Package 11. The connection of the semi-substrate as described in item 7 of the scope of patent application is a long finger. Package 12 The semiconductor tape as described in item 7 of the patent scope of Shenyan is a window tape, which has an opening, which is the electrical bonding surface of the substrate. The opening 13 π is a semiconductor sealing tape as described in item 7 of Shen Qing's patent scope. The package is electrically connected to a surface corresponding to one of the surfaces, wherein the base, the base, where the, where the, where the mouth is slightly larger, where the 第15頁Page 15
TW90107583A 2001-03-28 2001-03-28 Method of bonding lead fingers of a lead frame and a substrate TW480695B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW90107583A TW480695B (en) 2001-03-28 2001-03-28 Method of bonding lead fingers of a lead frame and a substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW90107583A TW480695B (en) 2001-03-28 2001-03-28 Method of bonding lead fingers of a lead frame and a substrate

Publications (1)

Publication Number Publication Date
TW480695B true TW480695B (en) 2002-03-21

Family

ID=21677805

Family Applications (1)

Application Number Title Priority Date Filing Date
TW90107583A TW480695B (en) 2001-03-28 2001-03-28 Method of bonding lead fingers of a lead frame and a substrate

Country Status (1)

Country Link
TW (1) TW480695B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI478295B (en) * 2009-03-11 2015-03-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI478295B (en) * 2009-03-11 2015-03-21

Similar Documents

Publication Publication Date Title
US9991213B2 (en) Resin-encapsulated semiconductor device and its manufacturing method
KR100470897B1 (en) Method for manufacturing dual die package
JP3297254B2 (en) Semiconductor package and manufacturing method thereof
JP2556294B2 (en) Resin-sealed semiconductor device
US8399970B2 (en) Semiconductor device attached to island having protrusion
JP2014220439A (en) Method of manufacturing semiconductor device and semiconductor device
TW200805526A (en) Semiconductor device, and method of manufacturing the same
JP2000077435A (en) Semiconductor device and manufacture thereof
JP3663295B2 (en) Chip scale package
US6590279B1 (en) Dual-chip integrated circuit package and method of manufacturing the same
JP3638750B2 (en) Semiconductor device
US20020182773A1 (en) Method for bonding inner leads of leadframe to substrate
JPH08139218A (en) Hybrid integrated circuit device and its manufacture
TW483134B (en) Micro BGA package
TW480695B (en) Method of bonding lead fingers of a lead frame and a substrate
JP3454192B2 (en) Lead frame, resin-sealed semiconductor device using the same, and method of manufacturing the same
JP3241772B2 (en) Method for manufacturing semiconductor device
JPH0338057A (en) Flagless lead frame, and package using it, and manufacture
TWI285407B (en) LOC (lead-on-chip) IC package
JP3406147B2 (en) Semiconductor device
TWI239059B (en) Chip packaging method chip package structure
JP2010056325A (en) Semiconductor device and method of manufacturing same
JP2681145B2 (en) Resin-sealed semiconductor device
KR100352112B1 (en) Structure of chip-sized semiconductor package and fabricating method thereof
JP2000164790A (en) Lead frame, semiconductor device provided therewith, and manufacture thereof

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees