TW293150B - - Google Patents

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TW293150B
TW293150B TW085102998A TW85102998A TW293150B TW 293150 B TW293150 B TW 293150B TW 085102998 A TW085102998 A TW 085102998A TW 85102998 A TW85102998 A TW 85102998A TW 293150 B TW293150 B TW 293150B
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polycrystalline silicon
gate
bridge
conductive material
layer
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TW085102998A
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Samsug Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Plasma & Fusion (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)

Description

經濟部中央標準局員工消費合作社印製 A7 B7 — — 五、發明説明（1 ) 發明背景 本發明係關於一種半導體記憶裝置製造方法，尤指一 種降低以離子化氣體加諸於複晶矽層之電漿蝕刻過程中所 必然產生的電荷累積。 通常，在半導體裝置的製造過程中需要一些蝕刻步 驟。此外，使用離子化氣體的電漿蝕刻過程廣泛地在半導 體裝置的製造中使用。在電漿處理過程中，用於電漿蝕刻 的離子以及被蝕刻的裝置離子結合在一起，因而在被蝕刻 的裝置中收集了不需要的離子。該等累積的離子降低了裝 置中所產生的應力電流（stress current)，所以可會g 在MOS電晶體內鄰近複晶矽層之薄氧化層之處產生崩潰 (breakdown) 〇也就是說，在形成MOS電晶體之閘極的 圖案的情況中，在爲形成閘極所爲之電漿蝕刻期間所產生 的電荷累積於被蝕刻的裝置中。以這種方式所累積的離子 導致了流經閘極與基體間之閘極氧化層的號勒-諾得海 (Fowler-Nordheim)電流，且因此電荷被捕捉於閘極 氧化層內。此外，被捕捉於閘極氧化層內的電荷降低閘極 氧化層的崩潰電壓，因而引發M0S電晶體之閘極氧化層的 崩潰。另外，以半導體裝置的高積體化及低溫，電晶體的 薄氧化層有變薄的傾向。既然閘極氧化層對於因電漿蝕刻 過程所產生的電荷累積所致之應力變得比較敏感，由於該 2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ----------^------1T'|_一_----^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消費合作社印製 A7 B7 五、發明説明（2 ) 應力的閘極氧化層的退化即行產生，並導致了產品品質的 惡化。 圖1A係習知NMOS電晶體在金屬蝕刻過程中的截面 圖，而圖1B表示了圖1A的等效電路》以圖ΙΑ,ΙΒ來解釋 消除金靥蝕刻過程期間的電漿蝕刻所導致之損壞的程序* 在電漿蝕刻過程期間，在晶圓材料上反應的材料大部份是 正離子，而該正離子經由金屜或複晶矽直接或間接地與電 晶體的閘極連接》因此，離子引發了對電晶體閘極的正方 向性電壓。 在本發明之複晶矽閘極NMOS電晶體結構中，η型雜質 110形成於一 Ρ型基體100之二側，而一閘極氧化層150形 成於基體100上。因此，由於施加於閘極130之正電荷所 形成的電場，Fowler-Nordheim電流在鬧極150內產 生。當負電荷由於該F-N電流而於電晶體的閘極氧化層內 增加時，臨界電壓（threshold voltage)增加。所 以，增加的臨界電壓導致了閛極氧化層內的崩潰。 分析上述臨界電壓的偏移（shift)現象，二極體120 連接於閘極130與基體100之間，所以連接至電晶體閘極 130的電荷可能放電於基體100之內。也就是說，爲了防 止F-N電流所造成之導致臨界電壓位移的崩潰*二極體 120被形成於半導體基體100之上，隨後形成金屬天線 140以便連接閘極電極130與二極體120，藉此將收集於 閘極130的電荷經由二極體120放電至半導體基體100 內。然而，在如前所述的NM0S電晶體內，二極體係與半導 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ----------^------ΐτ--：----^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（3 ) 體基體成反向偏壓關係，而因此難以使連接至閘極130的 電荷放電。此外還有因電荷被收集於閘極內所產生之閘極 氧化層1 5 0加速退化的問題。 爲解決圖一所產生的問題，圖二電晶體形成了如下的 結構。取代圖一的二極體，一雙載子接面電晶體BJT200 連接於閘極130與基體100之間。因此，如果BJT200藉由 電漿蝕刻過程中所產生的電荷而導通，閘極130與基體自 動互相連接，而與閘極13 0連接的電荷放電至基體內。藉 此防止閘極氧化層的退化。因此，經由上述的方法可以防 止在金屬蝕刻過程中所產之由電槳引發的電荷所造成的損 壞，但仍有一個由在複晶矽蝕刻過程中之電漿蝕刻所產生 的嚴重問題極待解決。 發明綜合說明 因此，本發明之一目的在於提供一種半導體記憶裝置 製造方法，能夠使以離子化氣體施加於複晶矽層之電漿触 刻過程中所累積於一氧化層內的電荷降至最少》 本發明之另一目的在提供一種半導體記憶裝置製造方 法，使在使用電漿形成複晶矽閘極圖案時所產生的電荷累 積減至最少，而能夠降低對複晶閘極與基體間之氧化層造 成影響的應力（stress)。 4 本紙張尺度適用中國國家標準（CNS ) A4说格（210X297公釐） 裝17線 (請先閲讀背面之注意事項再填寫本頁) S〇3i5〇 A7 B7 五、 發明説明（4 本發明之次一目的在提供一種半導體記憶裝置製造方 法，可以使造成閘極氧化層退化之電漿蝕刻所致之電荷累 積降至最小而保護了閘極氧化層。 本發明之又一目的在供一種半導體記憶裝置製造方 法，可以使複晶矽蝕刻過程中造成閘極氧化層退化之電漿 蝕刻所致之電荷累積降至最小而防止裝置的崩潰，並且解 決因電荷累積所造成之電晶體臨界電壓的位移現象。 爲達成上述及其它目的，在依據本發明原理之半導體 記憶裝置之製造方法中包括一電漿蝕刻步驟用以形成一複 晶矽閘極，爲了降低氧化層內的累積電荷所致之損壞，複 晶砂閘極被分爲形成於一主動區域（active region)中 之閘極複晶矽以及形成於一非主動區域（inactive r e g i ο η )中用以蝕刻的橋複晶矽。 圖式簡要說明 經濟部中央標準局貝工消費合作杜印製 本發明得藉下列圖式及詳細說明俾得一深入了解，其 中相同的標號指示相同或相似的部份，其中： 圖1Α :係用以解釋習知金屬蝕刻步驟之NM0S截面 rcrt ·圖， 圖1 B :係圖1 A之等效電路； 圖2A :係用以解釋金屬蝕刻步驟之另一 NU0S截面 nsrt · 圖， 圖2B :係圖2A之等效電路； 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） ----------餐------IT'—-----線- (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（5) 圖3 :係解釋習知複晶矽閘極製造過程之示圖； 圖4 :表示在蝕刻過程後即將被蝕刻之一裝置的截面 結構，用以解釋習知複晶矽閘極的製造過程； 圖5 :表示圖4即將被蝕刻之裝置的平面圖； 圖6 :表示一將被蝕刻之裝置的平面圖，用以解釋依 據本發明原理之半導體記憶裝置之製造方法》 較佳實施例詳細說明 以下將參照所附之圖3,4, 5而解釋本發明較佳實施例 之結構及運作細節。此外，足以混淆本發明之功能及結構 的事物將不予以描述。 參照圖3，爲解釋複晶矽閘極製造過成，一複晶矽間 極330分佈於一場氧化層320及一形成於一 p型基體的薄氧 化層360之上，而一鶴的砂化物340(tungsten silicide)形成於複晶政之上。 圖4表示在蝕刻過程後將被蝕刻之一裝置的截面結構 圖，用以解釋包括使用含數百瓦特能量的電漿370的蝕刻 步驟的複晶矽閘極製造過程。在圖4，由於複晶閘極330， 鎢的矽化物340及光阻350收集的電荷，應力（stress) 施加於電晶體的閘極氧化層360，因而導致了閘極氧化層 3 6 0的退化。 圖5表示MOS電晶體的平面結構，包括複晶矽閘極 540，一源極530連接至一接地線550，以及一汲極510連 6 本紙張尺度適用中國國家梂準（CNS ) A4規格（210X297公釐） ---------裝-------——^----線. (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標率局員工消費合作社印製 A7 ,__ B7i、發明説明（6 ) 接至其它電晶體530的閘極。在圖5，一栓鎖區域570代表 該處被加上了複晶矽矽蝕刻過程中所產生的損壞。此時， 電漿蝕刻損壞施加應力至閘極氧化層，因而導致了閘極氧 化層的損壞。 圖6表示將被蝕刻之裝置的平面結構圖，用來解釋依 據本發明原理之半導體記憶裝置之製造方法。以圖6解釋 降低被電漿蝕刻損壞所影響之栓鎖區域570中所收集的電 荷。在圖6中，爲了藉由降低電漿蝕刻時受影響的複晶矽 區域而使電漿蝕刻的損壞降至最小，栓鎖區域570被分爲 一閘極複晶矽部份610以及一橋複晶矽部份620。 另一方面，如果希望縮小電晶體的複晶閘極570的區 域而降低在閘極氧化層內所產生的應力，電漿蝕刻損壞可 以減小。此時，形成於主動區域（active region)內的 閘極複晶矽部份610與和該部份610分開的橋複晶矽部份 620的長度比大約是1比10。此外，閘極複晶矽部份610 及和該部份610分開的橋複晶矽部份620係由導電材料 6 0 0連接，如金靥之類。 在如前所述之本發明中，藉由降低在使用電漿蝕刻的 過程中所產生的電荷累積而存在著降低電漿蝕刻所產生之 損壞的益處。此外，閘極氧化層的退化可以被防止，且因 此消除了 Fowler-Nordheim電流所造成的臨界電壓篇移 現象。因此具有防止閘極氧化層崩潰的益處。 當本發明係參照特定實施例而爲描述時，所有的描述 僅爲舉例之用而非用以限制本發明。熟悉本技藝之人士於 (請先閱讀背面之注意事項再填寫本頁) .裝. 訏 線 7 本紙張尺度逋用中國國家標準（CNS ) A4規格（210 X 25>7公釐） A7 B7 五、發明説明（7 ) 不悖離本發明申請專利範圍所定義之眞實精神及範圍的情 況下可有不同修飾。 ---------裝------ΐτΓί.:----線· (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印策 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）

Claims (1)

  1. 經濟部中央標準局員工消费合作杜印製 293150 ll ___ D8 ☆、申請專利範圍 1. —種使用電漿蝕刻步驟之半導體記憶裝置製造方法，包 括下列步驟： 形成該半導體記憶裝置之相互分離之一閘極複晶砂層 及一橋複晶矽層，其中該閘極複晶矽層係分佈於一主動區 域（active region)內而該橋複晶矽層係分佈於一非主 動區域（inactive region)內； 以一導電材料連接於該閘極複晶矽層與該橋複晶矽層 之間。 2. 如申請專利範圍第1項之方法，其中該電漿蝕刻步驟使 用數百瓦特電位能量的離子化氣體。 3. 如申請專利範圍第1項之方法，其中該導電材料從該閘 極複晶矽至該橋複晶矽層具有不同的導電度。 4. 如申請專利範圍第3項之方法，其中該導電材料係金 屬。 5. 如申請專利範圍第1項之方法，其中該閘極複晶矽與該 橋複晶矽之長度比爲1比1 0或更多。 6. —種半導體記憶裝置之複晶矽閘極，包括一第一複晶砂 層形成於一主動區域（active region)，一第二複晶砂 形成於一非主動區域（inactive region)，以及一導 電材料連接於該相互分離的第一與第二複晶矽，該導電材 料從該等複晶矽層具有不同的導電度。 9 本紙張尺度適用中國國家梯準（CNS〉A4規格（210 X 297公釐〉 In 1VH J^i tl^^i f^i— i m'- ^ I n^i flun n ϋκ i V~-J^1/1 ^^^^1 nt ^^^^1 - 务 .% J 备 (請先間讀背面之注意事項再填寫本頁)
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