4 I 25twf.doc/006 A7 B7 五、發明説明（/ ) 本發明是有關於一種積體電路之靜電放電(Electrostatic Discharge ;簡稱ESD)保護電路，且特別是有關於—種與其 之內部電路同時製造完成，無須增加額外光罩來完成ESD 植入與基納崩潰植入之靜電放電保護電路的製造方法。 在積體電路(1C)例如動態隨機存取記憶體(DRAM)、靜 態隨機存取記憶體（SRAM)的製造過程中或是晶片完成 後，靜電放電事件常是導致積體電路損壞的主要原因，因 此我們通常都會順道在其內部製造一靜電放電保護電路， 以避免因外來靜電而導致積體電路受到傷害(damage)。例 如在地毯上行走的人體，於相對濕度(RH)較高的情況下可 檢測出約帶有幾百至幾千伏的靜態電壓，而於相對濕度較 低的情況下則可檢測出約帶有一萬伏以上的靜態電壓。當 這些帶電體接觸到晶片時，將會向晶片放電，結果有可能 造成晶片失效。以目前最普遍的互補式金氧半(CMOS)製程 技術而言，靜電放電事件所產生的問題尤其嚴重。 於是’爲了避免靜電放電損傷晶片，各種防制靜電放 電的軟體與硬體便因應而生。最常見的習知作法是利用硬 體防制靜電放電，也就是在內部電路(Internal Circuit)與每 一焊墊(Pad)間，均設計一靜電放電保護電路以保護其內部 電路。目前，靜電放電的問題已成爲深次微米積體電路故 障的主要原因之一。所以，如何有效提昇靜電放電保護電 路的效率乃爲目前業界所亟盼的。 再者，由於閘氧化層之形成厚度隨著製程積集度同步 縮小的因素，使得閘氧化層的崩潰電壓將逐步逼近源極/ 3 本紙張尺度適用中國囷家標準（CNS ) /\4^将（2丨OX297公 —?---------"-裝------訂------味 (誚先閲讀背面之注意事項再填寫本頁) 經漭部中央標準局只工消f合作社印^ 經满部中央標攀局β工消费合作社印^ 4 1 25twf.d〇c/006 A? B7 五、發明説明（>) '汲極接面崩潰電壓，甚或更低，此時原來的ESD保護電路 設計效能將大打折扣。此外，內部電路多半依循最小設計 準則（Minimum Design Rules)設計，且未適當地設計(例如接 觸窗到擴散區的邊緣以及接觸窗到閘極邊緣均需要較大的 空間）以抵抗巨大的靜電放電暫態電流(Transient Current) ’ 致使在高積集度的情況下，晶片極容易受到靜電放電的損 害。 因此，以往ESD保護電路係採用耦合式二極體或耦合 式金氧半元件來達成，由於依此方法其功率消耗很大，無 法承受較大的ESD應力（stress)，當閘氧化層厚度縮小使閘 氧化層崩潰電壓亦同步下降時，若崩潰電壓降至金氧半接 面崩潰左右，傳統ESD保護電路效能將大打折扣。 請參照第1A〜1D圖，第1A〜1D圖繪示的是習知一種積 體電路之靜電放電保護電路的製造流程剖面圖。 首先請參照第1A圖，提供一半導體基底10,在半導體 基底10上形成隔離結構12以界定出元件區14及保護電路 區16，其中隔離結構12例如爲淺溝渠隔離結構或場氧化 層。並且，在元件區14及保護電路區16中分別形成金氧 半電晶體18與20。金氧半電晶體18包括閘氧化層22、多 晶矽層24、間隙壁26及淡摻雜汲極區結構(Lightly Doped Drain ;簡稱LDD)之源極/汲極區28(包括N+離子摻雜區與 N-離子摻雜區）。以及，金氧半電晶體20包括閘氧化層30、 多晶矽層32、間隙壁34及LDD結構之源極/汲極區36(包 括N+離子摻雜區與N-離子摻雜區）。 4 本紙張尺度適用中國國家標準（CNS ) Λ4規枋（210Χ 297ϋ_*^ … — ---Γ----^-裝------訂------瘃 yf, (誚先閱讀背而之注意事項再填寫本N ) 4125twf.doc/〇〇6 A7 B7 五、發明説明（>) 接著請參照第1B圖，進行自行對準金屬矽化物製程 (Salidde)，以同時在多晶矽層24、32及源極/汲極區28、 36上分別形成一層金屬矽化物層38、39、40與41。 再來請參照第1C圖，形成一層光阻層42同時覆蓋及 曝光顯影蝕刻出元件區14及保護電路區16中之金屬矽化 物層40與部分金屬砂化物層41，其中覆蓋於部分金屬砂 化物層41上之光阻層42，其與多晶矽層32之距離約爲2 微米。之後，以乾蝕刻的方式去除未被光阻層42覆蓋之金 屬矽化物層41，直到暴露出源極/汲極區36爲止。 然後請參照第1D圖，以新的光阻層44爲罩幕，去除 間隙壁34。然後於暴露出之源極/汲極區36中植入濃度較 濃的離子(例如N+離子），以消除源極/汲極區36之N-離子 摻雜區，形成濃摻雜之源極/汲極區36a。隨後去除光阻層 44 ° 接著，進行後續的步驟，以完成積體電路的製造，然 而此後續製程爲習知此技藝者所熟知，無關本發明之特 徵，故此處不再贅述。 由上述的製造流程得知’積體電路之靜電放電保護電 路的製造係與其內部電路同時製造完成的，不需另外多加 製程步驟來竞成。雖然習知靜電放電保護電路之結構具有 濃的N離子慘雜區，其可降低高接面電阻而得到一均句的 功率耗散(Power Dissipation) ’然而卻無法降低接面崩潰電 壓(Junction Breakdown Voltage)，以致不利於保護35埃以下 之閘極氧化層厚度的內部元件。 5 本紙張尺度適用中國國家梂準（CNS Μ心兄枱（210Χ29λ)>^ ) ------------ (对先閲讀背面之注意事項再填寫本頁} 1¾衣· iM---- . 經滅部中央橾準局貝工消费合作社印製 4 1 25twt.doc/006 A7 B7 經滴部中央標率局貝工消费合作社印^ 五、發明説明（y) 有鑒於此，本發明的目的就是在提供一種積體電路之 靜電放電保護電路的製造方法，以避免高積集度時之薄氧 化層無法抵抗巨大的靜電放電暫態電流，導致晶片容易受 到靜電放電之損害的問題。 爲達成上述和其他目的，本發明提供一種靜電放電保 護電路的製造方法，係與其之內部電路同時製造完成，無 須增加額外光罩，即可完成ESD植入與基納崩潰植入之步 驟，並且經由控制N+或P+濃度來達到所要求的觸發電壓 値，使其觸發電壓低、功率損耗低，以達到保護在高積集 度時之薄閘氧化層的功能，同時不會有成本增加的問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下= 圖式之簡單說明： 第1A〜1D圖繪示的是習知一種積體電路之靜電放電保 護電路的製造流程剖面圖；以及 第2A〜2E圖繪示的是依照本發明一較佳實施例的一種 積體電路之靜電放電保護電路的製造流程剖面圖。 圖式之標號說明： 10、50 :半導體基底 12、52 :隔離結構 Η、54 :元件區 16、56 :保護電路區 18、20、58、60 :金氧半電晶體 (誚先閱讀背面之注意事項再填寫本頁) 丨裝- -so 豫 本紙張尺度適用中國國家標準（CNS ) Λ4说彳Μ 210Χ 297公垃） .1 25twf.doc/006 A7 Η 7 五、發明説明（jr) 22、30、62、70 :閘氧化層 24、32、64、72 :多晶矽層 26、34、66、74 :間隙壁 28、36、36a、68、76、76a :源極/汲極區 38、39、40、41、78、79、80、81 :金屬矽化物層 42、44、82 :光阻層 奮施例 請參照第2A〜2E圖，第2A~2E圖繪示的是習知一種積 體電路之靜電放電保護電路的製造流程剖面圖。 首先請參照第2A圖，提供一半導體基底50,在半導體 基底50上形成隔離結構52以界定出元件區54及保護電路 區56，其中隔離結構52例如爲淺溝渠隔離結構或場氧化 層。並且，在元件區54及保護電路區56中分別形成金氧 半電晶體58與60。金氧半電晶體58包括閘氧化層62、多 晶矽層64、間隙壁66及淡摻雜汲極區結構(Lightly Doped Drain ;簡稱LDD)之源極/汲極區68(例如包括N+離子摻雜 區與N-離子摻雜區）。以及，金氧半電晶體60包括閘氧化 層70、多晶矽層72、間隙壁74及LDD結構之源極/汲極區 76(例如包括N+離子摻雜區與N-離子摻雜區）。 接著請參照第2B圖，進行自行對準金屬矽化物製程， 以同時在多晶矽層64、72及源極/汲極區68、76上分別形 成一層金屬矽化物層78、79、80與81。 再來請參照第2C圖，形成一層光阻層82同時覆蓋元 件區54及保護電路區56中之源極/汲極區76上之部分金 本紙張尺度適用中國國家梂準（CNS ) Λ4蚬格（210'χ29ϋ1 I'---------—裝------訂------' 線 (誚先閱讀背面之注意事項再填寫本頁) 經濟部中央標率局貝工消费合作社印袈 4 I 25twf.doc/006 A7 H7 五、發明说明（& ) :屬矽化物層81，其中覆蓋於部分金屬矽化物層81上之光 阻層82，其與多晶矽層72之距離約爲2微米。之後，例如 以乾蝕刻的方式去除未被光阻層44覆蓋之金屬矽化物層 41，直到暴露出源極/汲極區76與多晶矽層72爲止。 然後請參照第2D圖，以上述光阻層82與間隙壁74爲 罩幕，例如使用能量約爲50~200Kev、摻雜劑量約爲 1E14-1E16原子/平方公分之硼（Boron)離子，於暴露出之源 極/汲極區76下植入P+離子，以形成如圖所示P-N-P之基 納(Zener)二極體之結構。 接著請參照第2E圖，繼續以光阻層82爲罩幕，去除 間隙壁74。然後於暴露出之源極/汲極區76中植入濃度較 濃的離子(N+離子），以消除源極/汲極區76之N-離子摻雜 區，形成濃摻雜之源極/汲極區76a。隨後去除光阻層84。 接著，進行後續的步驟，以完成積體電路的製造，然 而此後續製程爲習知此技藝者所熟知，無關本發明之特 徵，故此處不再贅述。 本發明係於積體電路之靜電放電保護電路中，形成有 一基納二極體之結構，例如P-N-P或N-P-N之結構如第2 圖所示，其可經由控制N+或P+濃度來達到所要求的觸發 電壓値。亦即，經由降低觸發電壓値，來達到保護在高積 集度時之薄閘氧化層的功能。另一方面，低的觸發電壓， 其功率損耗也較低，相對地所產生的熱效應也較低，使得 較薄的閘氧化層也能免於受到ESD的傷害，因此ESD的保 護效能也更佳。另外，一般基納二極體的導通電壓約在4 I 25twf.doc / 006 A7 B7 V. Description of the Invention (/) The present invention relates to an electrostatic discharge (ESD) protection circuit for integrated circuits, and in particular, it relates to a circuit that is at the same time as its internal circuit After the manufacturing is completed, there is no need to add an additional photomask to complete the manufacturing method of the electrostatic discharge protection circuit of the ESD implantation and the Kener breakdown implantation. During the manufacture of integrated circuits (1C) such as dynamic random access memory (DRAM), static random access memory (SRAM), or after the chip is completed, electrostatic discharge events are often the main cause of damage to integrated circuits Therefore, we usually make an electrostatic discharge protection circuit in-house to avoid damage to the integrated circuit due to external static electricity. For example, a human walking on a carpet can detect a static voltage of about several hundred to several thousand volts when the relative humidity (RH) is high, and can detect an approximate band when the relative humidity is low. There is a static voltage of more than 10,000 volts. When these charged bodies come into contact with the wafer, they will discharge to the wafer, which may cause the wafer to fail. For the most common complementary metal-oxide-semiconductor (CMOS) process technology, the problems caused by electrostatic discharge events are particularly serious. Therefore, in order to prevent the electrostatic discharge from damaging the wafer, various kinds of software and hardware for preventing electrostatic discharge have been developed. The most common practice is to use hardware to prevent electrostatic discharge. That is, an electrostatic discharge protection circuit is designed between the internal circuit and each pad to protect its internal circuit. At present, the problem of electrostatic discharge has become one of the main reasons for the failure of deep submicron integrated circuits. Therefore, how to effectively improve the efficiency of electrostatic discharge protection circuits is urgently expected by the industry. In addition, because the formation thickness of the gate oxide layer shrinks synchronously with the process accumulation degree, the breakdown voltage of the gate oxide layer will gradually approach the source electrode / 3 This paper is applicable to the Chinese family standard (CNS) / \ 4 ^ (2 丨 OX297 Male —? --------- " -Packing ------ Order ------ Taste (诮 Read the notes on the back before filling this page) The Central Standards Bureau of the People ’s Republic of China only prints the f cooperatives ’seals ^ The Central Bureau of Standards and Construction Bureau ’s β industrial consumption cooperatives’ seals ^ 4 1 25twf.d〇c / 006 A? B7 V. Description of the invention Voltage, or even lower, the original ESD protection circuit design efficiency will be greatly reduced. In addition, the internal circuit is mostly designed according to Minimum Design Rules and is not properly designed (such as the contact window to the edge of the diffusion area and A large space is required from the contact window to the edge of the gate) to resist the huge electrostatic discharge transient current ('Transient Current'), which makes the wafer extremely susceptible to electrostatic discharge damage under high accumulation conditions. Therefore, the previous ESD The protection circuit uses a coupled diode or a coupled metal-oxide half-element To achieve this, due to the large power consumption in this method, it cannot withstand large ESD stress. When the thickness of the gate oxide layer is reduced, the breakdown voltage of the gate oxide layer is also reduced simultaneously. The performance of traditional ESD protection circuits will be greatly reduced at the time of the collapse. Please refer to Figures 1A ~ 1D, which shows a cross-sectional view of the manufacturing process of an electrostatic discharge protection circuit of a conventional integrated circuit. 1A, a semiconductor substrate 10 is provided. An isolation structure 12 is formed on the semiconductor substrate 10 to define an element region 14 and a protection circuit region 16. The isolation structure 12 is, for example, a shallow trench isolation structure or a field oxide layer. Metal oxide semiconductors 18 and 20 are formed in region 14 and protection circuit region 16, respectively. Metal oxide semiconductors 18 include a gate oxide layer 22, a polycrystalline silicon layer 24, a spacer 26, and a lightly doped drain region structure (Lightly Doped Drain structure). ; Abbreviated as LDD) source / drain region 28 (including N + ion-doped region and N-ion-doped region). And the metal-oxide semiconductor transistor 20 includes a gate oxide layer 30, a polycrystalline silicon layer 32, a spacer 34, and LDD structure Source / drain region 36 (including N + ion-doped region and N- ion-doped region). 4 This paper size is applicable to Chinese National Standard (CNS) Λ4 Regulations (210 × 297ϋ _ * ^… — --- Γ-- -^-装 ------ Order ------ 瘃 yf, (诮 Read the precautions before filling in this N) 4125twf.doc / 〇〇6 A7 B7 V. Description of the invention (>) Next, referring to FIG. 1B, a self-aligned metal silicide process (Salidde) is performed to simultaneously form a metal silicide layer 38, 39 on the polycrystalline silicon layers 24, 32 and the source / drain regions 28, 36, respectively. , 40 and 41. Please refer to FIG. 1C again, and form a photoresist layer 42 to cover and expose and develop and etch out the metal silicide layer 40 and part of the metal sand layer 41 in the device region 14 and the protection circuit region 16, and the metal sand layer is covered in part The photoresist layer 42 on the compound layer 41 is about 2 micrometers away from the polycrystalline silicon layer 32. Thereafter, the metal silicide layer 41 not covered by the photoresist layer 42 is removed by dry etching until the source / drain region 36 is exposed. Then referring to FIG. 1D, the new photoresist layer 44 is used as a mask, and the spacer 34 is removed. A more concentrated ion (eg, N + ion) is implanted into the exposed source / drain region 36 to eliminate the N-ion doped region of the source / drain region 36 and form a heavily doped source. / Drain region 36a. Subsequently, the photoresist layer is removed at 44 °. Then, the subsequent steps are performed to complete the fabrication of the integrated circuit. However, this subsequent process is well known to those skilled in the art and has nothing to do with the features of the present invention, so it will not be repeated here. According to the above manufacturing process, it is known that the manufacturing of the electrostatic discharge protection circuit of the integrated circuit is completed at the same time as its internal circuit, and no additional process steps are required to complete. Although the structure of the conventional electrostatic discharge protection circuit has a thick N-ion miscellaneous region, it can reduce the high junction resistance and obtain a uniform power dissipation. However, it cannot reduce the junction breakdown voltage. Voltage), which is not conducive to protecting internal components with gate oxide thicknesses below 35 angstroms. 5 This paper size is applicable to China National Standards (CNS Ｍ 心 弟 台 (210 × 29λ) > ^) ------------ (Read the precautions on the back before filling out this page} 1¾ ·· iM ----. Printed by the Shellfish Consumer Cooperative of the Central Provincial Bureau of Economic Affairs, Ministry of Economic Affairs and Economics 4 1 25twt.doc / 006 A7 B7 Therefore, the purpose of the present invention is to provide a method for manufacturing an electrostatic discharge protection circuit of an integrated circuit, so as to avoid that a thin oxide layer at a high accumulation degree cannot resist a huge electrostatic discharge transient current, and the wafer is susceptible to electrostatic discharge. In order to achieve the above and other objectives, the present invention provides a method for manufacturing an electrostatic discharge protection circuit, which is manufactured simultaneously with its internal circuit, and can complete ESD implantation and Kina crash implantation without adding an additional photomask. Step, and by controlling the concentration of N + or P + to achieve the required trigger voltage 使其, so that the trigger voltage is low and the power loss is low, in order to achieve the function of protecting the thin gate oxide layer at a high accumulation level, and there will be no Increased costs In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below with reference to the preferred embodiments and the accompanying drawings as follows: Figures 1A to 1D show cross-sectional views of the manufacturing process of an electrostatic discharge protection circuit of a conventional integrated circuit; and Figures 2A to 2E illustrate static electricity of a integrated circuit according to a preferred embodiment of the present invention. A cross-sectional view of the manufacturing process of the discharge protection circuit. Symbols of the drawings: 10, 50: semiconductor substrate 12, 52: isolation structure Η, 54: element area 16, 56: protection circuit area 18, 20, 58, 60: metal oxide Semi-transistor (诮 Please read the notes on the back before filling in this page) 丨 Installation--so The paper size of this paper applies the Chinese National Standard (CNS) Λ4 said 彳 210 × 297 male waste. 1 25twf.doc / 006 A7 Η 7 V. Description of the invention (jr) 22, 30, 62, 70: gate oxide layers 24, 32, 64, 72: polycrystalline silicon layers 26, 34, 66, 74: spacers 28, 36, 36a, 68, 76, 76a : Source / drain regions 38, 39, 40, 41, 78, 79, 80, 81: metal silicide layers 42, 44 82: Photoresist layer Example Please refer to Figures 2A to 2E. Figures 2A to 2E show cross-sectional views of the manufacturing process of a conventional electrostatic discharge protection circuit of an integrated circuit. First, referring to FIG. 2A, a semiconductor substrate 50 is provided, and an isolation structure 52 is formed on the semiconductor substrate 50 to define an element region 54 and a protection circuit region 56. The isolation structure 52 is, for example, a shallow trench isolation structure or a field oxide layer. Further, metal oxide semiconductors 58 and 60 are formed in the element region 54 and the protection circuit region 56, respectively. The metal-oxide semiconductor transistor 58 includes a gate oxide layer 62, a polycrystalline silicon layer 64, a spacer 66, and a source / drain region 68 (for example, N + ion doping) of a lightly doped drain structure (LDD). Region and N-ion doped region). Also, the metal-oxide semiconductor transistor 60 includes a gate oxide layer 70, a polycrystalline silicon layer 72, a spacer 74, and a source / drain region 76 of the LDD structure (for example, including an N + ion doped region and an N-ion doped region). Next, referring to FIG. 2B, a self-aligned metal silicide process is performed to form a metal silicide layer 78, 79, 80, and 81 on the polycrystalline silicon layers 64, 72 and the source / drain regions 68, 76, respectively. Please refer to FIG. 2C again to form a photoresist layer 82 to cover both the element region 54 and the source / drain region 76 in the protection circuit region 56 at the same time. The paper size of the paper is applicable to the Chinese National Standard (CNS) Λ4 蚬Grid (210'χ29ϋ1 I '----------------------- Order ------' line (诮 Please read the precautions on the back before filling this page) Rate Bureau Shellfish Consumer Cooperatives Co., Ltd. 4 I 25twf.doc / 006 A7 H7 V. & Description of Invention: It is a silicide layer 81, which covers a photoresist layer 82 on a part of the metal silicide layer 81, and The distance between the polycrystalline silicon layer 72 is about 2 micrometers. Then, the metal silicide layer 41 not covered by the photoresist layer 44 is removed by dry etching, for example, until the source / drain region 76 and the polycrystalline silicon layer 72 are exposed. Please refer to FIG. 2D, using the photoresist layer 82 and the spacer 74 as a mask, for example, using boron ions with an energy of about 50 to 200 Kev and a doping dose of about 1E14-1E16 atoms / cm 2 to expose P + ions are implanted under the source / drain region 76 to form a structure of a Zener diode of PNP as shown in the figure. Then refer to Section 2E. , Continue to use the photoresist layer 82 as a mask and remove the spacer 74. Then, a more concentrated ion (N + ion) is implanted in the exposed source / drain region 76 to eliminate the source / drain region 76 The N-ion doped region forms a heavily doped source / drain region 76a. The photoresist layer 84 is then removed. Next, the subsequent steps are performed to complete the fabrication of the integrated circuit, but this subsequent process is conventional The person skilled in the art is familiar with the features of the present invention, so it will not be repeated here. The present invention is in the electrostatic discharge protection circuit of the integrated circuit, and has a structure of a kina diode, such as the structure of PNP or NPN As shown in Figure 2, it can achieve the required trigger voltage P by controlling the concentration of N + or P +. That is, by reducing the trigger voltage 値, it can achieve the function of protecting the thin gate oxide layer at high accumulation. Another In terms of low trigger voltage, its power loss is also low, and the thermal effect is relatively low, so that the thinner gate oxide layer can also be protected from ESD damage, so the protection performance of ESD is better. , General turn-on of kina diode The voltage is about
Ir---*-----^ 1 裝------訂------' ^ (諳先閱讀背而之注意事項再填寫本頁) 經潢部中央標率局員工消费合作社印狀 本紙張尺度適用中國國家榡導（CNS ) Λ4规格（210X 297公# ) 4 I 25twf.doc/006 B7 五、發明説明（？） HOV左右，相較於習知ESD保護電路的觸發電壓在 10〜15V左右，本發明之ESD保護電路有更佳的保護效果。 此外，本發明之靜電放電保護電路的製造方法，係與 其之內部電路同時製造完成，無須增加額外光罩來完成 ESD植入與基納崩潰植入，因此不會有成本增加的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 *n L^i - 11 —il- L I 士ϊ/ I I :1 *_ n - - 1:1 w冬 {邡先閱讀背而之iif事項再填寫本頁)Ir --- * ----- ^ 1 Pack ------ Order ------ '^ (谙 Read the precautions before filling in this page) Staff of the Central Standards Bureau of the Ministry of Economics and Decoration Consumer Cooperative Copies The size of this paper applies to the Chinese National Guide (CNS) Λ4 specification (210X 297 public #) 4 I 25twf.doc / 006 B7 V. Description of the invention (?) About HOV, compared with the conventional ESD protection circuit The trigger voltage is about 10 ~ 15V, and the ESD protection circuit of the present invention has better protection effect. In addition, the manufacturing method of the electrostatic discharge protection circuit of the present invention is completed at the same time as its internal circuit, and there is no need to add an additional photomask to complete the ESD implantation and the Kina crash implantation, so there is no problem of increased cost. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. * n L ^ i-11 —il- L I 士 ϊ / I I: 1 * _ n--1: 1 w Dong (邡 read the iif matters first and then fill out this page)
M 經漭部中央標隼局只工消费合作社印製 度 4 Λ VI/ 5 ΝM Printed by the Central Standards Bureau of the Ministry of Economic Affairs, only printed by consumer cooperatives 4 Λ VI / 5 Ν