經濟部中央標準局貝工消费合作社印« A 7 _______ B7 五、發明説明（i) 本發明係有關一種在不同電位階（level)之工作電壓 (operating voltage)下操作之混合電壓裝置（mixed voltage device) ’特別有關於一種用於不同電壓源間之靜電保護裝 置（ESD protection device for different power supply)。 在積體電路(ICs)的應用上，導艘、半導體及絕緣層等 材料已被廣泛使用，而薄膜沈積（Thin Film Deposition)、 微影製程（photolithography)、及姓刻程序（etching)則為主 要之半導體技術》 其中薄膜沈積，即是將上述各材料分層沈積於待製晶 圓（wafer)表面，而微影製程則是複製（replicate)所欲形成之 元件或電路圖案，並透過蝕刻步驟，將該些圖案轉移至待 製晶圓表面各層以形成内部半導體元件如電晶體或電容 等。此外為避免水氣、鹼金屬離子的侵入或機械性刮傷， 必須另沈積一護層（passivation layer)以保護前述積艘電路 結構，且尚須定義出作為輸出/入(input/output)用之金屬錄 墊（metal pad)區之範圍，並以蝕刻步驟挖開護層，露出金 屬鲜整表面，方能進行最後之構裝（packaging)工作。 然而在前述所完成之半導體裝置中，靜電放電(ESD : electrostatic discharge)經常在乾燥環境下因碰觸帶靜電體 而自晶片之輸出/入墊(I/O pad)侵入，造成積髏電路損傷。 尤其在進入極大型積體電路(ULSI)世代以後，例如使 用0.2#m以下之深次微米製程所形成的半導體裝置，如 CMOS ICs，其薄閘極氧* 化層（thin gate oxide)、短通道（short channel length)、和淺接面（shallow junction)等結構特徵， 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公嫠） -----r---I — i. - (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央摞率局貝工消费合作社印« A7 _B7__ 五、發明説明（2 ) 或者是淡摻雜(LDD)和金屬石夕化物擴散(salicided diffusion) 技術的運用，均嚴重衰減了電晶體之抗ESD能力，且影響 其對靜電放電之可靠度問題，例如，前述製作之電晶體元-件因具有容易破裂（rupture)之薄閘極氧化層（thin gate oxide)，因此對高電壓放電（high voltage discharges)極為敏 一般靜電放電引起電子元件失效者可分為電壓型損 傷和電流型損傷，而依據人體模型，高靜電電壓可能源自 於人體碰觸到積體電路接腳，其可能產生超過2000V之電 荷並以較長期間之高電流脈衝型態出現；另依據機器模 型，高靜電電壓亦可能來自積體電路接腳與不良接地導 體，如測試機台之接觸，其則能以較短期間之高電壓脈衝 型態出現。若依人體模型設計靜電放電保護結構時，其ESD 值需高達4000V，而若依機器模型設計靜電放電保護結構 時，其ESD值則約500V。 目前有關靜電放電保護結構，大抵係利用保護電路之 MOS電晶體導通(turn on)機制和MOS電晶體崩潰-跳回機 制兩種，其中電晶體導通(turn on)機制係以厚氧化型電晶 體閘極連接輸出/入墊，因此以導通通道臨限電壓值為其特 徵；而電晶艘崩溃-跳回機制係以薄氧化型電晶體汲極連 接輸出/入墊，閘極則與源極連接，因此以電晶體崩溃電壓 值為其特徵》 前述靜電保護裝置係適用於單一電壓源系統（single voltage system)之設計，然而目前超大型（VLSI)或極大型 4 本紙张尺度適用中囷固家標準（CNS ) A4说格（210X297公釐） (請先閲讀背面之注項再填寫本頁}Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives «A 7 _______ B7 V. Description of the Invention (i) The present invention relates to a mixed voltage device that operates at operating voltages of different potential levels device) 'Especially related to an ESD protection device for different power supply. In the application of integrated circuits (ICs), materials such as guide ships, semiconductors, and insulation layers have been widely used, while Thin Film Deposition, photolithography, and etching are The main semiconductor technology "Among them, the thin film deposition is to deposit the above materials in layers on the wafer surface, and the lithography process is to replicate the desired element or circuit pattern and etch through In step, the patterns are transferred to each layer on the surface of the wafer to be formed to form internal semiconductor elements such as transistors or capacitors. In addition, in order to avoid the intrusion of water vapor, alkali metal ions, or mechanical scratches, a separate passivation layer must be deposited to protect the aforementioned building circuit structure, and it must be defined as an input / output function. The scope of the metal pad area, and the protective layer is excavated in an etching step to expose the fresh metal surface before the final packaging can be performed. However, in the completed semiconductor device, electrostatic discharge (ESD: electrostatic discharge) often invades from the I / O pad of the wafer due to touching the electrostatic body in a dry environment, causing damage to the cross-section circuit. . Especially after entering the ultra large integrated circuit (ULSI) generation, such as semiconductor devices formed using deep sub-micron processes below 0.2 # m, such as CMOS ICs, their thin gate oxide layers (thin gate oxide), short Structural features such as short channel length and shallow junction. This paper size applies to China National Standard (CNS) A4 specification (210X297 cm) ----- r --- I — i.- (Please read the notes on the back before filling out this page) Order the seal of the Bayer Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs «A7 _B7__ V. Description of the invention (2) Or lightly doped (LDD) and metal oxide diffusion ( The use of salicided diffusion) technology has severely weakened the anti-ESD capability of the transistor and affected its reliability against electrostatic discharge. For example, the transistor elements made as described above have thin gates that are easily ruptured. Oxide layer (thin gate oxide), so very sensitive to high voltage discharges (high voltage discharges) General electrostatic discharge causes electronic component failure can be divided into voltage damage and current damage, and according to the human body model, high static electricity The voltage may be caused by the human body touching the pins of the integrated circuit, which may generate a charge of more than 2000V and appear in the form of a high current pulse for a long period of time; according to the machine model, high electrostatic voltage may also come from the integrated circuit If the pin is in contact with a poor ground conductor, such as a test machine, it can appear as a high-voltage pulse in a short period of time. If the electrostatic discharge protection structure is designed according to the human body model, its ESD value needs to be as high as 4000V, and if the electrostatic discharge protection structure is designed according to the machine model, its ESD value is about 500V. At present, there are two types of electrostatic discharge protection structures: the MOS transistor turn-on mechanism and the MOS transistor collapse-jump-back mechanism that use the protection circuit. The transistor turn-on mechanism is a thick oxide transistor. The gate is connected to the output / input pad, so it is characterized by the threshold voltage value of the conduction channel; the transistor crash-jumpback mechanism is connected to the output / input pad with a thin oxide transistor drain, and the gate is connected to the source Connection, so it is characterized by the breakdown voltage of the transistor. "The aforementioned electrostatic protection device is designed for a single voltage system. However, at present, VLSI or very large 4 paper standards are suitable for solid-state storage. Home Standard (CNS) A4 Grid (210X297mm) (Please read the note on the back before filling this page}
4}濟部中央標率局貝工消费合作社印掣 A7 B7 五、發明説明（3 ) (ULSI)積體電路晶片之工作電壓則隨著半導體製造技術的 進步及節約能源之要求，而有逐漸降低之趨勢，因此，在 各數位電子元件間產生不同電位階之介面電壓已是無法 避免的問題，再者，混合電壓也被應用到許多的電路型態 中’其特徵是於不同的電路方塊（sections of the circuit)中 使用不同的工作電壓，例如類比-邏輯混合電路之特用 IC(ASIC : application specific integrated circuit)的 I/O 電 路和核心邏輯電路(core logic)，或者是嵌入式動態隨機存 取記憶體（embedded DRAM)等。 若以目前產品規格為例，典型常見於數位電子系統中 之工作電壓為5伏特，但由於降低工作電壓可減少電力消 耗及提昇性能，因此’目前市場上已同時有採用3.3伏特 及2.5伏特（甚或1.8伏特）工作電壓之電子元件出現。例如 在電腦系統中，此邏輯電路可以是一系統特用晶片 (application specific 1C ’· ASIC)，其包括核心邏輯（〇〇代 logic)及複數個輸出入電路，核心邏輯需透過輸出入電路來 與外部電路電性連接’但該些外部電路則各自具有相對應 的工作電壓，諸如，工作電壓2.5伏特之微處理器（cpu)， 工作電壓3.3伏特之靜態隨機存取記憶體（sram)，或者工 作電壓5伏特之動態隨機存取記憶體(DRAM)。 其中為了提供不同電壓源間之ESD電流導通路徑，傳 統作法係於不同電壓源間設置一由雙向二極體串列模組 形成之靜電保護裝置，如美國第5616943號專利，其以第 1，2圖說明之。 本紙張尺度通用中國國家棣準（CNS ) A4規格（2丨0x297公釐） (锖先閲讀背面之注^'項再填寫本頁)4} A7 B7 printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 5.Invention (3) (ULSI) The operating voltage of integrated circuit chips has gradually increased with the advancement of semiconductor manufacturing technology and energy conservation requirements. As a result, it is an unavoidable problem to generate interface voltages of different potential levels between digital electronic components. Furthermore, mixed voltages have also been applied to many circuit types, which is characterized by different circuit blocks. (Sections of the circuit) use different operating voltages, such as I / O circuits and core logic (application specific integrated circuit) ICs for analog-logic hybrid circuits, or embedded dynamics Random access memory (embedded DRAM), etc. If the current product specification is taken as an example, the working voltage typically used in digital electronic systems is 5 volts, but because lowering the working voltage can reduce power consumption and improve performance, '3.3 volts and 2.5 volts have been used in the market at the same time ( Electronic components even at 1.8 volts) operating voltage. For example, in a computer system, this logic circuit may be a system-specific chip (application specific 1C '· ASIC), which includes core logic (00th generation logic) and a plurality of input / output circuits. The core logic needs to be transmitted through the input / output circuits. It is electrically connected to the external circuit, but each of these external circuits has a corresponding working voltage, such as a microprocessor with a working voltage of 2.5 volts, and a static random access memory (sram) with a working voltage of 3.3 volts. Or a dynamic random access memory (DRAM) operating at 5 volts. Among them, in order to provide an ESD current conduction path between different voltage sources, the traditional method is to set an electrostatic protection device formed by a bidirectional diode serial module between different voltage sources, such as US Patent No. 5616943, which is based on the first, Figure 2 illustrates this. The paper size is in accordance with China National Standards (CNS) A4 (2 丨 0x297 mm) (锖 Please read the note ^ 'on the back before filling this page)
—-IT 經濟部中央標率局負工消费合作杜_* A7 --------87 五、發明説明（4) 依據第1圓，輸出入電路於輸出入接墊提供一電壓 VIO，例如5V，核心邏輯電路則於核心邏輯電路接墊提 供電壓VCORE ’例如3_3V，其間則以雙向二極體串列模 組110、120隔絕，其中每一二極體如U1〜11η·、.121〜12n 之導通電壓約為0.7V。當ESD電壓循輸出入接墊侵入時， 即可於雙向二極想串列模組11〇、12〇形成導通路徑。 以一極體串列模組110為例，如第2囷所示之半導體 剖面圖，其係在- P型發基底100處形成多個㈣，在N 井内則於既定位置各別形成P+型接觸區和N+型接觸區， 如此構成等效二極體m〜lln，其中每—個二極艘如lu 之N(陰）極與下-個二極體112之？(陽）極可透過金屬線電 性連接，形成一二極體串列模組110，此時ESD電流即可 循VIO端向VC0RE端之導通路徑均勾分佈反之則可以 一極體串列模組120為導通路徑。然而上述結構之問題在 於ESD電流只沿著二極體之單一流向故使得導通路徑之 電流密度仍然偏高。 ~ 有鑑於此，本發明之目的即在於以串聯之雙載子電晶 體取代二極體，並利用雙載子電晶體之數個電流流向來均 勻分散ESD電流，降低導通路徑之電流密度。 為達成上述目的，本發明提供一種用於不同電壓源間 之靜電保護裝置，包括：兩不同電壓源端；及一雙向電晶 體串列模組，其與該兩不同電壓源端電性連接，且該雙向 電晶體串列模組由順向電晶體串列和反向電晶艘串列並 聯形成’其中該各電晶體串列由複數級電晶體構成，該順 本紙張尺度適用中困固家橾率（CNS ) M規格（21〇χ：297公釐} (請先閲讀背面之注意事項再填寫本I·}—-Industrial and consumer cooperation of Central Standards Bureau, Ministry of Economic Affairs, Du_ * A7 -------- 87 V. Description of the invention (4) According to the first circle, the input and output circuits provide a voltage VIO on the input and output pads. For example, 5V, the core logic circuit provides a voltage VCORE ', such as 3_3V, in the core logic circuit pads. In the meantime, it is isolated by two-way diode serial modules 110 and 120, where each diode is U1 ~ 11η ·. The on-state voltage of 121 ~ 12n is about 0.7V. When the ESD voltage intrudes through the input and output pads, a conduction path can be formed in the bidirectional bipolar tandem module 11 and 12. Take a polar tandem module 110 as an example. As shown in the second cross section of the semiconductor, a plurality of ridges are formed at the -P type hair base 100, and P + types are formed at predetermined positions in the N well. The contact area and the N + type contact area constitute equivalent diodes m to lln, where each of the two diodes is lu (N) and the next diode 112? The (positive) poles can be electrically connected through a metal wire to form a diode serial module 110. At this time, the ESD current can be distributed through the conduction path from the VIO terminal to the VC0RE terminal. Otherwise, a polar string mode can be used. Group 120 is a conduction path. However, the problem with the above structure is that the ESD current only flows along a single direction of the diode, so that the current density of the conduction path is still high. In view of this, the object of the present invention is to replace the diode with a series of bipolar transistor and use several current flows of the bipolar transistor to evenly disperse the ESD current and reduce the current density of the conduction path. In order to achieve the above object, the present invention provides an electrostatic protection device for use between different voltage sources, including: two different voltage source terminals; and a bidirectional transistor serial module, which is electrically connected to the two different voltage source terminals, And the bi-directional transistor series module is formed by the parallel transistor series and the reverse transistor series connected in parallel. 'Each of the transistor series is composed of a plurality of transistor grades. Furniture ratio (CNS) M specification (21〇χ: 297 mm) (Please read the notes on the back before filling in this I ·}
_ *1T 經濟部中央標準局貝工消费合作社印輩 A7 B7 五、發明説明（5 ) 向電晶體串列之連接關係為前一級電晶體之基極電性連 接至下一級之射極，每一級電晶體之集極則和最後一級電 晶體之基極共接至該兩電壓源之一，且該第一級電晶體之 射極電性連接該另一電壓源，至於該反向電晶體串列則具 有相同之連接關係，但其與系統電壓端之連接位置為反 向。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係顯示一傳統用於不同電壓源間之二極體串列 模組型靜電保護裝置示意圖。 第2圖係顯示一依據第1圖二極體串列模組型靜電保 護裝置之半導體剖面圓。 第3圓係顯示一依據第2圖部份二極體串列模組之電 流流向。 第4囷係為第3圖之電流-二極艘導通電壓之特性曲 線圖。 第5圓係顯示本發明之一實施例中，一用於不同電壓 源間之電晶體串列模組型靜電保護裝置示意圖。 第6圓係顯示一依據第5圖部份電晶體串列模組型靜 電保護裝置之半導體剖面圓》 第7圖係顯示一依據第6圖部份電晶體串列模組之電 流流向》 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -- (請先閲讀背面之注意事項再填寫本頁} tr. .V. 經璘部中央標準局貝工消费合作社印家 A7 __ ___B7_ 五、發明説明（6) 第8圊係為第7圖之電流-電晶體導通電壓之特性曲 線囷。 符號說明 10〜P+接觸區；20〜P+接觸區；30~N+接觸區；100〜 基底；110〜二極體串列模組型靜電保護裝置；120〜二極 體串列模組型靜電保護裝置；1U-lln〜二極體；121-12η〜二極體；VIO〜輸出入電壓源；VCORE〜核心邏輯電 壓源；200〜基底；210〜電晶體串列模組型靜電保護裝 置；220〜電晶體串列模組型靜電保護裝置；21卜21η〜雙 裁子電晶體；221-2211〜雙載子電晶體。 實施例 請配合第5圓並參閱第6圖，其顯示本發明之一實施 例中，一用於不同電壓源間之電晶體串列模組型靜電保護 裝置及其對應之半導體剖面圖。 首先依據第5圖，兩不同電壓源端VI、V2，係與一 雙向電晶想串列模組（bi-directional bipolar transistor assembly)電性連接，且該雙向電晶體串列模組由第一電晶 體串列210和第二電晶體串列220並聯形成。其中各電晶 體串列由複數級電晶體構成，如電晶體21 l~21n 、 221〜22η 。 其中，電壓源端VI、V2例如是系統特用晶片ASIC， 其包括核心邏輯(core logic)電壓VCORE或接地端VSS1， 及複數個輸出入電路電壓VI0或接地端VSS2，因此在雙 向電晶體串列模組兩端之電壓差(V1，V2)有可能是電源差 8 ^紙張尺度適用>國國家標準（CNS ) A4規格（210X297公釐厂 ^----C 裝-- -- (#先閲讀背面之注意事項再填寫本頁) ----|杯 經濟部中央標準局貝工消费合作社印掣 A7 B7 五、發明説明（7 ) (VCORE，VIO)或接地差（VSS1，VSS2)，也有可能是電源與 接地差，因此平時兩電壓源端VI、V2係透過雙向電晶體 串列模組之電晶體導通電壓隔絕，但當發生靜電放電事件 時，則形成導通路徑以導引（bypass)靜電放電電流。舉例 而言，當靜電作用到以電壓源端VI為基準點之保護線路 時，若電壓源端V2電性連接接地節點，則必須以電壓源 端V2為基準點來進行放電，所以保護裝置可提供一條由 VI通向V2的路徑。 接著請參閱第6圖，其顯示一依據第5圈部份電晶體 串列模組型靜電保護裝置如210之半導體剖面圖。首先基 底200為一半導體材質如矽（silicon )，而若係選擇PNP 雙載子電晶體串列，則可採用P型矽基底，而若為NPN雙 載子電晶體串列，則選擇N型矽基底。 其次利用一熱氧化製程，如區域氧化法(LOCOS)來形 成一場絕緣層（field insulator )，並藉該場絕緣層來隔離 出主動區（active area )，在主動區上則另以半導艘製程 如離子植入來形成多個N井，以及於N井内形成一較淺之 P井，接著即在P井内之既定位置形成P+型接觸區1〇， 和N井内之既定位置各別形成P+型接觸區20和型接觸 區30’如此即構成多個等效PNP雙載子電晶艘2u〜21n。 其中，該電晶艘串列模組210之連接關係為，前—級 電晶體如211之基極B ’係利用N+型接觸區3〇電性連接 至下一級之P+型接觸區20如212之射極E，每一級電晶 體之集極c則透過P+型接觸區ίο’和最後一級電晶艘 本纸張尺度適用中國國家標率（CNS ) A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) Ί1Τ- 經濟部中央搮率局貝工消费合作社印簟 Α7 Β7 五、發明説明（8) 之基極B透過N+型接觸區3〇而共接至該兩電壓源之一如 V2，且第〆級電晶體211之射極E另透過p+型接觸區20 而電性連接另一電壓源VI。其中，在基底上方之連接關 係可透過沈積之金屬連線進行連接。 比較前述傳統結構和本發明之實施例，並以電壓端VI 和接地端為例’如第3、4圏和第7、8圓所示，其中’ 第3圏係顯示一依據第2圖部份二極體串列模組之電流流 向II，第4圖則為第3圓之電流-二極體導通電壓之特性 曲線圓。以二極艘111為例，當有靜電放電事件發生時’ 大量之靜電電流II可能自P+型接觸區（陽極)侵入，尋PN 二極體之單一導通路徑而從N+型接觸區（陰極）流出至接 地端，因此上述結構之問題在於ESD電流僅沿二極體之單 一流向，使得導通路徑之電流密度仍然偏高。 反之，第7囷係顯示一依據第6圖部份電晶體串列模 組之電流流向’包括II、12、13，第8圖則為第7圖之 電流-電晶體導通電壓之特性曲線圖《以PNP電晶艘211 為例，當有靜電放電事件發生時，大量之靜電電流η可能 從電壓源端VI侵入射極Ε(ρ+型接觸區20)，而沿射_集 (E-C)回路形成電流12，其自Ρ+型接觸區1〇流出，另並 沿射-基(Ε-Β)回路形成電流13，其自（Ν+型接觸區3〇)流 出。因此依該結構’由於ESD電流之分佈更為均勻而分散， 故可降低導通路徑之電流密度。 因此依據本發明實施例之結果’除可提昇抗ESd能力 外’對於在正常操作下之雜訊免疫力’也因雙栽子電晶艘 本紙張尺度適用中國困家標準（CNS ) Α4规格（210X297公釐） -ΊΨ _ (清1ST赛肾c黃年奐疼_ * 1T Yiner A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Explanation of the invention (5) The connection relationship between the transistor in series is that the base of the transistor in the previous stage is electrically connected to the emitter in the next stage. The collector of the first-stage transistor and the base of the last-stage transistor are connected to one of the two voltage sources in common, and the emitter of the first-stage transistor is electrically connected to the other voltage source, as for the reverse transistor The series has the same connection relationship, but its connection position to the system voltage terminal is reversed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 It is a schematic diagram of a traditional diode serial module type electrostatic protection device used between different voltage sources. Fig. 2 shows a semiconductor cross-section circle of a diode tandem module type electrostatic protection device according to Fig. 1. The third circle shows the current flow of a diode serial module according to the second figure. The fourth line is a characteristic curve of the current-diode vessel on-voltage in FIG. 3. The fifth circle is a schematic diagram of a transistor series module type electrostatic protection device used between different voltage sources in one embodiment of the present invention. The 6th circle shows a semiconductor cross section of a transistor series module type electrostatic protection device according to Fig. 5 "The 7th circle shows a current flow direction of a transistor series module according to Fig. 6" Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm)-(Please read the notes on the back before filling out this page} tr. .V. Yinjia A7, Jiagong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs __ ___B7_ 5. Description of the invention (6) The 8th line is the characteristic curve of the current-transistor on-voltage of the 7th line in Figure 7. Symbol description 10 ~ P + contact area; 20 ~ P + contact area; 30 ~ N + contact area; 100 ~ Base; 110 ~ diode tandem module type electrostatic protection device; 120 ~ diode tandem module type electrostatic protection device; 1U-lln ~ diode; 121-12η ~ diode; VIO ~ output Voltage source; VCORE ~ core logic voltage source; 200 ~ substrate; 210 ~ transistor tandem module type electrostatic protection device; 220 ~ transistor tandem module type electrostatic protection device; 21 ~ 21η ~ double cut transistor; 221-2211 ~ Bipolar transistor. For the example, please match the fifth circle and refer to the second circle. FIG. 6 shows a transistor tandem module type electrostatic protection device and its corresponding semiconductor cross-section view according to an embodiment of the present invention. First, according to FIG. 5, two different voltage source terminals VI and V2 are electrically connected to a bi-directional bipolar transistor assembly, and the bi-directional transistor string module is composed of a first transistor string 210 and a second transistor string Column 220 is formed in parallel. Each transistor is composed of a plurality of transistors in series, such as transistors 21 l ~ 21n, 221 ~ 22η. Among them, the voltage source terminals VI and V2 are, for example, system-specific chip ASICs, which include core logic. (core logic) The voltage VCORE or the ground terminal VSS1, and a plurality of input / output circuit voltages VI0 or the ground terminal VSS2, so the voltage difference (V1, V2) between the two ends of the bidirectional transistor serial module may be a power difference of 8 ^ Paper Size Applicable> National Standard (CNS) A4 Specification (210X297 mm factory ^ ---- C Pack--(#Read the precautions on the back before filling this page) ---- | Cup Ministry of Economy Central Bureau of Standards, Shellfish Consumer Cooperatives, India, A7, B7 (7) (VCORE, VIO) or ground difference (VSS1, VSS2) may also be the difference between power and ground, so the two voltage source terminals VI and V2 are usually isolated by the on-voltage of the transistor of the bidirectional transistor series module. However, when an electrostatic discharge event occurs, a conduction path is formed to bypass the electrostatic discharge current. For example, when static electricity acts on a protection circuit with the voltage source terminal VI as a reference point, if the voltage source terminal V2 is electrically When the ground node is connected, the voltage source terminal V2 must be used as the reference point for discharging, so the protection device can provide a path from VI to V2. Next, please refer to FIG. 6, which shows a semiconductor cross-section view of a series-type transistor-type electrostatic protection device such as 210 according to part 5 of the transistor. First, the substrate 200 is made of a semiconductor material such as silicon, and if a PNP bipolar transistor series is selected, a P-type silicon substrate can be used, and if an NPN bipolar transistor series is selected, an N type is selected. Silicon substrate. Secondly, a thermal oxidation process, such as LOCOS, is used to form a field insulator, and the field insulation layer is used to isolate the active area. On the active area, another semi-conductive ship is used. A process such as ion implantation is used to form multiple N wells, and a shallower P well is formed in the N well, and then a P + type contact zone 10 is formed at a predetermined position in the P well, and P + is formed at a predetermined position in the N well. The type contact region 20 and the type contact region 30 'thus constitute a plurality of equivalent PNP bipolar transistor cells 2u ~ 21n. Among them, the connection relationship of the transistor module 210 is that the base B of the front-stage transistor such as 211 is electrically connected to the P + -type contact region 20 such as 212 by using the N + -type contact region 30. The emitter electrode E, the collector electrode c of each stage of the transistor is passed through the P + contact area ίο 'and the last stage of the transistor. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read first Note on the back, please fill in this page again.) Ί1Τ- Seal of the Central Labor Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative Association A7 B7 V. Description of the invention (8) The base B is connected to the two voltages through the N + contact area 30. One of the sources is V2, and the emitter E of the first-stage transistor 211 is electrically connected to another voltage source VI through the p + -type contact region 20. Among them, the connection above the substrate can be connected through the deposited metal connection. Compare the aforementioned conventional structure and the embodiment of the present invention, and take the voltage terminal VI and the ground terminal as examples, as shown in the 3rd, 4th and 7th and 8th circles, where the 3rd line shows a section based on the second figure The current flow direction of the bipolar tandem module II is shown in Figure 4. Figure 3 shows the circle of the current-diode on-voltage characteristic curve for the third circle. Take the diode 111 as an example, when an electrostatic discharge event occurs, a large amount of electrostatic current II may invade from the P + type contact area (anode), and seek a single conduction path of the PN diode from the N + type contact area (cathode). It flows to the ground terminal, so the problem with the above structure is that the ESD current flows only in a single direction of the diode, so that the current density of the conduction path is still high. In contrast, Figure 7 shows the current flow of some transistor series modules according to Figure 6 (including II, 12, 13, and Figure 8 is the current-transistor on-voltage characteristic curve of Figure 7). "Taking the PNP transistor 211 as an example, when an electrostatic discharge event occurs, a large amount of electrostatic current η may invade the emitter E (ρ + contact region 20) from the voltage source terminal VI, and the emission_set (EC) The loop forms a current 12, which flows out from the P + -type contact region 10, and also forms a current 13 along the emission-based (E-B) loop, which flows out from the (N + -type contact region 30). Therefore, according to this structure, since the ESD current distribution is more uniform and dispersed, the current density of the conduction path can be reduced. Therefore, according to the results of the embodiments of the present invention, in addition to improving the anti-ESd capability, the immunity to noise under normal operation is also applicable to the Chinese paper standard (CNS) A4 specification for the size of the paper. 210X297 mm) -ΊΨ _ (Qing 1ST match kidney c yellow year pain
經濟部中央標準局貝工消费合作社印繁 A7 B7 五、發明説明（9 ) 串列模組之設置而獲得改善。 又在選擇NPN雙載子電晶體的場合，則可以N型矽 基底為實施例，不需另形成N井，其餘除電性相反外，皆 為相同之配置。 此外本發明中所應用之物質材料，並不限於實施例所 引述者，其能由各種具恰當特性之物質和形成方法所置 換，且本發明之結構空間亦不限於實施例引用之尺寸大 小0 雖然本發明已以一較佳實施例揭露如下，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可做些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 --------f裝-- »» (請先閱讀背面之注意事項再填寫本頁) 、-β 本紙張尺度適用中國國家橾準（CNS) Α4規格（210Χ297公釐）Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, A7 B7 5. Description of the Invention (9) The arrangement of the serial module has been improved. In the case where an NPN bipolar transistor is selected, an N-type silicon substrate can be used as an example, and no additional N wells need to be formed. The rest are of the same configuration except for the opposite electrical properties. In addition, the material materials used in the present invention are not limited to those cited in the examples, they can be replaced by various substances and forming methods with appropriate characteristics, and the structural space of the present invention is not limited to the dimensions cited in the examples. Although the present invention has been disclosed in the following with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. -------- f Pack-»» (Please read the precautions on the back before filling this page), -β This paper size is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm)