TW404039B - The manufacture method of the electrostatic discharge (ESD) protection circuit in integrated circuit - Google Patents

Abstract

A manufacture method of the electrostatic discharge (ESD) protection circuit in the integrated circuit, which is manufactured and completed with its inner circuit on the same time without adding extra photomask and process step, one only needs to change the dopant source to make it have the diode structure with P-N junction, and reduce effectively the trigger voltage value through controlling the concentration of the dopant so that the power loss is lowered. It has better protection performance of the punchthrough effect to avoid the damage of the electrostatic discharge (ESD) of the thin gate oxide at high degree of integration to achieve better effect of the electrostatic discharge (ESD) protection without the problem of increasing the cost at the same time.

Description

4 126twf.doc / 006 404039 at B7 V. Description of the Invention (/) The present invention relates to an electrostatic discharge (ESD) protection circuit for integrated circuits, and in particular, relates to a circuit that is simultaneously with its internal circuit. After the manufacturing is completed, there is no need to add additional photomasks and process steps to achieve a method for manufacturing an electrostatic discharge protection circuit with a low punch-through voltage. During the manufacture of integrated circuits (1C) such as dynamic random access memory (DRAM), static random access memory (SRAM), or after the chip is completed, electrostatic discharge events are often the main cause of damage to integrated circuits Therefore, we usually make an electrostatic discharge protection circuit in-house to avoid damage to the integrated circuit due to external static electricity. For example, a human walking on a carpet can detect a static voltage of about several hundred to several thousand volts when the relative humidity (RH) is high, and can detect an approximate band when the relative humidity is low. There is a static voltage of more than 10,000 volts. When these charged bodies come into contact with the wafer, they will discharge to the wafer, which may cause the wafer to fail. For the most common complementary metal-oxide-semiconductor (CMOS) process technology, the problems caused by the 'ESD event are particularly serious. Therefore, in order to prevent the electrostatic discharge from damaging the wafer, various methods for preventing electrostatic discharge have been developed. The most common practice is to use hardware to prevent electrostatic discharge. That is, an electrostatic discharge protection circuit is designed between the internal circuit (Circular) and each pad (Pad) to protect the internal circuit. At present, the problem of electrostatic discharge has become the cause of deep sub-micron integrated circuit failure.

I because of one. Therefore, how to effectively improve the performance of the electrostatic discharge protection circuit is urgently expected by the industry. Furthermore, the thickness of the gate oxide layer will increase with the process accumulation degree 3 (" Read the precautions for the back first, and then fill the {" page).

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# :; ίρ '部 屮 次 ^^-"', only h " · " ": ^ " 'India V paper redundant scale'! Ψ K (ΓΝίΓχ ^ Τΐίο'χ 297 ^ ¾ ')- 4 126twf.doc / 006 A7 —_________ B7___________ 5. The description of the invention (X) is increased and reduced, so that the breakdown voltage of the gate oxide layer will gradually approach the breakdown voltage of the source / drain interface, or even lower. At this time, the original ESD protection The efficiency of circuit design will be greatly reduced. In addition, most internal circuits are designed in accordance with Minimum Design Rules and are not properly designed (for example, sufficient space is required from the edge of the contact window to the diffusion region and from the contact window to the gate edge) to resist large electrostatic discharge transients. The state current (Transient Current) 'makes the wafer extremely vulnerable to electrostatic discharge damage in the case of high accumulation. Therefore, the previous ESD protection circuit was achieved by using a coupled diode or a coupled metal-oxide half-element. Due to the large power consumption in this method, it cannot withstand large ESD stress. When the thickness of the gate oxide layer is reduced, When the breakdown voltage of the gate oxide layer is also decreased simultaneously, if the breakdown voltage is reduced to about the breakdown of the metal-oxygen half junction, the performance of the traditional ESD protection circuit will be greatly reduced. Please refer to Figs. 1A to 1D. What Figs. 1A to 1D do not show is a sectional view of the manufacturing process of an electrostatic discharge protection circuit of a conventional integrated circuit. First, referring to FIG. 1A, a semiconductor substrate 10 is provided. An isolation structure 12 is formed on the semiconductor substrate 10 to define an element region 14 and a protection circuit region 16. The isolation structure 12 is, for example, a shallow trench isolation structure or a field oxide layer. Further, gold-oxide semiconductors 18 and 20 are formed in the element region 14 and the protection circuit region 16, respectively. The metal-oxide-semiconductor 18 includes a gate oxide layer 22, a polycrystalline silicon layer 24, a spacer 26, and a source / drain region 28 of a lightly doped drain structure (LDD) (for example, including an N + ion doped region). With N-ion doped regions). And, the metal-oxide semiconductor transistor 20 includes a gate oxide layer 30, a polycrystalline silicon layer 32, a spacer 34, and a source / drain region 36 of the LDD structure (for example, including an N + ion-doped region and an N-ion-doped region). 4 (" Read the precautions before filling in this page) _ _ 1T

A7 B7 Next, referring to FIG. 1B, a photoresist layer 38 is formed to cover the element region 14 °, and the spacer 34 of the gold gas transistor 20 in the protection circuit region 16 is removed, for example, by wet etching. Please refer to FIG. 1C. In the exposed source / drain region 36, relatively densely implanted ions (such as N + ions) are used to eliminate the source / drain region 36 & N-ion doped region. A heavily doped source / drain region 36a is formed. Referring to FIG. 1D, the photoresist layer 38 is removed. Next, a spacer 40 is formed on the sidewall of the metal-oxide semiconductor transistor 20 by, for example, a thermal oxidation method. Subsequently, a row-aligned metal silicide process (Sallclde) is performed to simultaneously form a layer of metal sands 42, 43, 44 and 45 on the polycrystalline silicon layer M'32 and the source / drain regions 28 and 36a, respectively. Next, the subsequent steps are performed to complete the fabrication of the integrated circuit, but the subsequent processes are well known to those skilled in the art, so they will not be repeated here. It is known from the above manufacturing process that the manufacturing of the electrostatic discharge protection circuit of the integrated circuit is completed at the same time as its internal circuit, and no additional process steps are required to complete it. Although the structure of the conventional electrostatic discharge protection circuit has a thick N-ion doped region, which can reduce the high junction resistance and obtain a uniform power dissipation, it cannot reduce the junction breakdown voltage, which is not conducive to protection below 35 Angstroms. The gate oxide thickness is an internal component. In view of this, the object of the present invention is to provide a method for manufacturing an electrostatic discharge protection circuit of an integrated circuit, so as to avoid that a thin oxide layer at a high accumulation degree cannot resist a huge electrostatic discharge transient current, which causes the wafer to be easily subjected to static electricity. The problem of electrical damage. In order to achieve the above and other objectives, the present invention provides an electrostatic discharge Baochuan, which disturbs ((he) Λ4 gauge (210x297g t) 404039 4126twf.d〇c / 〇〇6 A7 _________ _ _ B7_ V. Description of the invention ~ protection The circuit manufacturing method is completed at the same time as its internal circuit, without the need to add additional masks and process steps, only the implant source needs to be changed (the N + ion is changed to P + ion), and the concentration of the implant source is controlled to achieve the required The trigger voltage 値 is low, so that the trigger voltage is low and the power loss is low, to achieve the function of protecting the thin gate oxide layer at a high accumulation degree, and to improve the protection effect of the breakdown effect. At the same time, there is no cost increase problem. To make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings' as follows: Brief description of the drawings: Figures 1A to 1D FIG. 2 is a cross-sectional view showing the manufacturing process of an electrostatic discharge protection circuit of a conventional integrated circuit; and FIGS. 2A to 2D illustrate static electricity of an integrated circuit according to a preferred embodiment of the present invention. Cross-sectional view of the manufacturing process of the electrical protection circuit. Symbols of the drawings: 10, 50: Semiconductor substrate 12, 52: Isolation structure _ 14, 54: Element area 16, 56: Protection circuit area 18, 20, 58, 60: Gold Oxygen semitransistors 22, 30, 62, 70: gate oxide layers 24, 32, 64, 72: polycrystalline silicon layers 26, 34, 40, 66, 74: spacers 28, 36, 36a, 68, 76: source / Drain area (please read the precautions before filling in this page)

* 1T The size of this paper is Quzhou Zezhen pillow ((.NS) M Yue nuclear (210x297 public §) 404039 4 I 26twf.doc / 006 8 7 B7 V. Description of the invention (ir) 38, 82: Photoresist layer 42 , 43, 44, 45, 78, 79, 80, 81: For examples of metal silicide layers, please refer to Figures 2A to 2D. Figures 2A to 2D show the conventional electrostatic discharge protection circuits of integrated circuits. A cross-sectional view of the manufacturing process. First, referring to FIG. 2A, a semiconductor substrate 50 is provided, and an isolation structure 52 is formed on the semiconductor substrate 50 to define an element region 54 and a protection circuit region 56. The isolation structure 52 is, for example, a shallow trench isolation structure or A field oxide layer. In addition, metal oxide semiconductors 58 and 60 are formed in the element region 54 and the protection circuit region 56. The metal oxide semiconductor 58 includes a gate oxide layer 62, a polycrystalline silicon layer 64, a spacer 66, and light doping. Source / drain region 68 of the drain structure (LDD) (for example, including N + ion-doped region and N-ion-doped region). Also, the metal-oxide semiconductor transistor 60 includes a gate oxide layer 70, a polycrystalline silicon layer 72, and a gap. The wall 74 and the source / drain regions 76 of the LDD structure (for example, include N + ion-doped regions and N- ion-doped regions). Please refer to FIG. 2B for a self-aligned metal silicide process to form a metal silicide layer 78, 79, 80, and 81 on the polycrystalline silicon layers 64, 72 and the source / drain regions 68, 76, respectively. Referring again to FIG. 2C, a photoresist layer 82 is formed to cover the element region 54. Then, for example, the spacer 74 of the gold-oxygen semi-transistor 60 in the protection circuit region 56 is removed by wet etching to expose the source N-ion doped region of the pole / drain region 76. Next, refer to FIG. 2D, for example, using a boron ion with an energy of about 30 ~ 10OKev and a doping dose of about 1E14 ~ 1E16 atoms / cm2, 7 (Please read the back and pay attention to the item before filling in this page)

、 1T This paper is a standard test of Chuanxiong's leisure materials .: Pillow ((.NS) Λ4 Regulations (210X297) 404039 4l26twf.doc / 006 A7 V. Description of the invention (Handled) To the exposed source / drain P + ions are implanted in the N-ion doped region of the pole region 76 to eliminate the N-ion doped region and form the structure of the PN diode as shown in the figure. Then, the subsequent steps are performed to complete the integrated body. Circuit manufacturing, however, this subsequent process is well known to those skilled in the art and has nothing to do with the features of the present invention, so it will not be repeated here. The present invention is a structure of a PN diode in an electrostatic discharge protection circuit of an integrated circuit It can achieve the required trigger voltage 控制 by controlling the implantation source (N + or P + ion) concentration. That is, by reducing the trigger voltage 値, it can achieve the function of protecting the thin gate oxide layer at high accumulation. On the other hand, low trigger voltage has low power loss and relatively low thermal effect, so that the thinner gate oxide layer can also be protected from ESD damage. Therefore, ESD and breakdown effects are protected. Better performance. For 0.18 micron process, 35 Angstroms As for the internal components of the gate oxide layer thickness, the trigger voltage of the ESD protection circuit of the present invention is about 3 ~ 5V, compared with the conventional trigger voltage of about 10 ~ 15V, the ESD protection circuit of the present invention has more In addition, the manufacturing method of the electrostatic discharge protection circuit of the present invention is completed simultaneously with its internal circuit, without the need to add additional photomasks or other process steps, and only needs to change the implantation source (such as changing N + ions to P + ion), so there will be no cost increase problem. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. Various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. 8 (诮 Please read the precautions on the back before filling in this page)

、 1T paper ruler 戍 埤 川 屮 W1¾ is a harassment ((, NS) 8 4 sayings (2 丨 〇X 297 mm)

Claims (1)

Bulletin 404039 4 I 26twf.doc / 006 〇 // A8 B8 C8 D8 VI. Application for patent scope 1. A method for manufacturing an integrated circuit's electrostatic discharge protection circuit, which is manufactured simultaneously with its internal circuit on a semiconductor substrate An isolation structure has been formed thereon to define an element region and a protection circuit region, and a first metal-oxide-semiconductor and a second metal-oxide-semiconductor have been formed in the element region and the protection circuit region, respectively, the The first metal-oxide-semiconductor and the second metal-oxide-semiconductor each have a first source / drain region and a second source / drain region with a lightly doped drain structure, and the first source Both the electrode / drain region and the second source / drain region have a first conductivity type. The manufacturing method of the integrated circuit's electrostatic discharge protection circuit includes the following steps: performing a self-aligned metal silicide process; removing A spacer of the second metal-oxide-semiconductor in the protection circuit region to expose a lightly doped region of the second source / drain region; and implanting a dopant ion of a second conductivity type to expose Light doping of the second source / drain region Region to form the first conductivity type - of the second conductivity type diode structure. 2. The manufacturing method of the electrostatic discharge protection circuit according to item 1 of the scope of the patent application, wherein the isolation structure includes a shallow trench isolation structure. Printed by the Central Bureau of Standards, Ministry of Economic Affairs and Consumer Cooperatives (please read the precautions on the back before filling this page) 3. The manufacturing method of the electrostatic discharge protection circuit described in item 1 of the scope of patent application, where the first conductive When the type is N type, the second conductive type is P type. 4. The manufacturing method of the electrostatic discharge protection circuit according to item 1 of the scope of patent application, wherein when the first conductivity type is a P type, the second conductivity type is an N type. 5. As described in item 1 of the scope of the patent application, the paper size of 9 electrostatic discharge protection circuits is applicable to SB home ladder (CNS) A4 wash grid (210X297 mm) ^ 04039 A8 4126tWfd〇C / 〇 ° 6 C8 D8 6. The manufacturing method in the scope of the patent application, wherein the dopant ions of the second conductivity type include boron ions having an energy of about 30 to 10 OKev and a doping dose of about 1E14 to 1E1 atoms / cm 2. 6. The manufacturing method of the electrostatic discharge protection circuit according to item 1 of the scope of the patent application, wherein the method of removing the spacer of the second metal-oxide semiconductor includes a wet etching method. (Please read the notes on the back before filling out this page) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is in Chinese standard (CNS) A4 size (210X297 tolerance)