JP2004281843A - Static discharge protective element and semiconductor integrated circuit device equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a static discharge protective element with its resistance to static discharge improved by suppressing the local breakdown of the gate insulating film, and to provide a semiconductor integrated circuit device mounted with the same. <P>SOLUTION: The static discharge protective element comprises a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a pair of source/drain regions formed on the surface of the semiconductor substrate and arranged to sandwich the gate insulating film from both sides, and an impurity-doped conductor formed on the gate insulating film. A pair of side regions are provided near the source/drain regions and a central region is sandwiched between the side regions, and a gate electrode is provided wherein the impurity concentration level in the pair of side regions is lower than that in the central region. By using this design, partial depletion is prompted in the gate electrode for the moderation of local concentration of the gate current. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electrostatic discharge protection element and a semiconductor integrated circuit device including the same.
[0002]
[Prior art]
2. Description of the Related Art A large-scale semiconductor integrated circuit device (LSI) includes a protection element (electrostatic discharge protection element) for protecting an internal circuit from external peripheral devices connected to the LSI, the peripheral circuit, and static electricity discharged by a person who handles the peripheral circuit. Is provided.
[0003]
FIG. 7 is a schematic diagram of a typical internal circuit and a circuit including an electrostatic discharge protection element. The protection element 1 is generally connected to a signal line 7 connecting the OLE_LINK 1 PadOLE_LINK 13 connected to an external terminal and the internal circuit 5. In such a circuit, when a surge current that cannot be tolerated by the internal circuit 5 is applied to the signal line 7, the internal resistance of the protection element 1 is temporarily reduced, and the surge current is released to the ground via the protection element 1. The internal circuit 5 can be protected.
[0004]
FIG. 8 is a diagram for explaining an integrated circuit device using a CMOS inverter as an example of an element constituting an internal circuit. FIG. 8 is a cross-sectional view of the CMOS inverter, and a circuit diagram showing a connection between the CMOS inverter via the signal line 7 and the internal circuit 1 and the pad 3 and a connection between the CMOS inverter via the wiring 11 and another internal circuit 9. .
[0005]
The CMOS inverter inverts the signal input from Pad3 in a range from 0 V to the power supply voltage Vdd and transmits the inverted signal to another circuit. Here, the CMOS inverter includes an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) formed on a semiconductor substrate and a complementary field-effect transistor (CMOSFET) including a p-type MOSFET.
[0006]
The CMOSFET is generally formed on the surface of the silicon substrate 501. The n-type MOSFET and the p-type MOSFET of the CMOSFET are electrically isolated from each other by an element isolation region 503 formed on the surface of the silicon substrate 501.
[0007]
A p-type well region 505 is formed on the surface of the substrate 501 on which the n-type MOSFET is formed, and an n-type well region 514 is formed on the surface of the substrate 501 on which the p-type MOSFET is formed. The n-type MOSFET includes a pair of n-type source / drain regions 507, a gate insulating film 509 formed therebetween, and a gate electrode 511 made of n-type polysilicon or the like. The p-type MOSFET includes a pair of p-type source / drain regions 515, a gate insulating film 517 formed therebetween, and a gate electrode 519 made of p-type polysilicon or the like.
[0008]
The gate electrodes 511 and 519 of the two MOSFETs are mutually connected to the Pad 3 via the signal line 7. One of the source / drain regions 507 of the n-type MOSFET is connected to the ground. One of the source / drain regions 515 of the p-type MOSFET is connected to a power supply 523 and supplied with a power supply voltage Vdd. The other of the source / drain regions of the n-type MOSFET is connected to the other of the source / drain regions of the p-type MOSFET, and is connected to another circuit (further internal circuit) 9 via the signal line 11.
[0009]
In the CMOS inverter of FIG. 8, if the protection element 5 cannot release the surge voltage to the ground, the gate insulating films 501 and 517 of the CMOSFET are destroyed.
[0010]
Next, an example of the protection element 1 will be described with reference to FIG. In FIG. 9, the protection element 1 is shown in a cross-sectional view, and the connection between the protection element 1 and the Pad 3 or the internal circuit 5 is shown in a circuit diagram.
[0011]
The protection element 1 includes an n-type MOSFET. This n-type MOSFET is formed on the surface of a substrate 501 made of silicon or the like in which the element isolation region 503 and the p-type well 105 are formed. The n-type MOSFET includes a pair of source / drain regions 107, and a gate insulating film 109 and a gate electrode 111 formed on a channel region on the surface of the silicon substrate 501 sandwiched between the source / drain regions 107.
[0012]
The drain of the source / drain region 107 is connected to the signal line 7. The gate electrode 111 and the source are both grounded. In this case, when a surge exceeding the tolerance of the internal circuit 9 is applied to the signal line 7, the conduction between the source and the drain 107 of the protection element is conducted and the surge can be released to the ground.
[0013]
That is, since the gate electrode 111 is grounded, the resistance of the channel portion is high, and when a surge propagates to the signal line 7, a high electric field concentrates between the source region and the drain region, particularly near the drain. This high electric field causes impact ionization of electrons, and the generated holes flow toward the p-type well 105. Then, the potential of the p-type well 105 increases due to the resistance of the p-type well 105, and the parasitic bipolar transistor is turned on, so that conduction between the source and drain regions 107 is established. Thereby, the surge can be released to the ground, and the protection of the internal circuit 9 is realized.
[0014]
However, when a surge that the protection element 1 cannot withstand flows, the gate insulating film 109 is broken. As a result, the conduction between the drain region and the gate electrode 111 is always in a conductive state, and all signals on the signal line 7 are leaked to the ground as a leak current. Then, necessary signals do not reach the internal circuit 9. Therefore, the semiconductor integrated circuit device whose protection element has been destroyed cannot be used.
[0015]
With respect to the protection element, a technique has been proposed in which a low impurity region is provided in a drain region to allow more current generated by a surge to escape to a ground or a power supply line (see Patent Document 1). In addition, a technique has been proposed in which the concentration of the electric field only under the wiring contact in the source / drain region is reduced to thereby alleviate the electric field concentration at the time of applying a surge and improve the breakdown resistance against the surge (see Patent Document 2). However, these techniques cannot improve the surge resistance of the gate insulating film.
[0016]
[Patent Document 1]
JP-A-11-17022 [Patent Document 2]
JP-A-4-336463
[Problems to be solved by the invention]
In many cases, a MOSFET is used as the main element for the protection element 1. When the gate insulating film is broken by electrostatic discharge, the broken portion is often local. In particular, the frequency of local destruction is high at the ends of the gate insulating film near the source / drain regions (both ends in the channel length direction) and on the ends of the element isolation regions (both ends in the channel width direction). all right.
[0018]
An object of the present invention is to provide a semiconductor integrated circuit device provided with an electrostatic discharge protection element that suppresses such local breakdown of a gate insulating film and has resistance to electrostatic discharge.
[0019]
[Means for Solving the Problems]
In order to solve the above problems, a first aspect of the present invention is a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a pair of sources formed on the surface of the semiconductor substrate and sandwiching the gate insulating film from both sides. A drain region and a conductive region containing impurities formed on the gate insulating film, a pair of side regions near the source and drain regions, and a central region sandwiched between the side regions; A gate electrode having an impurity concentration in the side region lower than that in the central region.
[0020]
Further, a second aspect of the present invention is a semiconductor substrate, an element isolation region formed on the surface of the semiconductor substrate and having an end bordering the surface of the semiconductor substrate, and a gate insulating film formed over the semiconductor substrate and the boundary And a pair of source / drain regions formed on the surface of the semiconductor substrate and sandwiching the gate insulating film, and a conductor containing impurities formed on the gate insulating film. And a gate electrode having a partial region having an impurity concentration lower than that of the central region.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments and examples of the present invention will be described in detail with reference to the drawings. In the following description, the same components will be denoted by the same reference symbols, without redundant description. In addition, each drawing is a schematic diagram, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, when manufacturing an actual device, it is necessary to consider the following description and a known technique. Can be.
[0022]
(First Embodiment)
First, a protection element according to the first embodiment will be described with reference to a top view of FIG. 1 and cross-sectional views of FIGS. 2 (a) and 2 (b). Here, only the protection element (n-type MOSFET) will be described. The connection between the protection element 1 and the pad 3 and the internal circuit 5 in the semiconductor integrated circuit device is referred to the description in FIGS. 7 to 9, and redundant description will be omitted.
[0023]
FIG. 1 is a top view of the protection element according to the present embodiment. FIG. 2A shows an AA ′ cross section (gate length direction cross section), and FIG. 2B shows a BB ′ cross section (gate width direction cross section).
[0024]
In this embodiment, an explanation will be given using an n-type MOSFET which is an electron conduction type. This time, it was found that the frequency of local destruction of the gate insulating film 209 (located at the same position as the gate 211 in FIG. 1) in the region surrounded by the dotted line in FIG. 1 was high. That is, in the gate insulating film 209, the local destruction frequency is low at the end near the source / drain region 207 (both ends of the channel length L) and at the end of the element isolation region 203 (both ends of the channel width W). high. This is also due to the fact that the gate insulating film 209 is made thinner with the miniaturization of MOSFETs, and the resistance to electrostatic discharge is reduced.
[0025]
As shown in FIGS. 2A and 2B, an n-type MOSFET serving as a protection element is formed on one surface of a semiconductor substrate 213 made of silicon or the like. An element isolation region 203 such as STI (Shallow Trench Isolation) is formed on the surface of the semiconductor substrate 213. A region sandwiched between the element isolation regions 203 of the silicon substrate 213 is an expected n-type MOSFET region.
[0026]
A p-type impurity diffusion layer (well) 215 is formed in the expected n-type MOSFET region. A pair of n ⁺ -type source / drain regions 207 are formed on the p-type well 215, and a gate insulating film 209 and a gate electrode 211 are sequentially formed on a channel region sandwiched between them.
[0027]
Here, the gate electrode 211 is made of a polycrystalline silicon film to which an n-type impurity such as As is added. On the side walls and the like, n-type low impurity concentration regions 219 and 221 to which p-type impurities such as boron are added in addition to n-type impurities are formed.
[0028]
The low impurity concentration region 219 is formed on both sides of the gate electrode 211 from the source / drain region 207 so as to overlap with the source / drain region 207 (FIG. 2A). However, the low impurity concentration region 219 and the source / drain region 207 need not necessarily overlap. This is because when the gate length is reduced, the transistor is driven even if the source / drain region 207 is separated from the gate electrode 211.
[0029]
The low impurity concentration region 221 is formed on the boundary between the element isolation region 203 and the p-type well 215 of the silicon substrate 213 in the gate electrode 211 (FIG. 2B). That is, the low impurity concentration region 221 is formed so as to cover the end of the element isolation region 203 and the end of the silicon substrate 213 on both sides of the boundary.
[0030]
Such low impurity concentration regions 219 and 221 are formed by adding an n-type impurity to make the entire gate polycrystalline silicon 211 n ⁺ type and then forming a p-type impurity such as boron. It can be formed by selectively introducing into a position.
[0031]
For example, the ion implantation protective film 217 is formed on the upper surface of the gate electrode 211 at a position other than the position where the low impurity concentration region 221 is to be formed. Then, when p-type impurities are ion-implanted from the upper surface of the gate electrode 211, p-type impurities can be selectively introduced only into the low impurity concentration region 221. Further, by using this protective film 217, boron ions are implanted obliquely to the side surfaces of the gate electrode 211 (ions are implanted from the substrate surface so as to form an acute angle with respect to the side surfaces), so that the low impurity concentration region is formed. 219 can be formed.
[0032]
By this ion implantation step, the donor impurity concentration (n-type impurity concentration) in the ion implantation region of the gate electrode 211 is offset, and the effective impurity concentration decreases. When the MOSFET is a hole conduction type (p-type), the gate impurity type is an acceptor (p-type), and a donor-type impurity (n-type) is selectively ion-implanted into the low impurity concentration regions 219 and 221. .
[0033]
As a method of providing the low impurity concentration region 221 on the boundary with the element isolation region 203, impurities may be selectively separated between the low impurity concentration region 221 and other regions using a mask.
[0034]
As another means for providing the low impurity concentration region 219 on the gate side wall, a mask is formed on the gate electrode excluding the side wall, and this is used to selectively adjust the impurity and the concentration of the gate side wall and other gate regions. You may separate. For example, silicon nitride can be used for the ion implantation protection film 217. Note that the ion implantation protective film 217 is used for forming a low impurity concentration region, and may be left after use, or may be peeled off.
[0035]
Next, the functions of the low impurity concentration regions 219 and 221 will be described with reference to FIGS. FIG. 3A is a partial cross-sectional view in a gate width direction, and FIG. 3B is a partial cross-sectional view in a gate length direction. In FIG. 3A, an insulating film such as a gate sidewall insulating film and an interlayer isolation film is located on the side of the gate insulating film 209 and the gate electrode 211 above the source / drain region 207.
[0036]
First, according to the gate electrode 211 having no low impurity concentration region 219, as shown in the partial cross-sectional view of FIG. 3A, the end of the gate electrode 211 (FIG. The gate current flows through the circled part a)). As a result, the gate insulating film 209 is locally broken.
[0037]
Similarly, according to the gate electrode 211 having no low impurity concentration region 221, as shown in the partial cross-sectional view of FIG. The gate current starts to concentrate. As a result, the gate insulating film 209 (the portion circled in FIG. 3B) immediately above the element isolation region 203 is locally broken. According to the structure of the present embodiment, by providing the low impurity concentration regions 219 and 221, local destruction can be prevented.
[0038]
FIG. 4 shows the distribution of the electron current density (A / cm ⁻² ) at the lower end of the gate electrode (lower position near the gate insulating film). The horizontal axis in FIG. 4 indicates the direction from the central region of the gate electrode to the drain or source (μm). This distribution assumes a state in which a donor having an impurity concentration of N _D = 10 ²⁰ cm ⁻³ is present in the gate electrode, and most of the gate current is composed of the electron current. The gate width W was 20 μm, the gate length L was 0.4 μm, and the thickness of the gate insulating film was about 3 nm. Further, the gate voltage _Vg was set to 6V.
[0039]
Each data in FIG. 4 is (a) _ND = 10 ¹⁸ cm ⁻³ , (b) _ND = 5 × 10 ¹⁸ cm ⁻³ , (c) _ND = 1 × 10 ¹⁹ cm ⁻³ , (D) is N _D = 2 × 10 ¹⁹ cm ⁻³ , (e) is N _D = 4 × 10 ¹⁹ cm ⁻³ , (f) is N _D = 5 × 10 ¹⁹ cm ⁻³ , (g) is N _D = 7 × 10 ¹⁹ cm ⁻³ , (h) is data of N _D = 10 ²⁰ cm ⁻³ .
[0040]
From Figure 4, as to reduce the N _D of the gate sidewalls low impurity concentration region 219, the electron current density at the gate edge is seen to decrease. On the other hand, as to reduce the N _D of the gate sidewalls low impurity concentration region at the boundary of the gate region adjacent to the gate sidewalls low impurity concentration region (near about 0.165 (near about 35nm from the side wall)), gradually Current Current Density You can also see that goes up. Assuming that the width of the low impurity concentration region 219 on the gate side wall is specified, the width at which the source / drain diffusion layer 207 and the gate electrode 211 overlap is appropriate. This width can be calculated, for example, by the depth of the end of the source / drain region 207 on the gate electrode 211 side × 0.7.
[0041]
FIG. 5 shows the relationship between the impurity concentration (cm ⁻³ ) of the low impurity concentration region 219 in the gate electrode and the maximum value of the electron current density (A / cm ² ). As the impurity concentration of the low concentration region 219 decreases from 10 ²⁰ cm ⁻³ , the maximum value of the electron current density also decreases. However, when the impurity concentration of the low-concentration region 219 becomes 10 ¹⁹ cm ⁻³ or less, the maximum value of the electron current density starts to increase. This is because the electric field concentrates at the boundary between the low impurity concentration region 219 and the normal impurity concentration region, and the gate current also concentrates there.
[0042]
In order to improve the reliability, the upper limit of the concentration of the gate sidewall low impurity concentration region is about 7 × 10 ¹⁹ cm ⁻³ from FIG. The lower limit of the concentration is 1 × 10 ¹⁹ cm ⁻³ . This is the lowest value at about 1 × 10 ¹⁹ cm ⁻³ from FIG. 5. If the concentration is lower than this, the metallic properties of the gate electrode on the side are impaired, and the gate electrode functions as a gate electrode. This is because they may disappear. The term “approximately” added to the numerical value of the concentration includes a numerical range in which such a function works. It is considered that the same effect can be obtained even if the concentration of the low impurity concentration region is changed from 1 × 10 ²⁰ cm ^{−3 in the} central region.
[0043]
FIG. 6 shows a snapback characteristic of the protection element of this embodiment.
[0044]
Here, the gate width W was about 500 μm, the gate length L was about 0.3 μm, and the gate insulating film thickness was about 5 nm. Since the gate of the ordinary protection element is grounded, the characteristic shown by the broken line (Vg = 0) in FIG. In this case, since the resistance inside the protection element is reduced, the drain voltage becomes 8 V (Vt1). Thus, at the high voltage Vt1, the internal circuit may be broken before the protection element operates.
[0045]
Here, Vt1 is a voltage required to cause the parasitic bipolar transistor to transition to the ON state. That is, holes generated by impact ionization between the drain region and the substrate flow toward the substrate electrode, and at that time, a potential drop occurs between the substrate electrode and the channel, and the potential is formed in the source region / substrate / drain region. The parasitic bipolar transistor is turned on. Vt1 is a breakdown voltage required between the drain region and the substrate at this time.
[0046]
In the protection element according to the first embodiment (solid line (Vg floating) in FIG. 6), since the low concentration region 221 is provided in the gate region, the gate electrode on the channel region is in a semi-electrically floating state. is there. Therefore, as the potential of the channel region rises, the potential of the gate region on the channel region also rises due to capacitive coupling. As a result, Vt1 decreases as compared with the prior art. Therefore, it is possible to prevent local destruction of the gate electrode on the end of the element isolation region due to electrostatic discharge and to reduce Vt1.
[0047]
When the edge of the gate electrode is sufficiently rounded by oxidation after forming the gate, the low concentration impurity region 221 may be provided only on the element isolation region. Further, when a trench (groove) is formed in a semiconductor substrate by etching to form an element isolation region, if the Si region in the trench opening is sufficiently rounded by an oxidation process, only the gate sidewalls at the source / drain ends are formed. The low-concentration impurity region 219 can also be used.
[0048]
The embodiments of the present invention have been described above, but the present invention is not limited thereto, and various changes can be made within the scope of the invention described in the claims.
[0049]
Further, the present invention can be variously modified in an implementation stage without departing from the gist thereof.
[0050]
Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Further, components of different embodiments may be appropriately combined.
[0051]
【The invention's effect】
A protection element which promotes partial depletion of a gate electrode to reduce local concentration of a gate current and a semiconductor integrated circuit device including the protection element can be provided.
[Brief description of the drawings]
FIG. 1 is a plan view for explaining a protection element according to a first embodiment of the present invention.
FIG. 2 is a sectional view for explaining a protection element according to the first embodiment.
FIG. 3 is a cross-sectional view illustrating a protection element according to the first embodiment.
FIG. 4 is a sectional view for explaining characteristics of the protection element according to the first embodiment;
FIG. 5 is a characteristic diagram for explaining characteristics of the first embodiment.
FIG. 6 is a characteristic diagram showing a relationship between a drain voltage and a drain current according to the first embodiment.
FIG. 7 is a circuit diagram for explaining a conventional technique and the like.
FIG. 8 is a partial cross-sectional view and a circuit diagram for explaining a conventional internal circuit and the like.
FIG. 9 is a partial sectional view and a circuit diagram for explaining a conventional electrostatic discharge protection element and the like.
[Explanation of symbols]
1 ... protection element 3 ... pad (Pad)
5 internal circuit 7 signal line 9 other internal circuit 11 signal line 501 silicon substrate 503 element isolation region 505 p-type well 507 n-type source / drain regions 509, 517 gate insulating film 511 n-type gate electrode 513 p-type diffusion layer 514 n-type well 515 p-type source / drain region 519 ..P-type gate electrode 521 n-type diffusion layer 523 power supply voltage terminal 105 p-type well 107 n-type source / drain region 109 gate insulating film 111 n Type gate electrode 113 ··· p type diffusion layer 203 ··· element isolation region 207 ··· source / drain region 209 ··· gate insulating film 211 ··· gate electrode 213 ··· semiconductor substrate 215 ··· p Mold well 217 Ion implantation protection film 219, 221 ... low impurity concentration regions

Claims (5)

A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate,
A pair of source / drain regions formed on the surface of the semiconductor substrate, sandwiching the gate insulating film from both sides;
A pair of side regions in the vicinity of the source / drain regions and a central region sandwiched between the side regions, comprising a conductor containing impurities formed on the gate insulating film; A gate electrode having a lower impurity concentration in the region than the impurity concentration in the central region. 2. The electrostatic discharge protection device according to claim 1, wherein an impurity concentration of the pair of side regions is about 1 × 10 ¹⁹ cm ⁻³ or more and about 7 × 10 ¹⁹ cm ⁻³ or less. A semiconductor substrate;
An element isolation region formed on the surface of the semiconductor substrate and having an end portion bounding the surface of the semiconductor substrate,
A gate insulating film formed over the semiconductor substrate and the boundary,
A pair of source / drain regions formed on the surface of the semiconductor substrate and sandwiching the gate insulating film;
The semiconductor device includes a conductor containing impurities formed on the gate insulating film, and includes a partial region on the boundary and a central region on the semiconductor substrate, wherein an impurity concentration of the partial region is higher than an impurity concentration of the central region. An electrostatic discharge protection device comprising a low gate electrode. 2. The electrostatic discharge protection device according to claim 1, wherein the impurity concentration of the partial region is about 1 × 10 ¹⁹ cm ⁻³ or more and about 7 × 10 ¹⁹ cm ⁻³ or less. A semiconductor integrated circuit device comprising: the electrostatic discharge protection device according to claim 1; and an internal circuit connected to the electrostatic discharge protection device via a wiring.

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