412856 A7 45 1 8twl\d〇c/002 _B7________ 五、發明説明（I ) 本發明是有關於一種靜電放電（Electrostatic Discharge ;以下簡稱ESD)保護電路’且特別是有關於一種 可使多晶矽餍達到低阻抗及低傳播延遲功能’而且不會有 任何電流消散路徑縮短問題’進而達到增進ESD保護能力 之靜電放電保護電路的製造方法。 在積體電路（1C)例如動態隨機存取記憶體(DRAM)、靜 態隨機存取記憶體（SRAM)的製造過程中或是晶片完成 後，靜電放電事件常是導致積體電路損壞的主要原因’因 此我們通常都會順道在其內部製造一靜電放電保護電路’ 以避免因外來靜電而導致積體電路受到傷害（damaSe)。例 如在地毯上行走的人體，於相對濕度(RH)較高的情況下可 檢測出約帶有幾百至幾千伏的靜態電壓’而於相對濕度較 低的情況下則可檢測出約帶有一萬伏以上的靜態電壓。當 這些帶電體接觸到晶片時，將會向晶片放電’結果有可能 造成晶片失效。以目前最普遍的互補式金氧半（CMOS)製程 技術而言，靜電放電事件所產生的問題尤其嚴重。 於是，爲了避免靜電放電損傷晶片，各種防制靜電放 電的軟體與硬體便因應而生。最常見的習知作法是利用硬 體防制靜電放電，也就是在內部電路(Internal Circuit)與每 一焊墊（Pad)間，均設計一靜電放電保護電路以保護其內部 電路。 再者，由於閘氧化層之形成厚度隨著製程積集度同步 縮小的因素，使得閘氧化層的崩漬電壓將逐步逼近源極/ 汲極接面崩潰電壓，甚或更低，此時原來的ESD保護電路 (請先閲讀背面之注意事項再填寫本頁)412856 A7 45 1 8twl \ d〇c / 002 _B7________ V. Description of the Invention (I) The present invention is related to an electrostatic discharge (ESD) protection circuit ', and in particular, it relates to a method that can reduce polycrystalline silicon to a low level. Impedance and low propagation delay function 'and there will be no problem of shortening the current dissipation path', thereby achieving an electrostatic discharge protection circuit manufacturing method which improves the ESD protection capability. During the manufacture of integrated circuits (1C) such as dynamic random access memory (DRAM), static random access memory (SRAM), or after the chip is completed, electrostatic discharge events are often the main cause of damage to integrated circuits 'So we usually make an electrostatic discharge protection circuit inside it' to avoid damage to the integrated circuit due to external static electricity (damaSe). For example, a human body walking on a carpet can detect a static voltage of about several hundred to several thousand volts when the relative humidity (RH) is high, and can detect an approximate band when the relative humidity is low. There is a static voltage of more than 10,000 volts. When these charged bodies come into contact with the wafer, they will be discharged to the wafer, with the result that the wafer may fail. For the most common complementary metal-oxide-semiconductor (CMOS) process technology, the problems caused by electrostatic discharge events are particularly serious. Therefore, in order to prevent the wafer from being damaged by the electrostatic discharge, various software and hardware for preventing the electrostatic discharge are developed. The most common practice is to use hardware to prevent electrostatic discharge. That is, an electrostatic discharge protection circuit is designed between the internal circuit and each pad to protect its internal circuit. In addition, due to the simultaneous reduction in the thickness of the gate oxide layer with the process accumulation, the collapse voltage of the gate oxide layer will gradually approach the source / drain junction breakdown voltage, or even lower. At this time, the original ESD protection circuit (Please read the precautions on the back before filling this page)
1T 經濟部智慧財產局8工消f合作社印製 本紙張尺度適用中國菌家標準（CNS ) A4规格〈210X297公釐） 412856 45 I 8tvvr,d〇c/002 A7 B7 五、發明説明（> ) 設計效能將大打折扣。此外，內部電路多半依循最小設計 準貝丨J(Minimuni Design Rules)設計，且未適當地設計，例如 接觸窗到擴散區的邊緣，以及接觸窗到閘極邊緣均需要較 大的空間以抵抗巨大的靜電放電暫態電流（Transient Current) ’致使在高積集度的情況下，晶片極容易受到靜 電放電的損害。所以，靜電放電的問題已成爲深次微米積 體電路故障的原因之一，因此如何能有效提昇靜電放電保 護電路的效能乃爲目前業界所亟盼的。 第1A圖與第1B圖是繪示傳統之靜電放電保護電路示 意圖。請參照第1A圖，由輸入埠INP輸入之靜電可由N 型MOS電晶體N1至接地線Vss放電，用以保護內部電路 1〇。請參照第1B圖，其乃繪示另一種靜電放電保護電路， 由輸入埠INP輸入之靜電可由N型MOS電晶體N1至接地 線Vss放電，亦可由p型MOS電晶體P1至電壓源VDD放 電，用以保護內部電路10。 請參照第2A〜2D圖，其繪示的是習知一種靜電放電保 護電路的製造流程剖面圖。 首先請參照第2A圖，提供一半導體基底20，在半導 體基底20上形成隔離結構22以界定出元件區24及保護電 路區26，其中隔離結構22例如爲淺溝渠隔離結‘構或場氧 化層。並且，在元件區24及保護電路區26中分別形成金 氧半電晶體28與30。金氧半電晶體28包括閘氧化層32a、 多晶矽層34a、間隙壁36a及淡摻雜汲極區結構(Lightly Doped Drain ;簡稱LDD)之源極/汲極區38a(包括N+離子 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210X 297公釐） (請先閱讀背面之注^^項再填寫本頁}1T Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, 8 Industrial Cooperatives, Cooperatives, and printed on this paper. Applicable to Chinese standards (CNS) A4 specifications <210X297 mm) 412856 45 I 8tvvr, doc / 002 A7 B7 V. Description of the invention ) Design efficiency will be greatly reduced. In addition, the internal circuits are mostly designed according to the minimum design rules (Jm) and are not properly designed. For example, the contact window to the edge of the diffusion area and the contact window to the edge of the gate require a large space to resist the huge The transient current of the electrostatic discharge (Transient Current) 'makes the wafer extremely vulnerable to electrostatic discharge damage under high accumulation conditions. Therefore, the problem of electrostatic discharge has become one of the reasons for the failure of deep sub-micron integrated circuits. Therefore, how to effectively improve the performance of the electrostatic discharge protection circuit is currently urgently expected by the industry. Figures 1A and 1B are schematic diagrams showing a conventional electrostatic discharge protection circuit. Please refer to Figure 1A. The static electricity input from the input port INP can be discharged from the N-type MOS transistor N1 to the ground line Vss to protect the internal circuit 10. Please refer to Figure 1B, which shows another electrostatic discharge protection circuit. The static electricity input from the input port INP can be discharged from the N-type MOS transistor N1 to the ground line Vss, or it can be discharged from the p-type MOS transistor P1 to the voltage source VDD. To protect the internal circuit 10. Please refer to FIGS. 2A to 2D, which are cross-sectional views showing a manufacturing process of a conventional electrostatic discharge protection circuit. First, referring to FIG. 2A, a semiconductor substrate 20 is provided. An isolation structure 22 is formed on the semiconductor substrate 20 to define an element region 24 and a protection circuit region 26. The isolation structure 22 is, for example, a shallow trench isolation junction structure or a field oxide layer. . Further, metal-oxide semiconductors 28 and 30 are formed in the element region 24 and the protection circuit region 26, respectively. The metal-oxide semiconductor transistor 28 includes a gate oxide layer 32a, a polycrystalline silicon layer 34a, a spacer 36a, and a source / drain region 38a of a lightly doped drain region structure (LDD) (including N + ion paper size). Applicable to China National Standard (CNS) Α4 specification (210X 297 mm) (Please read the note ^^ on the back before filling this page}
、1T 經濟部智慧財產局8工消費合作社印製 經濟部智慧財產局員工消費合作杜印製 412856 45 I Slwf.doc/002 A7 B7 五、發明説明（多） 摻雜區與N-離子摻雜區）。以及，金氧半電晶體30包括閘 氧化層32b、多晶矽層3仆、間隙壁36b及LDD結構之源 極/汲極區38b。 接著請參照第2B圖，形成一層金屬矽化物罩幕層 (Salicide Block ; SAB)40覆蓋整個保護電路區26，其中金 屬砂化物罩幕層40的材質包括氧化物(oxide)。 再來請參照第2C圖，進行自行對準金屬矽化物製程 (Salicide)，藉以在元件區24中之多晶砂層34a及源極/汲 極區38a上形成一層金屬矽化物層42、44。 接著請參照第2D圖，隨後去除保護電路區26中之金 屬砂化物罩幕層40。然後，形成一層介電層46覆蓋元件 區24及保護電路區26，其中介電層46的材質例如是二氧 化矽（Si02)。之後，使用非等向性乾蝕刻法分別去除元件 區24及保護電路區26中之部份介電層46 ^以分別暴露出 金屬矽化物層44及源極/汲極區38b，而形成如第2D圖所 繪示之結構。 接著，進行後續的步驟，以完成積體電路的製造，然 而此後續製程爲習知此技藝者所熟知，無關本發明之特 徵，故此處不再贅述。 由上述的製造流程得知，積體電路之靜電放電保護電 路的製造係與其內部電路同時製造完成的，不需另外多加 製程步驟來完成。然而，於整個保護電路區上覆蓋一層金 屬矽化物罩幕層，如此不僅增加了多晶矽層的阻抗，而且 也會增加傳播延遲（propagation delay)。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家橾準（CNS ) A4规格（2!〇Χ 297公釐） 經濟部智慧財產局員工消費合作社印製 412856 4 5 ϊ 8l w t'.doc/OU 2 A7 ___B7___ 五、發明説明（一） 另一方面，若於部分保護電路區上覆蓋一層金屬矽化 物罩幕層，將會降低接觸窗至閘極（多晶矽層）邊緣的準則 (rule)。舉例來說，如第3圖所示，最初接觸窗50至多晶 矽層52邊緣的準則爲DHD2+D3，然而經過覆蓋部分金屬 矽化物罩幕層（SAB)54後，將使得其準則變成只剩下D2。 如此將會縮短電流消散路徑，造成ESD保護能力不佳。 有鑒於此，本發明提出一種靜電放電保護電路的製造 方法，包括首先於半導體基底上形成隔離結構以界定出元 件區及保護電路區，此元件區及保護電路區中分別已形成 第一金氧半電晶體與第二金氧半電晶體，上述第一金氧半 電晶體與第二金氧半電晶體分別具有第一多晶矽層與第二 多晶矽層，且第一多晶矽層與第二多晶矽層上分別已形成 第一矽化鎢層與第二矽化鎢層。接著，形成金屬矽化物罩 幕層覆蓋保護電路區。之後，進行自行對準金屬矽化物製 程3最後，去除金屬砂化物罩幕層。 本發明所提出之種靜電放電保護電路的製造方法，由 於不需另外多加製程步驟或光罩，故不會有成本增加的問 題。而且在多晶砂層上形成砂化鶴層，可因而使得多晶砂 層具有低阻抗及低傳播延遲的功能。此外，本發明並未降 低接觸窗至多晶矽層邊緣的準則，因此不會有任何電流消 散路徑縮短的問題，進而可達到高電路執行效能及提昇 ESD保護能力的目的。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例’並配合所附圖式’作詳細 6 本紙張尺度適用中國Ϊ家棒$ ( CNS )八4规^( 2丨〇><297公董^ " ^ ^^1 I - 1 - -- I I m l^i (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 412856 45 iStvv f.doc/002 A 7 B7五、發明説明（f) 說明如下： 圖式之簡單說明： 第1A圖繪示的是習知一種靜電放電保護電路的電路 結構圖； 第1B圖繪示的是習知另一種靜電放電保護電路的電 路結構圖； 第2A〜2D圖繪示的是習知一種靜電放電保護電路的製 造流程剖面圖； 第3圖繪示·的是習知靜電放電保護電路經覆蓋部分金 屬矽化物罩幕層後的上視圖；以及 第4A〜4D圖繪示的是依照本發明一較佳實施例的一種 靜電放電保護電路的製造流程剖面圖。 圖式之標號說明： 10 :內部電路 20 ' 60 :半導體基底 22、62 :隔離結構 24、64 :元件區 26、66 :保護電路區 28、30、68、70 :金氧半電晶體 32a、32b、72a、72b :閘氧化層 34a、34b ' 52、74a、74b :多晶矽層 36a、36b、76a、76b :間隙壁 38a、38b、78a、78b :源極/汲極區 40、54、82 :金屬矽化物罩幕層 i 1·^^— n^i 1^1^1 1 n^i— T i 穿 ·ν5 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 412856 A7 45 1 Stw r.doc/002 Λ/ B7____ 五、發明説明（^) 42、44、84 :金屬矽化物層 — 46、86 :介電層 50 :接觸窗 80a、80b :矽化鎢層 實施例 請參照第4A〜4D圖，其繪示的是依照本發明一較佳實 施例的一種靜電放電保護電路的製造流程剖面圖。 首先請參照第4A圖，提供一半導體基底60 ’在半導 體基底60上形成隔離結構62以界定出元件區64及保護電 路區66，其中隔離結構62例如爲淺溝渠隔離結構或場氧 化層。並且，在元件區64及保護電路區66中分別形成金 氧半電晶體68與70。金氧半電晶體68包括閘氧化層72a、 多晶矽層74a、間隙壁76a及淡摻雜汲極區結構(LDD)之源 極/汲極區78a(包括N+離子摻雜區與N-離子摻雜區）。金氧 半電晶體70包括閘氧化層72b、多晶矽層74b、間隙壁76b 及LDD結構之源極/汲極區78b。此外，必須注意的是，在 金氧半電晶體68、70之多晶矽層74a、74b上，更形成有 一砍化鎢層8 0 a、8 0 b。 接著請參照第4B圖，例如以化學氣相沉積法（CVD), 形成一層金屬矽化物罩幕層（SAB)82覆蓋整個保護電路區 66 ’其中金屬矽化物罩幕層S2包括氧化層。 再來請參照第4C圖，進行自行對準金屬矽化物製程， 藉以在元件區64中之源極/汲極區78a上形成一層金屬砂 化物層84。 . J— - II - II - I ^ - I n --訂 {請先閲讀背面之注意事項再填寫本頁) 本紙ft尺度適用令國國家標準（CNS) M規格（21〇Χ 297公着） A7 B7 412856 45 I 8twr.tiuc/(J02 五、發明説明（rp 接著請參照第4D圖，隨後例如使用傳統微影蝕刻法’ 去除保護電路區66中之金屬矽化物罩幕層82。然後，形 成一層介電層86覆蓋元件區64及保護電路區66，其中介 電層86的材質例如是二氧化矽（Si〇2)。之後，例如使用非 等向性乾蝕刻法分別去除元件區64及保護電路區66中之 部份介電層86，以分別暴露出金屬矽化物層84及源極/汲 極區78b，而形成如第4d圖所繪示之結構。 接著’進行後續的步驟，以完成積體電路的製造’然 而此後續製程爲習知此技藝者所熟知，無關本發明之特 徵，故此處不再贅述。 由上述的製造流程得知，本發明之靜電放電保護電路 的製造同樣係與其內部電路同時製造完成的，不需另外多 加製程步驟或光罩來完成。此外，由於本發明之結構，係 在保護電路區66中之金氧半電晶體70的多晶矽層7朴上 形成有一砍化鎢層80b，故可使多晶矽層74b具有低阻抗 及低傳播延遲的功能。而且，本發明並未改變（降低）原先 接觸窗至多晶矽層邊緣的準則，因此不會發生任何電流消 散路徑縮短的問題，進而可達到高電路執行效能以及ESD 保護能力佳的目的。 綜上所述，本發明具有以下的優點： (1) 不需另外多加製程步驟或光罩，故不會有成本增加 的問題。 (2) 可使得多晶矽層具有低阻抗及低傳播延遲的功 I 1- ml ^fn in^i -- -- mt J I I— I: 1 一eJ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局資工消资合作社印" 本紙張尺度適用中國國家標率（CNS ) A4規格< 210X297公釐} 4U_ 〇 c / Ο Ο 2 Α7 Β7 五、發明説明（公） (3) 未降低接觸窗至多晶矽層邊緣的準則，因此不會有 任何電流消散路徑縮短的問題。 (4) 可達到高電路執行效能以及提昇ESD保護能力的 目的。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準{ CNS ) Α4規格（210><297公釐>、 1T Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs 8 Industrial Consumer Cooperatives Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Printing Du 412856 45 I Slwf.doc / 002 A7 B7 V. Description of the invention (multiple) Doped regions and N-ion doping Area). And, the metal-oxide semiconductor transistor 30 includes a gate oxide layer 32b, a polycrystalline silicon layer 3, a spacer 36b, and a source / drain region 38b of the LDD structure. Referring to FIG. 2B, a metal silicide mask (Salicide Block; SAB) 40 is formed to cover the entire protection circuit area 26, and the material of the metal sand mask cover 40 includes oxide. Referring to FIG. 2C again, a self-aligned metal silicide process (Salicide) is performed to form a metal silicide layer 42, 44 on the polycrystalline sand layer 34a and the source / drain region 38a in the device region 24. Referring to FIG. 2D, the metal sanding mask layer 40 in the protection circuit area 26 is subsequently removed. Then, a dielectric layer 46 is formed to cover the element region 24 and the protection circuit region 26. The material of the dielectric layer 46 is, for example, silicon dioxide (SiO2). After that, a part of the dielectric layer 46 in the element region 24 and the protection circuit region 26 is removed by using an anisotropic dry etching method to expose the metal silicide layer 44 and the source / drain region 38b, respectively, and formed as The structure shown in Figure 2D. Next, the subsequent steps are performed to complete the manufacture of the integrated circuit. However, this subsequent process is well known to those skilled in the art and has nothing to do with the features of the present invention, so it will not be repeated here. It is known from the above manufacturing process that the manufacturing of the electrostatic discharge protection circuit of the integrated circuit is completed at the same time as its internal circuit, and no additional process steps are required to complete it. However, covering the entire protection circuit area with a metal silicide mask layer not only increases the impedance of the polycrystalline silicon layer, but also increases the propagation delay. (Please read the precautions on the back before filling in this page) This paper size uses the Chinese National Standard (CNS) A4 size (2! 〇 × 297 mm) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 412856 4 5 ϊ 8l w t'.doc / OU 2 A7 ___B7___ 5. Description of the invention (1) On the other hand, if a layer of metal silicide cover is covered on a part of the protection circuit area, the contact window will be reduced to the gate (polycrystalline silicon layer) The rule of the edge. For example, as shown in FIG. 3, the criterion for initially contacting the window 50 to the edge of the polycrystalline silicon layer 52 is DHD2 + D3. However, after covering part of the metal silicide mask layer (SAB) 54, the criterion will be left only Press D2. This will shorten the current dissipation path and cause poor ESD protection. In view of this, the present invention proposes a method for manufacturing an electrostatic discharge protection circuit, which includes first forming an isolation structure on a semiconductor substrate to define an element region and a protection circuit region, and a first metal oxide has been formed in the element region and the protection circuit region, respectively. A semi-transistor and a second metal-oxide semi-transistor, the first metal-oxide semi-transistor and the second metal-oxygen semi-transistor each having a first polycrystalline silicon layer and a second polycrystalline silicon layer, and the first polycrystalline silicon A first tungsten silicide layer and a second tungsten silicide layer have been formed on the layer and the second polycrystalline silicon layer, respectively. Next, a metal silicide mask is formed to cover the protection circuit area. After that, the self-aligned metal silicide process 3 is performed. Finally, the metal sand mask layer is removed. Since the manufacturing method of the electrostatic discharge protection circuit proposed by the present invention does not require additional process steps or photomasks, there is no problem of cost increase. Furthermore, the formation of a sanding crane layer on the polycrystalline sand layer can thus make the polycrystalline sand layer have the functions of low impedance and low propagation delay. In addition, the present invention does not reduce the criterion of the contact window to the edge of the polycrystalline silicon layer, so there will not be any problem of shortening the current dissipation path, thereby achieving the goals of high circuit execution efficiency and improving ESD protection capability. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes in detail the preferred embodiment 'and the accompanying drawings' for details. 6 This paper size is applicable to China Jiajiabang $ (CNS) 8 rules ^ (2 丨 〇 > < 297 public directors ^ " ^ ^^ 1 I-1--II ml ^ i (Please read the precautions on the back before filling out this page} Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative 412856 45 iStvv f.doc / 002 A 7 B7 V. Description of the invention (f) The description is as follows: The diagram is briefly explained: Figure 1A shows the circuit structure of a conventional electrostatic discharge protection circuit Figure 1B shows a circuit structure diagram of a conventional electrostatic discharge protection circuit; Figures 2A to 2D show cross-sectional views of a manufacturing process of a conventional electrostatic discharge protection circuit; Figure 3 shows It is a top view of a conventional electrostatic discharge protection circuit after covering a part of a metal silicide cover curtain layer; and FIGS. 4A to 4D show cross-sectional views of a manufacturing process of an electrostatic discharge protection circuit according to a preferred embodiment of the present invention . Explanation of the number of the drawings: 10: Internal circuit 20 '60 : Semiconductor substrates 22, 62: Isolation structures 24, 64: Element regions 26, 66: Protective circuit regions 28, 30, 68, 70: Metal-oxide semiconductors 32a, 32b, 72a, 72b: Gate oxide layers 34a, 34b ' 52, 74a, 74b: polycrystalline silicon layers 36a, 36b, 76a, 76b: spacers 38a, 38b, 78a, 78b: source / drain regions 40, 54, 82: metal silicide mask layer i 1 ^^- n ^ i 1 ^ 1 ^ 1 1 n ^ i— T i wear · ν5 (Please read the precautions on the back before filling in this page) This paper size applies the Chinese National Standard (CNS) Α4 size (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 412856 A7 45 1 Stw r.doc / 002 Λ / B7____ V. Description of the Invention (^) 42, 44, 84: Metal silicide layer—46, 86: Dielectric layer 50: Contact windows 80a, 80b: For an embodiment of a tungsten silicide layer, please refer to FIGS. 4A to 4D, which show a cross-sectional view of a manufacturing process of an electrostatic discharge protection circuit according to a preferred embodiment of the present invention. First, please refer to FIG. 4A. A semiconductor substrate 60 is provided to form an isolation structure 62 on the semiconductor substrate 60 to define a device region 64 and a protection circuit region 66, wherein The structure 62 is, for example, a shallow trench isolation structure or a field oxide layer. Further, metal oxide semiconductors 68 and 70 are formed in the element region 64 and the protection circuit region 66. The metal oxide semiconductor 68 includes a gate oxide layer 72a and a polycrystalline silicon layer. 74a, a spacer 76a, and a source / drain region 78a (including an N + ion-doped region and an N-ion-doped region) of a lightly doped drain region structure (LDD). The metal-oxide semiconductor transistor 70 includes a gate oxide layer 72b, a polycrystalline silicon layer 74b, a spacer 76b, and a source / drain region 78b of the LDD structure. In addition, it must be noted that on the polycrystalline silicon layers 74a, 74b of the metal-oxide semiconductor transistors 68, 70, a tungsten carbide layer 80a, 80b is further formed. Referring to FIG. 4B, for example, a chemical vapor deposition (CVD) method is used to form a metal silicide mask layer (SAB) 82 to cover the entire protection circuit area 66 '. The metal silicide mask layer S2 includes an oxide layer. Referring to FIG. 4C again, a self-aligned metal silicide process is performed to form a metal sand layer 84 on the source / drain region 78a in the device region 64. J—-II-II-I ^-I n-Order {Please read the notes on the back before filling this page) The ft dimension of this paper applies the national standard (CNS) M specification (21〇 × 297) A7 B7 412856 45 I 8twr.tiuc / (J02 V. Description of the invention (rp) Please refer to FIG. 4D, and then use a conventional lithographic etching method to remove the metal silicide mask layer 82 in the protection circuit area 66. Then, A dielectric layer 86 is formed to cover the element region 64 and the protection circuit region 66, and the material of the dielectric layer 86 is, for example, silicon dioxide (SiO2). Thereafter, the element region 64 is removed by using an anisotropic dry etching method, for example. And a part of the dielectric layer 86 in the protection circuit area 66 to expose the metal silicide layer 84 and the source / drain area 78b respectively, so as to form the structure as shown in FIG. 4d. Then 'the subsequent steps are performed. To complete the manufacture of integrated circuits', however, this subsequent process is well known to those skilled in the art and has nothing to do with the features of the present invention, so it will not be repeated here. From the above manufacturing process, it is known that the electrostatic discharge protection circuit of the present invention Manufacturing is also completed at the same time as its internal circuits No additional process steps or photomasks are required to complete the process. In addition, due to the structure of the present invention, a polycrystalline silicon layer 7 of the gold-oxygen semi-transistor 70 in the protective circuit area 66 is formed with a chopped tungsten layer 80b. Therefore, the polycrystalline silicon layer 74b can have the functions of low impedance and low propagation delay. In addition, the present invention does not change (reduce) the criterion of the original contact window to the edge of the polycrystalline silicon layer, so no problem of shortening the current dissipating path will occur, which can To achieve the purpose of high circuit execution efficiency and good ESD protection ability. In summary, the present invention has the following advantages: (1) No additional process steps or photomasks are needed, so there will be no cost increase. (2) I 1- ml ^ fn in ^ i--mt JII— I: 1-eJ (please read the notes on the back before filling this page) Printed by the Property Bureau, Consumer and Consumer Cooperatives " This paper size applies to China's national standard (CNS) A4 specifications < 210X297 mm} 4U_ 〇c / Ο Ο 2 Α7 Β7 V. Description of the invention (public) (3) Not lowered Contact window Standards up to the edge of the polycrystalline silicon layer, so there will not be any problem of shortening the current dissipation path. (4) The purpose of high circuit execution efficiency and improvement of ESD protection capability can be achieved. Although the present invention has been disclosed as above with a preferred embodiment, its It is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the attached patent application. (Please read the notes on the back before filling in this page) The paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard {CNS) A4 Specification (210 > < 297mm >)