411510 26 i 6tu Π .doc/flfl2 第8 7 ] ίΠ 6 ；U號説明軎修正頁 五、發明說明（t ) 106a，暴露出基底100表與複晶矽層104表面’而使汲 極區11 〇上之第二熱氧化物層112形成一間隙壁結構 1 1 2a，而閘極1 04之另一側亦有部分的第一熱氧化物層 l〇6b存在，如第1F圖所示。之後，以閘極1〇4與間隙壁 結構112a爲罩幕，進行一第二摻雜1]3，而在相鄰於閘極 104 —側形成摻雜濃度不同之汲極區Π 〇a、110a’，其中汲 極區110a爲摻雜濃度較淡的區域，如此可減少電子自閘極 104穿透間隙壁112a至汲極區1 l〇a的機會，進而增加元 件的可靠度，而閘極104之另一側形成閘極104之源極區 1 l〇b。續再進行回火（anneal)的步驟以活化源/汲極區 110a、110a’、1 10b 的雜質。 而本發明的主要結構包括形成在基底100上的閘極 104及閘極氧化物層102a，更包括汲極區110a、110a’與 源極區110b。另外，以第二熱氧化物層形成的間隙壁結構 112a係作爲汲極區110a上之閘極氧化物層，而部分的第 一氧化物層l〇6b作爲源極區110b上之閘極氧化物層。 本發明由於在閘極靠近汲極區處形成一間隙壁結構狀 的閘極氧化物層，藉以提供一較厚的閘極氧化物層，而可 使通道區中的電場下降，而藉以減少熱載子效應。並因避 免使用LDD結構，亦增加了靜電保護的能力，因之得以增 進元件操作的可靠度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 7 本紙張尺度適用中關家標準（CNS)A4規格（210 X 297公釐)~ ~ .^1 I I « D n n I I I n {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財羞局貝工消费合作社印製 411510 2616TWF.DOC/006 經濟部中央樣隼局貝X消费合作社印製 五、發明説明（/ ) 本發明是有關於一種不同厚度閘極氧化物層的結構及 其製造方法’且特別是有關於一種增進靜電放電 (Electrostatic discharge，ESD)之不同厚度閘極氧化物層的 結構及其製造方法。 在半導體技術尺寸日漸縮小的情況下，M0S元件的通 道長度相對地也隨之縮短，而當MOS電晶體的通道長度縮 短’假若施加的電壓大小不變，通道內的橫向電場將增加， 而使得通道內的電子藉由電場加速所獲得的能量上升，尤 其是在通道和汲_極區相接的附近，電子的能量將很高。因 爲這些電子的能量比其他尙處於熱平衡狀態（Thermal Equilibrium)下的電子還高，所以稱爲熱電子（Hot Electrons)，此種現象則稱作熱電子效應（Hot Electron Effect)，亦稱熱載子效應(Hot Carrier Effect)。而熱電子效 應會隨著通道長度的縮短而影響MOS電晶體的操作。 而解決短通道MOS的“熱電子效應”的方法，例如降 低M0S電晶體的操作電壓。另一種較爲常用的方法，即在 原來的M0S源極和汲極接近通道的地方，再增加一組摻雜 程度較原來源極與汲極爲低的區域，即爲“淡摻雜汲極” (Lightly Doped Drain, LDD) ° 然使用LDD製程，則會影響靜電放電保護 (Electrostatic-Discharge Protection)的能力。元件靜電可藉 由各種方式而產生，例如將積體電路從其塑膠的封裝中移 出時，甚或是人移動經過時，均有可能產生靜電。而此高 電壓若未經注意而施加在1C封裝的接腳(pin)上，則將導致 3 (請先閲讀背面之注意事項再填寫本頁) -裝 訂 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐} 411510 26 I6TWF.DOC/006 A7 B7 五、發明説明（；）· 元件閘極氧化物層崩潰（Breakdown)。崩潰現象的產生可倉^ 對元件造成立即的破壞，或是降低元件操作的壽命。 因此，在所有MOS積體電路的接腳上，均提供保護電 路以預防上述的靜電電流對MOS閘極造成的損害，而保護 電路係置於元件的輸入端與輸出端之間，而輸入與輸出端 連接至轉移電晶體閘極，用以傳導或承受崩潰的現象，藉 此提供一電路路徑接地。由於崩潰機制因上述之保護電路 而無害’故電路可提供一正常的通路，而僅在輸入端輸出 端施以一高電壓時關閉通路。 有鑑於此，本發明的主要目的，就是在MOS閘極接近 汲極區處形成一較厚的閘極氧化物層，因之通道區中的電 場可以下降而藉以降低熱載子效應。且由於未利用LDD製 程，因此可以增加靜電保護能力。 爲達上述之目的，本發明提供一種不同厚度閘極氧化物 層的製造方法，提供一基底，在基底上形成有一聞極氧化 物層與一閘極，之後去除部分的閘極氧化物層。接著形成 一第一熱氧化物層覆蓋住基底與閘極表面，更形成一罩幕 層覆蓋住第一熱氧化物層。續定義罩幕層與去除部分第一 熱氧化物層，而暴露出部分閘極與基底表面。再進行一第 -一摻雜，而在閘極相鄰之一側形成一汲極區。緊接著形成 一第二熱氧化物層，覆蓋住暴露出.之基底與閘極，再去除 罩幕層與回蝕刻第二氧化物層與第一熱氧化物層，暴露出 閘極表面，而使汲極區上之第二氧化物層成爲一間隙壁結 構。續再進行一第二摻雜，使汲極區在接近閘極處之摻雜 4 JUJU * 裝— I I 11 I 訂 I 111 ^ • 0 {諳先Μ讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印裝 本紙浪尺度通用中國國家標準（CNS ) Α4規格（210Χ297公釐） 經濟部中央標準局貞工消費合作社印製 411510 2616TWF.DOC/OU6 B7 五、發明説明（3 ) 濃度較淡，另外在閘極之另一側形成一源極區。 爲達上述之目的，本發明提供一種不同厚度閘極氧化物 層的結構，其包括一基底，且基底上具有一第一閘極氧化 物層與一閘極。尙包括一汲極區、一源極區、一第二閘極 氧化物層以及一第三閘極氧化物層。其中，汲極區位於相 鄰於閘極之一側，且汲極區在接近閘極處之摻雜濃度較 淡，而源極區位於相鄰於閘極之另一側。第二閘極氧化物 層爲一間隙壁結構，位於汲極區上且相鄰於閘極，以及第 三閘極氧化物層位於源極區上且相鄰於閘極。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 __ 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1F圖係顯示根據本發明較佳實施例不同 厚度閘極氧化物層之製造流程剖面圖。 其中，各圖標號之簡單說明如下： 100 :基底 102、102a :閘極氧化物層 104 :閘極 106、106a、106 :第一熱氧化物層 108 ' 108a :罩幕層 110、1 10a、110a5、110b :源/汲極區 112、112a :第二熱氧化物層 實施例 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） J—--------—餐— (請先閱讀背面之注意事項再填寫本頁) 訂 5 經濟部中央標率局員工消費合作社印製 411510 26 16TWF.DOC/0 06 Β7 五、發明説明（y) 第1A圖至第IF圖係顯示根據本發明較佳實施例不同 厚度閘極氧化物層之製造流程剖面圖。 請參照第1A圖。在一 P型矽基底100上，例如以熱氧 化法形成一厚度約爲50A之閘極氧化物層102。之後，沉 積一摻有N型雜質的複晶矽層104，並定義複晶矽層104 作爲MOS電晶體的閘極。 接著，如第1B圖所示，利用等向性蝕刻法，例如爲氫 氟酸溶液，去除部分的閘極氧化物層102,而暴露出未被複 晶矽層104覆蓋的基底100表面。再以熱氧化法加熱基底 102而在基底100與複晶矽104表面形成一第一熱氧化物層 106，厚度約爲100-200A。續在第一熱氧化物層106上形成 一罩幕層108，例如以化學氣相沉積法沉積一氮化矽層，厚 度則約爲1000-2000A，如第1C圖所示。 請參照第1D圖，以微影蝕刻法定義罩幕層108a，並去 除部分的第一熱氧化物層1〇仏與閘極氧化物層102a，例如 以等向性濕蝕刻法之氫氟酸溶液進行，而暴露出相鄰閘極 104—側的基底100表面。再對基底100進行第一摻雜109， 例如以植入法，將N型離子植入基底100，而在基底100 形成一汲極區Π0。 請參照第1E圖。接著，再利用熱氧化法，在暴露出的 基底1〇〇表面形成一第二熱化物層112，第二熱氧化物層 112覆蓋住相鄰閘極104 —側的基底100表面，且覆蓋住部 分的閘極104。之後，去除罩幕層108a，並利用非等向性 蝕刻法，蝕刻第二熱氧化物層Π2與第一熱氧化物層 6 本紙張尺度適用中國國家楯準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁)411510 26 i 6tu Π.doc / flfl2 page 8 7 ίΠ 6; Description of U No. 軎 Correction Page V. Description of Invention (t) 106a, exposing the surface of the substrate 100 and the surface of the polycrystalline silicon layer 104 ', so that the drain region 11 The second thermal oxide layer 112 on 〇 forms a spacer structure 1 12a, and a part of the first thermal oxide layer 106b exists on the other side of the gate 104, as shown in FIG. 1F. After that, the gate electrode 104 and the spacer structure 112a are used as a mask to perform a second doping 1] 3, and a drain region Π 〇a, which has a different doping concentration, is formed on the side adjacent to the gate 104. 110a ', where the drain region 110a is a region with a lighter doping concentration, which can reduce the chance of electrons from the gate 104 penetrating the gap 112a to the drain region 110a, thereby increasing the reliability of the device, and the gate The other side of the electrode 104 forms a source region 11b of the gate 104. The annealing step is continued to activate the impurities in the source / drain regions 110a, 110a ', 1 10b. The main structure of the present invention includes a gate 104 and a gate oxide layer 102a formed on the substrate 100, and further includes a drain region 110a, 110a 'and a source region 110b. In addition, the spacer structure 112a formed by the second thermal oxide layer is used as the gate oxide layer on the drain region 110a, and a part of the first oxide layer 106b is used as the gate oxide on the source region 110b. Physical layer. In the present invention, a gate oxide layer with a gap structure is formed at the gate near the drain region, thereby providing a thicker gate oxide layer, which can reduce the electric field in the channel region, thereby reducing heat. Carrier effect. And because the use of LDD structure is avoided, the ability of electrostatic protection is also increased, which can increase the reliability of component operation. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 7 This paper size applies the Zhongguanjia Standard (CNS) A4 specification (210 X 297 mm) ~ ~. ^ 1 II «D nn III n {Please read the notes on the back before filling this page) Printed by the Bureau Cooperative Consumer Cooperative 411510 2616TWF.DOC / 006 Printed by the Central Bureau of the Ministry of Economic Affairs Bureau X Consumer Cooperative Co., Ltd. V. Description of the invention (/) The present invention relates to the structure of a gate oxide layer with different thickness and its manufacture The method and, more particularly, it relates to a structure of a gate oxide layer with different thicknesses that promotes electrostatic discharge (ESD) and a manufacturing method thereof. As the size of semiconductor technology is shrinking, the channel length of the M0S element is correspondingly shortened. When the channel length of the MOS transistor is shortened, if the applied voltage is not changed, the lateral electric field in the channel will increase, making The energy obtained by the electrons in the channel is accelerated by the electric field acceleration, especially in the vicinity of the connection between the channel and the drain region, the energy of the electrons will be very high. Because these electrons have higher energy than other electrons in the thermal equilibrium state (Thermal Equilibrium), they are called Hot Electrons. This phenomenon is called Hot Electron Effect, also known as heat load. Sub effect (Hot Carrier Effect). The thermal electron effect will affect the operation of the MOS transistor with the shortening of the channel length. The method to solve the "hot electron effect" of short-channel MOS, for example, to reduce the operating voltage of the MOS transistor. Another more commonly used method is to add a set of regions with lower doping levels than the original source and drain where the original MOS source and drain are close to the channel, which is called "lightly doped drain". (Lightly Doped Drain, LDD) ° However, using the LDD process will affect the ability of Electrostatic-Discharge Protection. Component static electricity can be generated in various ways, such as when the integrated circuit is removed from its plastic package, or even when people move past it. And if this high voltage is applied to the pins of the 1C package without attention, it will result in 3 (Please read the precautions on the back before filling this page)-Binding this paper size uses the Chinese National Standard (CNS ) A4 specification (210X297 mm) 411510 26 I6TWF.DOC / 006 A7 B7 V. Description of the invention (;) · Breakdown of the gate oxide layer of the device. The occurrence of the collapse phenomenon can cause damage to the device immediately, Or reduce the operating life of the component. Therefore, protection pins are provided on the pins of all MOS integrated circuits to prevent the above-mentioned electrostatic current from causing damage to the MOS gate, and the protection circuit is placed between the input end of the component and Between the output terminals, and the input and output terminals are connected to the transfer transistor gate to conduct or withstand the collapse phenomenon, thereby providing a circuit path to ground. Because the collapse mechanism is harmless due to the protection circuit described above, the circuit can provide It is a normal path, and the path is closed only when a high voltage is applied to the input end and the output end. In view of this, the main purpose of the present invention is to form a comparison between the MOS gate and the drain region. The thick gate oxide layer can reduce the hot carrier effect because the electric field in the channel region can be reduced. And because the LDD process is not used, the electrostatic protection ability can be increased. To achieve the above purpose, the present invention provides a different A method for manufacturing a thick gate oxide layer includes providing a substrate on which a gate oxide layer and a gate electrode are formed, and then a portion of the gate oxide layer is removed. A first thermal oxide layer is then formed to cover the gate oxide layer. The substrate and the gate surface further form a mask layer to cover the first thermal oxide layer. The mask layer and the portion of the first thermal oxide layer are further defined, and part of the gate and substrate surfaces are exposed. -A doping, and a drain region is formed on one side of the gate. Next, a second thermal oxide layer is formed to cover the exposed substrate and gate, and then the mask layer and etch-back are removed. The second oxide layer and the first thermal oxide layer expose the gate surface, so that the second oxide layer on the drain region becomes a spacer structure. A second doping is performed to make the drain region Near the gate Miscellaneous 4 JUJU * Equipment — II 11 I Order I 111 ^ • 0 {谙 Please read the precautions on the back before filling out this page) Central Standards Bureau of the Ministry of Economic Affairs Shellfish Consumer Cooperatives Printed Paper Wave Standard Common Chinese National Standards (CNS) A4 specification (210 × 297 mm) Printed by Zhengong Consumer Cooperative, Central Standards Bureau of the Ministry of Economic Affairs 411510 2616TWF.DOC / OU6 B7 V. Description of the invention (3) The concentration is relatively light, and a source region is formed on the other side of the gate. To achieve the above object, the present invention provides a structure of a gate oxide layer with different thicknesses, which includes a substrate, and the substrate has a first gate oxide layer and a gate electrode. Thallium includes a drain region, a source region, a second gate oxide layer, and a third gate oxide layer. Among them, the drain region is located on one side adjacent to the gate, the doping concentration of the drain region near the gate is relatively light, and the source region is located on the other side adjacent to the gate. The second gate oxide layer is a spacer structure, which is located on the drain region and adjacent to the gate, and the third gate oxide layer is located on the source region and adjacent to the gate. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: 1A to 1F are cross-sectional views showing a manufacturing process of gate oxide layers with different thicknesses according to a preferred embodiment of the present invention. Among them, a brief description of each icon number is as follows: 100: substrate 102, 102a: gate oxide layer 104: gate 106, 106a, 106: first thermal oxide layer 108 '108a: cover layer 110, 110a, 110a5, 110b: source / drain regions 112, 112a: second thermal oxide layer Example 5 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) J —--------— Meal — (Please read the notes on the back before filling in this page) Order 5 Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Printed by the Consumer Consumption Cooperative 411510 26 16TWF.DOC / 0 06 Β7 V. Description of the Invention (y) Figures 1A to IF FIG. Is a sectional view showing a manufacturing process of a gate oxide layer with different thicknesses according to a preferred embodiment of the present invention. Please refer to Figure 1A. On a P-type silicon substrate 100, a gate oxide layer 102 having a thickness of about 50 A is formed, for example, by a thermal oxidation method. After that, a N-type impurity-doped polycrystalline silicon layer 104 is deposited, and the polycrystalline silicon layer 104 is defined as the gate of the MOS transistor. Next, as shown in FIG. 1B, a part of the gate oxide layer 102 is removed by using an isotropic etching method, such as a hydrofluoric acid solution, to expose the surface of the substrate 100 which is not covered by the polycrystalline silicon layer 104. Then, the substrate 102 is heated by a thermal oxidation method to form a first thermal oxide layer 106 on the surface of the substrate 100 and the polycrystalline silicon 104 with a thickness of about 100-200A. Next, a mask layer 108 is formed on the first thermal oxide layer 106. For example, a silicon nitride layer is deposited by chemical vapor deposition, and the thickness is about 1000-2000A, as shown in FIG. 1C. Referring to FIG. 1D, the mask layer 108a is defined by a lithographic etching method, and a part of the first thermal oxide layer 10 仏 and the gate oxide layer 102a are removed, for example, hydrofluoric acid using an isotropic wet etching method. The solution is carried out, and the surface of the substrate 100 on the side of the adjacent gate 104 is exposed. A first doping 109 is performed on the substrate 100, for example, an N-type ion is implanted into the substrate 100 by an implantation method, and a drain region Π0 is formed on the substrate 100. Please refer to Figure 1E. Next, a thermal oxidation method is used to form a second thermal compound layer 112 on the exposed surface of the substrate 100. The second thermal oxide layer 112 covers the surface of the substrate 100 on the side of the adjacent gate electrode 104 and covers Parts of the gate 104. After that, the mask layer 108a is removed, and the second thermal oxide layer Π2 and the first thermal oxide layer 6 are etched using an anisotropic etching method. ) (Please read the notes on the back before filling this page)
411510 26 i 6tu Π .doc/flfl2 第8 7 ] ίΠ 6 ；U號説明軎修正頁 五、發明說明（t ) 106a，暴露出基底100表與複晶矽層104表面’而使汲 極區11 〇上之第二熱氧化物層112形成一間隙壁結構 1 1 2a，而閘極1 04之另一側亦有部分的第一熱氧化物層 l〇6b存在，如第1F圖所示。之後，以閘極1〇4與間隙壁 結構112a爲罩幕，進行一第二摻雜1]3，而在相鄰於閘極 104 —側形成摻雜濃度不同之汲極區Π 〇a、110a’，其中汲 極區110a爲摻雜濃度較淡的區域，如此可減少電子自閘極 104穿透間隙壁112a至汲極區1 l〇a的機會，進而增加元 件的可靠度，而閘極104之另一側形成閘極104之源極區 1 l〇b。續再進行回火（anneal)的步驟以活化源/汲極區 110a、110a’、1 10b 的雜質。 而本發明的主要結構包括形成在基底100上的閘極 104及閘極氧化物層102a，更包括汲極區110a、110a’與 源極區110b。另外，以第二熱氧化物層形成的間隙壁結構 112a係作爲汲極區110a上之閘極氧化物層，而部分的第 一氧化物層l〇6b作爲源極區110b上之閘極氧化物層。 本發明由於在閘極靠近汲極區處形成一間隙壁結構狀 的閘極氧化物層，藉以提供一較厚的閘極氧化物層，而可 使通道區中的電場下降，而藉以減少熱載子效應。並因避 免使用LDD結構，亦增加了靜電保護的能力，因之得以增 進元件操作的可靠度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 7 本紙張尺度適用中關家標準（CNS)A4規格（210 X 297公釐)~ ~ .^1 I I « D n n I I I n {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財羞局貝工消费合作社印製411510 26 i 6tu Π.doc / flfl2 page 8 7 ίΠ 6; Description of U No. 軎 Correction Page V. Description of Invention (t) 106a, exposing the surface of the substrate 100 and the surface of the polycrystalline silicon layer 104 ', so that the drain region 11 The second thermal oxide layer 112 on 〇 forms a spacer structure 1 12a, and a part of the first thermal oxide layer 106b exists on the other side of the gate 104, as shown in FIG. 1F. After that, the gate electrode 104 and the spacer structure 112a are used as a mask to perform a second doping 1] 3, and a drain region Π 〇a, which has a different doping concentration, is formed on the side adjacent to the gate 104. 110a ', where the drain region 110a is a region with a lighter doping concentration, which can reduce the chance of electrons from the gate 104 penetrating the gap 112a to the drain region 110a, thereby increasing the reliability of the device, and the gate The other side of the electrode 104 forms a source region 11b of the gate 104. The annealing step is continued to activate the impurities in the source / drain regions 110a, 110a ', 1 10b. The main structure of the present invention includes a gate 104 and a gate oxide layer 102a formed on the substrate 100, and further includes a drain region 110a, 110a 'and a source region 110b. In addition, the spacer structure 112a formed by the second thermal oxide layer is used as the gate oxide layer on the drain region 110a, and a part of the first oxide layer 106b is used as the gate oxide on the source region 110b. Physical layer. In the present invention, a gate oxide layer with a gap structure is formed at the gate near the drain region, thereby providing a thicker gate oxide layer, which can reduce the electric field in the channel region, thereby reducing heat. Carrier effect. And because the use of LDD structure is avoided, the ability of electrostatic protection is also increased, which can increase the reliability of component operation. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 7 This paper size applies the Zhongguanjia Standard (CNS) A4 specification (210 X 297 mm) ~ ~. ^ 1 II «D nn III n {Please read the notes on the back before filling this page) Printed by Bureau Shellfish Consumer Cooperative