TW451474B - Manufacturing method of embedded type dynamic random access memory - Google Patents
Manufacturing method of embedded type dynamic random access memory Download PDFInfo
- Publication number
- TW451474B TW451474B TW089114505A TW89114505A TW451474B TW 451474 B TW451474 B TW 451474B TW 089114505 A TW089114505 A TW 089114505A TW 89114505 A TW89114505 A TW 89114505A TW 451474 B TW451474 B TW 451474B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductive layer
- dynamic random
- manufacturing
- random access
- access memory
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 6
- 230000000903 blocking effect Effects 0.000 abstract description 5
- 239000004575 stone Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 206010040844 Skin exfoliation Diseases 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052500 inorganic mineral Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- -1 metal oxide compound Chemical class 0.000 description 1
- 239000011707 mineral Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
451474 五、發明說明(1) 本發明是有關於一種半導體(semi conductor)積體電 路(integrated circuits ;ICs)製程技術,特別是有關於 一種嵌入式動態隨機存取記憶體(embedded dynamic random access memory ;eDRAM)的製造方法,能夠解決虛 置護環脫落的問題。 習知邏輯(logic)裝置與記憶(memory)裝置分別被形 成於不同的晶片,然後再設置於同一板上。由於形成於不 同晶片的記憶裝置與邏輯裝置的構造,無法破保其高速 性,因此’有一種將記憶裝置與邏輯裝置混合設置於同一 晶片上的裝置被提出,此種裝置亦即所謂的嵌入式半導體 記憶裝置,例如eRAM(embedded Random Access Memory) 裝置。 以下利用第1 A圖至第1D圖之所示部分製程剖面圖,以 §兒明習知技術之一形成e D R A Μ的製造流程。 首先,請參照第1Α圖’該圖顯示具有一記憶體單元區 域(memory cell area)與一邏輯電路區域(1〇gic circuit area)的半導體基底1〇。形成該圖所示之剖面的步驟為’ 在上述邏輯電路區域的半導體基底1〇表面形成一第一導電 層12 ’此層例如先全面性地形成一非晶矽(am〇rph〇us s U 1 con)層,再選擇性餘刻掉記憶體單元區域的部分所形 成。然後全面性地在上述第一導電層12表面形成第二導電 層CL,其係由複晶矽層η與例如矽化鎢(WSi)的金屬矽化 物層16構成,此層CL覆蓋上述第一導電層12與上述記憶體 单元區域的半導體基底1〇的表面,且上述第二導電層具有451474 V. Description of the invention (1) The present invention relates to a semiconductor conductor integrated circuits (ICs) process technology, in particular to an embedded dynamic random access memory (eDRAM) manufacturing method, which can solve the problem of the dummy guard ring falling off. The conventional logic device and the memory device are respectively formed on different chips and then set on the same board. Due to the structure of memory devices and logic devices formed on different chips, the high speed cannot be guaranteed. Therefore, a device that mixes memory devices and logic devices on the same chip has been proposed. This device is also called embedded Semiconductor memory devices, such as eRAM (embedded Random Access Memory) devices. The following uses part of the process cross-sections shown in Figures 1A to 1D to form a manufacturing process of e D R A Μ using one of the conventional techniques. First, please refer to FIG. 1A, which shows a semiconductor substrate 10 having a memory cell area and a logic circuit area 10. The step of forming the cross section shown in the figure is to 'form a first conductive layer 12 on the surface of the semiconductor substrate 10 in the above-mentioned logic circuit region.' This layer, for example, first comprehensively forms an amorphous silicon (am〇rph〇us s U 1 con) layer, and then selectively engraving a portion of the memory cell region. A second conductive layer CL is then formed on the surface of the first conductive layer 12 comprehensively. The second conductive layer CL is composed of a polycrystalline silicon layer η and a metal silicide layer 16 such as tungsten silicide (WSi). This layer CL covers the first conductive layer The layer 12 and the surface of the semiconductor substrate 10 in the memory cell region, and the second conductive layer has
4514?4 五、發明說明(2) 第一尚度落差D1。接著在上述第二導電層CL的上方形成例 如由氮化矽材料構成的遮蔽物18,其表面具有對應於該第 一高度落差D1的第二高度落差]>2。其次,利用傳統的微影 技術在上述記憶體單元區域欲形成閘極的位置形成光阻罩 幕2 0 〇 接著,請參照第1 B圖,利用光阻罩幕2 0,並且非等向 性钱刻上述遮蔽層1 8直到露出該第二導電層Cl為止,以形 成硬質罩幕(hardmask)18a。此時由於第一導電層CL的表 面具有第一高度落差D1,因此,蝕刻上述遮蔽層18的同時 在第一南度落差D1處會自然地產生不想要的(undesired) 遮蔽物18b。之後,去除上述光阻罩幕2〇。 然後,請參照1 C圖,施以非等向蝕刻法以蝕刻該未被 硬質罩幕18a覆蓋的第二導電層CL,以在上述記憶體單元 區域形成閘極G (由複晶矽14 a與金屬矽化物1 6 a構成)。並 且遮蔽物18b下方會自然地形成一虚置護環GR(redundant guard ring),此護環GR的尺寸難以控制,尺寸過小的的 結果將導致護環GR容易脫落(pee ling),由於脫落的護環 GR通常具有導電性,若是附著在積體電路任何一處,將造 成短路,嚴重影響記憶體元件的性能。 最後,請參照第1 D圖,選擇性蝕刻位於邏輯電路區域 的第一導電層1 2,以形成此區域所需的電晶體閘極1 2 a, 接下來,後續為了形成源極/汲極與增加絕緣能力,在上 述兩區域的閘極G及閘極12a的側壁(side wall)周圍與虛 置護環G R的侧壁周圍形成間隙壁(s p a c e r ) 2 2。當然,後續4514? 4 V. Description of the invention (2) The first degree difference D1. Next, a shield 18 made of, for example, a silicon nitride material is formed on the second conductive layer CL, and its surface has a second height drop corresponding to the first height drop D1] > 2. Secondly, a conventional photolithography technique is used to form a photoresist mask 200 at the position where the gate electrode is to be formed in the memory cell area. Next, referring to FIG. 1B, the photoresist mask 20 is used, and is anisotropic. The masking layer 18 is engraved until the second conductive layer Cl is exposed to form a hard mask 18a. At this time, since the surface of the first conductive layer CL has the first height difference D1, the undesired shield 18b is naturally generated at the first south degree difference D1 while the shielding layer 18 is etched. After that, the photoresist mask 20 is removed. Then, referring to FIG. 1C, an anisotropic etching method is applied to etch the second conductive layer CL that is not covered by the hard mask 18a to form a gate G (composed of polycrystalline silicon 14 a (Composed with metal silicide 1 6 a). In addition, a dummy guard ring GR (redundant guard ring) is formed naturally under the cover 18b. The size of the guard ring GR is difficult to control. As a result of the small size, the guard ring GR is likely to peel off (pee ling). The guard ring GR is generally conductive. If it is attached to any part of the integrated circuit, it will cause a short circuit and seriously affect the performance of the memory element. Finally, referring to FIG. 1D, the first conductive layer 12 in the logic circuit area is selectively etched to form the transistor gate 12a required for this area. Next, in order to form a source / drain To increase the insulation capacity, a spacer 22 is formed around the side walls of the gate G and the gate 12a in the two regions and the side walls of the dummy guard ring GR. Of course, follow-up
45U7445U74
五、發明說明(3) 步驟利用傳統的方式以完成嵌入式動態隨機存取記憶體的 製作。 根據上述習知技術’會產生無法避免的虛置護環GR, 並且其尺寸難以控制’極容易造成脫落而嚴重影響記憶體 元件的性能。 有鑑於此’本發明的目的在於提供一種嵌入式動態隨 機存取記憶體的製造方法’在不增加製程步驟的情況下, 有效地改善上述護環脫落的問題。 根據上述目的’本發明提供一種嵌入式動態隨機存取 記憶體的製造方法’適用於具有一記憶體單元區域與一邏 輯電路區域的半導體基底’上述製造方法包括下列步驟: (a)在該邏輯電路區域的半導體基底表面形成—第一導電 層;(b)形成一第二導電層’其覆蓋該第一導電層與該記 憶體單元區域的半導體基底的表面,且該第二導電層具有 第一高度落差;(c)在該第二導電層表面形成一遮蔽層', 其具有對應於該第一高度落差的第二高度落差;在該 記憶體單元區域欲形成閘極的位置形成一第—光阻罩幕, 同時形成一覆蓋該第二高度落差的位置之第二光阻罩幕; ,及(e)利用該第一與第二光阻罩幕為阻擋物,並且姓刻5. Description of the invention (3) The steps use the traditional method to complete the production of embedded dynamic random access memory. According to the above-mentioned conventional technique ', an unavoidable dummy guard ring GR is generated, and its size is difficult to control', which is extremely likely to cause drop-out and seriously affect the performance of the memory element. In view of this, 'the object of the present invention is to provide a method for manufacturing an embedded dynamic random access memory', which can effectively improve the problem that the guard ring falls off without increasing the number of process steps. According to the above object, the present invention provides a method for manufacturing an embedded dynamic random access memory suitable for a semiconductor substrate having a memory cell region and a logic circuit region. The above manufacturing method includes the following steps: (a) in the logic The first conductive layer is formed on the surface of the semiconductor substrate in the circuit region; (b) a second conductive layer is formed to cover the surface of the semiconductor substrate on the first conductive layer and the memory cell region, and the second conductive layer has a first A height drop; (c) forming a shielding layer 'on the surface of the second conductive layer, which has a second height drop corresponding to the first height drop; forming a first at a position where a gate electrode is to be formed in the memory cell region -A photoresist mask, and simultaneously forming a second photoresist mask covering the position of the second height drop; and (e) using the first and second photoresist masks as a barrier,
層直到露出該第二導電層為止,以形成 X 物與第二遮蔽物。 忙敝 步 第 再者,上述嵌入式動態隨機存取記憶體的製造方法, Ιϋν' 步驟τ列步Ki)去除該第一與 .先阻罩幕;(11)利用第一舆第二遮蔽物為阻擋物,並Layer until the second conductive layer is exposed to form an X object and a second shield. The second step is busy. The above-mentioned manufacturing method of embedded dynamic random access memory, Ιϋν 'step τ step Ki) removes the first and first blocking the curtain; (11) using the first shield and the second shield As a barrier, and
4514?4 五、發明說明(4) 且蝕刻該第二導電層,以在該記憶體單元區域形成閘極與 在第二遮蔽物下方形成〜虛置護環;以及 (iii)選擇 性蝕刻該第一導電層’以在該邏輯電路區域形成閘極。 再者’上述嵌入式動態隨機存取記憶體的製造方法之 中,該第一導電層可以由非晶石夕構成。 再者,上述嵌入式動態隨機存取記憶體的製造方法之 中’ §亥弟一導電層可以由表面形成有金屬石夕化物的複晶妙 層構成。 而且,上述喪入式動態隨機存取記憶體的製造方法, 其中該金屬石夕化物可以是石夕化鑛。 再者,上述嵌入式動態隨機存取記憶體的製造方法之 中,該遮蔽層可以由氮化發構成。 為了讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: v ° 圖式之簡單說明: 第1A圖〜第1 D圖係根據習知技術之一的嵌入式動鲅 機存取記憶體的部分製程剖面圖。 〜 第2A圖〜第2D圖係根據本發明較佳實施例的嵌入 態隨機存取記憶體的部分製程剖面圖。 > 符號之說明 10、1〇〇〜半導體基底。 120〜第一導電層。 120〜邏輯電路區域之閘極。4514? 4 V. Description of the invention (4) The second conductive layer is etched to form a gate electrode in the memory cell region and a dummy guard ring under the second shield; and (iii) selectively etch the The first conductive layer 'forms a gate electrode in the logic circuit region. Furthermore, in the method for manufacturing an embedded dynamic random access memory, the first conductive layer may be composed of amorphous stone. Furthermore, among the above-mentioned manufacturing methods of the embedded dynamic random access memory ', the conductive layer may be composed of a complex crystal layer having a metal oxide compound formed on the surface. In addition, in the method for manufacturing a funnel-type dynamic random access memory described above, the metal petrified material may be a petrified mineral. Furthermore, in the above method for manufacturing an embedded dynamic random access memory, the shielding layer may be made of nitrided hair. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: v ° Brief description of the drawings: Figure 1A Figure 1D is a cross-sectional view of a part of a process for accessing a memory by an embedded mobile computer according to one of the conventional technologies. Figures 2A to 2D are partial process cross-sectional views of an embedded random access memory according to a preferred embodiment of the present invention. > Explanation of symbols 10, 100 to semiconductor substrate. 120 ~ first conductive layer. 120 ~ Gate of logic circuit area.
4〜74 五、發明說明(5) 14 0、14 0 a ~複晶石夕層。 160、160a〜金屬石夕化物層。 CL〜第二導電層。 1 8 0〜遮蔽層。 180a〜第一遮蔽物。 180b~第二遮蔽物。 200a〜第一光阻罩幕。 200b〜第二光阻罩幕。 GR〜虛置護環。 G〜記憶體單元區域的閘極。 實施例 以下利用第〜第2D圖所示之嵌入式(embedded)動態 隨機存取記憶體的部分製程剖面圖,以更詳細地說明本發 明。 首先,請參照第2A圖,該圖顯示具有一記憶體單元區 域(memory cell area)與一邏輯電路區域(logic circuit area)的半導體基底100。形成該圖所示之剖面的步驟為, 在上述邏輯電路區域的半導體基底100表面形成一第一導 電層1 2 0,此層例如先全面性地形成一非晶石夕(amor ph〇us s i 1 i con)層,再選擇性蝕刻掉記憶體單元區域的非晶矽層 部分所形成。然後全面性地在上述第一導電層1 2 〇表面形 成第二導電層CL,其係由複晶矽層140與例如矽化鎢(wSi) 的金屬矽化物層160構成,此層CL覆蓋上述第一導電層120 與上述記憶體單元區域的半導體基底100的表面,且上述4 ~ 74 V. Description of the invention (5) 14 0, 14 0 a ~ polycrystalite layer. 160, 160a ~ metallic oxide layer. CL ~ the second conductive layer. 1 0 0 ~ shielding layer. 180a ~ the first shelter. 180b ~ second shelter. 200a ~ First photoresist mask. 200b ~ second photoresist mask. GR ~ dummy guard ring. G ~ Gate of memory cell area. EXAMPLES Partial process cross-sectional views of the embedded dynamic random access memory shown in Figures 2 to 2D are used below to explain the present invention in more detail. First, please refer to FIG. 2A, which shows a semiconductor substrate 100 having a memory cell area and a logic circuit area. The step of forming the cross section shown in the figure is to form a first conductive layer 120 on the surface of the semiconductor substrate 100 in the above-mentioned logic circuit region. This layer, for example, firstly comprehensively forms an amorphous stone (amor phous si). 1 i con) layer, and then selectively etch away the amorphous silicon layer portion of the memory cell region. Then, a second conductive layer CL is comprehensively formed on the surface of the first conductive layer 120. The second conductive layer CL is composed of a polycrystalline silicon layer 140 and a metal silicide layer 160 such as tungsten silicide (wSi). This layer CL covers the first conductive layer CL. A conductive layer 120 and the surface of the semiconductor substrate 100 in the memory cell region; and
第8頁 4 45 1 47 五、發明說明(6) 第二導電層具有第一高度落差D1。接著在上述第二導電層 CL的上方形成例如由氮化矽材料構成的遮蔽物丨8 〇,其表 面具有對應於該第一高度落差…的第二高度落差…。其 次’利用傳統的微影技術在上述記憶體單元區域欲形成閘 極的位置形成一第一光阻罩幕2〇〇a,同時形成一覆蓋該第 二高度落差D2的位置之第二光阻罩幕2〇〇b,其同時跨過上 述記憶體單元區域與邏輯電路區域。 接著’請參照第2B圖’利用第一光阻罩幕2〇〇a與第二 光阻罩幕200b為阻擋物’並且非等向性蝕刻上述遮蔽層 180直到露出該第二導電層孔為止,以形成第一遮蔽物 180a與第二遮蔽物i8〇b。之後,去除上述第一光阻罩幕 200a與第二光阻罩幕2〇〇b。 然後,請參照第2 C圖,利用上述第一遮蔽物1 8 〇 a與第 二遮蔽物180b為阻擋物’亦即硬質罩幕(hard ,施 行非等向融刻法以蝕刻該未被上述第一、二遮蔽物丨8〇a、 180b覆蓋的第二導電層CL,以在該記憶體單元區域形成開 極G與在第二遮蔽物180b下方形成一虛置護環 GR(redundant guard ring),此護環GR具有既定尺寸,能 夠固定半導體基底100的表面不易脫落,而在此積體電路 之中不具任何功能。而上述記憶體單元區域之閘極G是由 複晶石夕140a與金屬砂化物i6〇a疊層所構成。 最後’請參照第2D圖’選擇性蝕刻位於邏輯電路區域 的第一導電層1 2 0 ’以形成此區域所需的電晶體閘極 1 2 0 a,接下來,後續為了形成源極/丨及極與增加絕緣能Page 8 4 45 1 47 V. Description of the invention (6) The second conductive layer has a first height drop D1. Next, a shield, such as a silicon nitride material, is formed over the second conductive layer CL, and its surface has a second height drop corresponding to the first height drop .... Secondly, using a conventional lithography technique, a first photoresist mask 200a is formed at a position where a gate electrode is to be formed in the memory cell area, and a second photoresist is formed to cover the position of the second height drop D2. The mask 200b crosses the memory cell area and the logic circuit area at the same time. Next, please refer to FIG. 2B. The first photoresist mask 200a and the second photoresist mask 200b are used as barriers, and the shielding layer 180 is anisotropically etched until the second conductive layer hole is exposed. To form a first shield 180a and a second shield i8〇b. After that, the first photoresist mask 200a and the second photoresist mask 200b are removed. Then, referring to FIG. 2C, the above-mentioned first shielding object 180a and the second shielding object 180b are used as a blocking object, that is, a hard mask (hard, an anisotropic melting method is performed to etch the non-isotropic melting method). The second conductive layer CL covered by the first and second shields 8a and 180b to form an open electrode G in the memory cell region and a dummy guard ring GR (redundant guard ring) under the second shield 180b. ), This guard ring GR has a predetermined size, can fix the surface of the semiconductor substrate 100 and is not easy to fall off, and does not have any function in this integrated circuit. The gate G of the above memory cell region is composed of polycrystalline stone 140a and It is composed of metal sand i6〇a stack. Finally, 'please refer to Figure 2D' to selectively etch the first conductive layer 1 2 0 'located in the logic circuit area to form the transistor gate 1 2 0 a Next, in order to form the source / 丨 and the electrode and increase the insulation energy
IIH 第9頁 4?4 五、發明說明(7) 力’在上述兩區域的閘極G及閘極12〇a的側壁(side wall) 周圍與虛置護環GR的侧壁周圍形成間隙壁(spacer)220。 當然,後續步驟利用傳統的方式以完成嵌入式動態隨機存 取記憶體的製作。 本發明實施例是以嵌入式動態隨機存取記憶體為例, 然而本發明的方法不限於此’任何具有高度落差的嵌入式 半導體元件皆可適用。 發明特徵與功效 本發明的特徵在於,形成用於記憶體單元區域之閘極 蝕刻用罩幕(第一光阻罩幕2〇〇3)的同時,形成第二光阻罩 幕2 0 0b ’以便在接下來的步驟形成能夠固定於半導體基底 表面,而不易脫落的虛置護環。 根據本發明的製造方法,不需要增加製程步驟僅需要 變更光罩的圖案設計,即能夠有效地改善上述護環脫落的 問題。 雖然本發明已以較佳實施例揭露如上,然其並非用以 ^發明,任何熟習此項技藝者,在不脫離本發明之精 έ圍内’ s可作更動與潤飾,因此 明之保護 當視後附之申請專利範圍所界定者為準。IIH Page 9 4? 4 V. Description of the invention (7) The force 'forms a gap wall around the side wall of the gate G and the gate 12a of the two regions and the side wall of the dummy guard ring GR. (Spacer) 220. Of course, the subsequent steps use traditional methods to complete the production of embedded dynamic random access memory. The embodiment of the present invention is based on the embedded dynamic random access memory as an example. However, the method of the present invention is not limited thereto. Any embedded semiconductor device having a high dropout can be applied. Features and Effects of the Invention The present invention is characterized by forming a second photoresist mask 2 0 0b ′ while forming a gate etching mask (first photoresist mask 2003) for a memory cell region. In order to form a dummy guard ring which can be fixed on the surface of the semiconductor substrate and is not easy to fall off in the next step. According to the manufacturing method of the present invention, there is no need to increase the number of manufacturing steps, and only the pattern design of the photomask needs to be changed, that is, the problem of the guard ring falling off can be effectively improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to invent the invention. Any person skilled in the art can make changes and retouches without departing from the spirit of the present invention. The appended application patent shall prevail.
第10頁Page 10
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW089114505A TW451474B (en) | 2000-07-20 | 2000-07-20 | Manufacturing method of embedded type dynamic random access memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW089114505A TW451474B (en) | 2000-07-20 | 2000-07-20 | Manufacturing method of embedded type dynamic random access memory |
Publications (1)
Publication Number | Publication Date |
---|---|
TW451474B true TW451474B (en) | 2001-08-21 |
Family
ID=21660487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW089114505A TW451474B (en) | 2000-07-20 | 2000-07-20 | Manufacturing method of embedded type dynamic random access memory |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW451474B (en) |
-
2000
- 2000-07-20 TW TW089114505A patent/TW451474B/en not_active IP Right Cessation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7759239B1 (en) | Method of reducing a critical dimension of a semiconductor device | |
CN101256939B (en) | Structure and IC manufacturing method | |
US8119470B2 (en) | Mitigation of gate to contact capacitance in CMOS flow | |
CN102956459B (en) | Semiconductor device and manufacture method thereof | |
US20160211344A1 (en) | Modified self-aligned contact process and semiconductor device | |
CN112086433A (en) | Semiconductor element and method for manufacturing the same | |
KR100190365B1 (en) | Semiconductor device manufacturing of photomask & forming method thereof | |
TW451474B (en) | Manufacturing method of embedded type dynamic random access memory | |
JP3141010B2 (en) | Manufacturing method of memory cell | |
US7429527B2 (en) | Method of manufacturing self-aligned contact openings | |
KR100480894B1 (en) | A method for manufacturing of merged memory logic in semiconductor device | |
US9620619B2 (en) | Borderless contact structure | |
TWI236072B (en) | Multilevel poly-Si tiling for semiconductor circuit manufacture | |
KR101068637B1 (en) | Method for fabrication semiconductor device having triple gate-spacer | |
US6521522B2 (en) | Method for forming contact holes for metal interconnection in semiconductor devices | |
KR100480586B1 (en) | Manufacturing Method of Semiconductor Device Having Local Silicide Film | |
KR101119158B1 (en) | Method for forming semiconductor device | |
KR20070001590A (en) | Method for forming recessed gate of semiconductor device | |
KR100243738B1 (en) | Method for manufacturing semiconductor device | |
KR100292052B1 (en) | Method for manufacturing semiconductor device | |
TW483114B (en) | Local formation method of metal silicide | |
KR100453917B1 (en) | Fabrication method of gate in semiconductor device | |
US6660594B2 (en) | Methods of forming integrated circuit devices having gate oxide layers with different thicknesses and integrated circuit devices formed thereby | |
KR20070069957A (en) | Method for manufacturing conducting layer pattern on the semiconductor device | |
TW469531B (en) | Method for forming trench conductive traces by ion metal plasma deposition method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |