TW451474B - Manufacturing method of embedded type dynamic random access memory - Google Patents

Abstract

The present invention provides the manufacturing method of embedded type dynamic random access memory. First, the first conducting layer is formed on the semiconductor substrate surface of the logic circuit region. Then, the second conducting layer is formed to cover the first conducting layer and the semiconductor substrate surface of memory cell region. In addition, the second conducting layer has the first height drop. After that, a shielding layer, which has the second height drop corresponding to the first height drop, is formed on the second conducting layer surface. The first photoresist mask is formed at the position that is desired for forming the gate on the memory cell region. The second photoresist mask is formed at the same time to cover the position of the second height drop. By using the first and the second photoresist masks as the blocking materials, the shielding layer is etched until the second conducting layer is exposed so as to form the first blocking material and the second blocking material. Based on the manufacturing method of this invention, the falling off problem of guard-ring can be effectively solved under the condition that the step of process is not increased.

Description

451474 V. Description of the invention (1) The present invention relates to a semiconductor conductor integrated circuits (ICs) process technology, in particular to an embedded dynamic random access memory (eDRAM) manufacturing method, which can solve the problem of the dummy guard ring falling off. The conventional logic device and the memory device are respectively formed on different chips and then set on the same board. Due to the structure of memory devices and logic devices formed on different chips, the high speed cannot be guaranteed. Therefore, a device that mixes memory devices and logic devices on the same chip has been proposed. This device is also called embedded Semiconductor memory devices, such as eRAM (embedded Random Access Memory) devices. The following uses part of the process cross-sections shown in Figures 1A to 1D to form a manufacturing process of e D R A Μ using one of the conventional techniques. First, please refer to FIG. 1A, which shows a semiconductor substrate 10 having a memory cell area and a logic circuit area 10. The step of forming the cross section shown in the figure is to 'form a first conductive layer 12 on the surface of the semiconductor substrate 10 in the above-mentioned logic circuit region.' This layer, for example, first comprehensively forms an amorphous silicon (am〇rph〇us s U 1 con) layer, and then selectively engraving a portion of the memory cell region. A second conductive layer CL is then formed on the surface of the first conductive layer 12 comprehensively. The second conductive layer CL is composed of a polycrystalline silicon layer η and a metal silicide layer 16 such as tungsten silicide (WSi). This layer CL covers the first conductive layer The layer 12 and the surface of the semiconductor substrate 10 in the memory cell region, and the second conductive layer has

4514? 4 V. Description of the invention (2) The first degree difference D1. Next, a shield 18 made of, for example, a silicon nitride material is formed on the second conductive layer CL, and its surface has a second height drop corresponding to the first height drop D1] > 2. Secondly, a conventional photolithography technique is used to form a photoresist mask 200 at the position where the gate electrode is to be formed in the memory cell area. Next, referring to FIG. 1B, the photoresist mask 20 is used, and is anisotropic. The masking layer 18 is engraved until the second conductive layer Cl is exposed to form a hard mask 18a. At this time, since the surface of the first conductive layer CL has the first height difference D1, the undesired shield 18b is naturally generated at the first south degree difference D1 while the shielding layer 18 is etched. After that, the photoresist mask 20 is removed. Then, referring to FIG. 1C, an anisotropic etching method is applied to etch the second conductive layer CL that is not covered by the hard mask 18a to form a gate G (composed of polycrystalline silicon 14 a (Composed with metal silicide 1 6 a). In addition, a dummy guard ring GR (redundant guard ring) is formed naturally under the cover 18b. The size of the guard ring GR is difficult to control. As a result of the small size, the guard ring GR is likely to peel off (pee ling). The guard ring GR is generally conductive. If it is attached to any part of the integrated circuit, it will cause a short circuit and seriously affect the performance of the memory element. Finally, referring to FIG. 1D, the first conductive layer 12 in the logic circuit area is selectively etched to form the transistor gate 12a required for this area. Next, in order to form a source / drain To increase the insulation capacity, a spacer 22 is formed around the side walls of the gate G and the gate 12a in the two regions and the side walls of the dummy guard ring GR. Of course, follow-up

45U74

5. Description of the invention (3) The steps use the traditional method to complete the production of embedded dynamic random access memory. According to the above-mentioned conventional technique ', an unavoidable dummy guard ring GR is generated, and its size is difficult to control', which is extremely likely to cause drop-out and seriously affect the performance of the memory element. In view of this, 'the object of the present invention is to provide a method for manufacturing an embedded dynamic random access memory', which can effectively improve the problem that the guard ring falls off without increasing the number of process steps. According to the above object, the present invention provides a method for manufacturing an embedded dynamic random access memory suitable for a semiconductor substrate having a memory cell region and a logic circuit region. The above manufacturing method includes the following steps: (a) in the logic The first conductive layer is formed on the surface of the semiconductor substrate in the circuit region; (b) a second conductive layer is formed to cover the surface of the semiconductor substrate on the first conductive layer and the memory cell region, and the second conductive layer has a first A height drop; (c) forming a shielding layer 'on the surface of the second conductive layer, which has a second height drop corresponding to the first height drop; forming a first at a position where a gate electrode is to be formed in the memory cell region -A photoresist mask, and simultaneously forming a second photoresist mask covering the position of the second height drop; and (e) using the first and second photoresist masks as a barrier,

Layer until the second conductive layer is exposed to form an X object and a second shield. The second step is busy. The above-mentioned manufacturing method of embedded dynamic random access memory, Ιϋν 'step τ step Ki) removes the first and first blocking the curtain; (11) using the first shield and the second shield As a barrier, and

4514? 4 V. Description of the invention (4) The second conductive layer is etched to form a gate electrode in the memory cell region and a dummy guard ring under the second shield; and (iii) selectively etch the The first conductive layer 'forms a gate electrode in the logic circuit region. Furthermore, in the method for manufacturing an embedded dynamic random access memory, the first conductive layer may be composed of amorphous stone. Furthermore, among the above-mentioned manufacturing methods of the embedded dynamic random access memory ', the conductive layer may be composed of a complex crystal layer having a metal oxide compound formed on the surface. In addition, in the method for manufacturing a funnel-type dynamic random access memory described above, the metal petrified material may be a petrified mineral. Furthermore, in the above method for manufacturing an embedded dynamic random access memory, the shielding layer may be made of nitrided hair. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: v ° Brief description of the drawings: Figure 1A Figure 1D is a cross-sectional view of a part of a process for accessing a memory by an embedded mobile computer according to one of the conventional technologies. Figures 2A to 2D are partial process cross-sectional views of an embedded random access memory according to a preferred embodiment of the present invention. > Explanation of symbols 10, 100 to semiconductor substrate. 120 ~ first conductive layer. 120 ~ Gate of logic circuit area.

4 ~ 74 V. Description of the invention (5) 14 0, 14 0 a ~ polycrystalite layer. 160, 160a ~ metallic oxide layer. CL ~ the second conductive layer. 1 0 0 ~ shielding layer. 180a ~ the first shelter. 180b ~ second shelter. 200a ~ First photoresist mask. 200b ~ second photoresist mask. GR ~ dummy guard ring. G ~ Gate of memory cell area. EXAMPLES Partial process cross-sectional views of the embedded dynamic random access memory shown in Figures 2 to 2D are used below to explain the present invention in more detail. First, please refer to FIG. 2A, which shows a semiconductor substrate 100 having a memory cell area and a logic circuit area. The step of forming the cross section shown in the figure is to form a first conductive layer 120 on the surface of the semiconductor substrate 100 in the above-mentioned logic circuit region. This layer, for example, firstly comprehensively forms an amorphous stone (amor phous si). 1 i con) layer, and then selectively etch away the amorphous silicon layer portion of the memory cell region. Then, a second conductive layer CL is comprehensively formed on the surface of the first conductive layer 120. The second conductive layer CL is composed of a polycrystalline silicon layer 140 and a metal silicide layer 160 such as tungsten silicide (wSi). This layer CL covers the first conductive layer CL. A conductive layer 120 and the surface of the semiconductor substrate 100 in the memory cell region; and

Page 8 4 45 1 47 V. Description of the invention (6) The second conductive layer has a first height drop D1. Next, a shield, such as a silicon nitride material, is formed over the second conductive layer CL, and its surface has a second height drop corresponding to the first height drop .... Secondly, using a conventional lithography technique, a first photoresist mask 200a is formed at a position where a gate electrode is to be formed in the memory cell area, and a second photoresist is formed to cover the position of the second height drop D2. The mask 200b crosses the memory cell area and the logic circuit area at the same time. Next, please refer to FIG. 2B. The first photoresist mask 200a and the second photoresist mask 200b are used as barriers, and the shielding layer 180 is anisotropically etched until the second conductive layer hole is exposed. To form a first shield 180a and a second shield i8〇b. After that, the first photoresist mask 200a and the second photoresist mask 200b are removed. Then, referring to FIG. 2C, the above-mentioned first shielding object 180a and the second shielding object 180b are used as a blocking object, that is, a hard mask (hard, an anisotropic melting method is performed to etch the non-isotropic melting method). The second conductive layer CL covered by the first and second shields 8a and 180b to form an open electrode G in the memory cell region and a dummy guard ring GR (redundant guard ring) under the second shield 180b. ), This guard ring GR has a predetermined size, can fix the surface of the semiconductor substrate 100 and is not easy to fall off, and does not have any function in this integrated circuit. The gate G of the above memory cell region is composed of polycrystalline stone 140a and It is composed of metal sand i6〇a stack. Finally, 'please refer to Figure 2D' to selectively etch the first conductive layer 1 2 0 'located in the logic circuit area to form the transistor gate 1 2 0 a Next, in order to form the source / 丨 and the electrode and increase the insulation energy

IIH Page 9 4? 4 V. Description of the invention (7) The force 'forms a gap wall around the side wall of the gate G and the gate 12a of the two regions and the side wall of the dummy guard ring GR. (Spacer) 220. Of course, the subsequent steps use traditional methods to complete the production of embedded dynamic random access memory. The embodiment of the present invention is based on the embedded dynamic random access memory as an example. However, the method of the present invention is not limited thereto. Any embedded semiconductor device having a high dropout can be applied. Features and Effects of the Invention The present invention is characterized by forming a second photoresist mask 2 0 0b ′ while forming a gate etching mask (first photoresist mask 2003) for a memory cell region. In order to form a dummy guard ring which can be fixed on the surface of the semiconductor substrate and is not easy to fall off in the next step. According to the manufacturing method of the present invention, there is no need to increase the number of manufacturing steps, and only the pattern design of the photomask needs to be changed, that is, the problem of the guard ring falling off can be effectively improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to invent the invention. Any person skilled in the art can make changes and retouches without departing from the spirit of the present invention. The appended application patent shall prevail.

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Claims (1)

6. Scope of Patent Application 1—A method for manufacturing an embedded dynamic random access memory, which is applicable to the semiconductor substrate of the memory cell area and a logic circuit area. The method includes the following ... (a) in A first conductive layer is formed on the surface of the semiconductor substrate in the edge circuit region; (b) a second conductive layer is formed to cover the first conductive layer and the surface of the semiconductor substrate in the memory cell region; and the second The conductive layer has a first height drop, (c) a shielding layer is formed on the surface of the second conductive layer, which has a second height drop corresponding to the first height drop; (d) a gate is to be formed in the memory cell area; A first photoresist mask is formed at the pole position, and a second photoresist mask covering the position of the second height difference is formed at the same time; and (e) using the first and second photoresist masks as a barrier, And the shielding layer is etched until the second conductive layer is exposed to form a first shielding object and a second shielding object. J style fan! The embedded dynamic random storage described in the above item (i) removing the first and second photo-blocking steps includes the following steps: (丄 i) using the first and second shields two conductive layers to locate the memory cell area Shape ::: and a dummy guard ring is formed under the first object; and the electrode and the first conductive region are selectively etched to form a gate electrode. u in the logic circuit area Page 11 6. Scope of Patent Application 3. The manufacturing method of the scattered dynamic random access memory described in item 1 of the scope of patent application, wherein the first conductive layer is composed of amorphous silicon. 4. The manufacturing method of the embedded dynamic random access memory according to item 1 of the scope of the patent application, wherein the second conductive layer is composed of a polycrystalline silicon layer having a metal silicide formed on the surface. 5. The manufacturing method of the embedded dynamic random access memory according to item 4 of the scope of the patent application, wherein the metal silicide is tungsten silicide. 6. The method for manufacturing an embedded dynamic random access memory according to item 1 of the scope of the patent application, wherein the shielding layer is made of silicon nitride. Page 12