TW469531B - Method for forming trench conductive traces by ion metal plasma deposition method - Google Patents

Abstract

A method for manufacturing trench conductive traces comprises the steps of: first, forming a barrier layer, such as an oxide layer, on a semiconductor substrate, and forming a trench by a microlithography and etching step, such as patterning by dry etching; then, applying an IMP process to deposit a silicon layer at the bottom of the trench in a manner of being vertical with respect with the substrate and on the patterned barrier layer, wherein no silicon layer is formed on the sidewall of the trench in this step; after ion implantation, applying a thermal annealing process so as to drive the conductive impurities into the semiconductor substrate, thereby forming a buried conductive area on the semiconductor substrate at the bottom of the trench; and finally, removing the barrier layer/silicon layer by a chemical mechanical polishing process or by using wet etching liquid to remove the barrier layer.

Description

469531 V. Description of the invention α) Field of the invention: The present invention relates to the semiconductor manufacturing process, in particular to a method that uses ionic metal plasma deposition method, ion implantation and thermal annealing to drive ions into the semiconductor substrate under the bottom of the trench to form conductivity. Take the method. 1 Background of the Invention: With the advancement of integrated circuit manufacturing processes, it has become a trend for high-density components to be formed on a wafer. Especially the development of memory cell manufacturing technology, only the extreme of high density can have strong competitiveness. However, with the increase in the number of elements in the integrated circuit, the cross-sectional area of the component and the wires connected to it decreases, so the resistance increases. To solve this problem, buried bit lines are used. It is a typical solution to have high conductivity impurities and increase the buried bit line thickness or semiconductor depth direction. Fig. 1 shows the fabrication of a mask-type read-only memory ROM manufactured by a conventional method. There are buried bit lines 12, 14, and 16 in the semiconductor substrate. The manufacturing method is briefly described as follows. First, an appropriate mask is used for ion implantation to form an ion-doped region, and then the substrate 10 is annealed in a high-temperature oxidation environment to activate the conductive impurities of the bit lines, and at the same time, the oxide layer is oxidized. It is also formed that the oxide layer includes a thin gate oxide layer 30 located above the channel regions 2 2 and 2 4, and a thick oxide layer 32 located above 1 2, 1 4 and 16. The thicker oxide layer 3 2 is due to the n-type of the bit line

Page 4 Δ 6 95 3 — ____ V. Description of the invention (2) After conductive impurities promote high temperature oxidation,-doped with conductive impurities Day :, then. The oxide layer is formed and patterned to form a gold oxide layer # 日 日 日 J I is then formed on the oxide layer 32, and the solar gate electrode 18 is formed. r. J 3 mention Γ ,. The word line of the curtain read-only memory (w ° rd 1 ines) 々 oxide layer "32 is formed by a thermal oxidation process, and the conductivity of the bit line" β; will spread outward in the soil environment of "«. Therefore, the shortcomings of this kind of device must not be too close to the bit line, otherwise the punch through effect may occur under normal operating voltage as long as the size of the device is reduced. The smaller the line width, the larger the resistance value. This will make the read-only memory read and write speed slower. Therefore, it is necessary to change the structure of the components, so that the size can be kept good while reducing the size. The performance of the component. The buried bit line under the trench combined with the ion-metal plasma process (IMP process for short) should be a solution to overcome the above difficulties. Because the MP process can accurately control the buried guide i The location of the electrical area, without the need for complicated manufacturing processes. j Purpose and summary of the invention: The purpose of the present invention is to provide a new method for manufacturing trench conductor tapes with the effect of preventing penetration due to the reduction in component size.

Page 5 V. Description of the invention (3) The present invention discloses a method for manufacturing a trench wire strip. The method of the present invention includes the following steps. First, a barrier layer such as an oxide layer is first formed on a semiconductor substrate, and then patterned to form trenches by lithography and etching steps such as dry etching. Then, an IMP process is applied to form a trench. A silicon layer is deposited perpendicular to the direction of the semiconductor substrate on the bottom of the trench and above the patterned barrier layer. In this step, no silicon layer is formed on the sidewall of the trench. After ion implantation, thermal annealing is applied to drive conductive impurities into the semiconductor substrate, and a buried conductive region is formed in the semiconductor substrate under the bottom of the trench. Finally, the barrier layer / silicon layer is removed by a chemical / mechanical polishing process or the immersion etching solution is used to remove the barrier layer, so that the silicon layer thereon loses support, and the barrier layer / fragment layer is removed together. . Detailed description of the invention: I..

[Please refer to the cross-section diagram shown in Figure 2. First, a barrier layer I Π 0 is formed on a semiconductor substrate 100. The function of the barrier layer Π 0 is to serve as a hard mask to form a trench and to prevent ion implantation from entering the semiconductor substrate 100 during annealing, as described in detail later. The barrier layer 110 includes a silicon oxide layer or a thin hafnium oxide layer / nitride layer. In a preferred embodiment, the barrier layer has a thickness of 30 to 300 nm. One of the barrier layers is formed by a chemical vapor deposition method or a thermal oxidation method to form a semiconductor substrate 100 I. A lithography process and a plasma etch are then performed to pattern the barrier

Page 6 469531 i V. Description of the invention (4) The layer 11 0, and then the semiconductor substrate 1 00 is etched by the patterned barrier layer 11 0 to form a trench 1 1 5 with a depth of about 1 0 0 To 400 nm. An ionic metal plasma deposition method is then performed to deposit a conductor layer 120, including a polycrystalline silicon layer, a polycrystalline silicon / tungsten metal layer, or a titanium nitride or tungsten metal.

One of the I layers is formed on the bottom of the barrier layer 110 and the trench Π 5. Ion gold | Iron plasma deposition is a process similar to sputtering. First, silicon or refractory metal is first ionized into silicon ions or metal ions, and then the ions are biased and deposited in a specific direction. Horizontal surface of a semiconductor substrate. It is not deposited on the side walls of the trench during the ionic metal plasma deposition step. Therefore, it can be predicted that the critical size for the trench size will be easy. In addition, it can also be less prone to the problem of penetration of the source-drain region due to lateral diffusion. Therefore, as shown in FIG. 3, an n-type or p-type conductive impurity enters the ion implantation (as shown by the arrow) as shown in the figure and is implanted in the conductor layer 120 to form the implantation as shown in the figure. Layer 1 2 0. In a preferred embodiment, if the n-type ions are implanted, arsenic or phosphorus can be implanted. If the p-type ions are implanted, boron or BF 2 ions can be implanted. Depending on the need to form an n-type or p-type conductive layer. A high-temperature thermal oxidation process is followed by ion implantation. The conductive layer at the bottom of the trench enters the semiconductor substrate 100 to form a buried conductive tape 13 0 and a metal silicide. If the previous conductive layer 120 is a fire metal

Page 7 469531 V. Description of the invention (5). At this time, impurities will be activated by annealing. The annealing temperature is preferably about 700 to 900 ° C. During the annealing process, the ions on the conductor layer on the banks of the trenches 5 are not blocked by the barrier layer 110 and are not driven into the semiconductor substrate 10. The conductive strip 130 and the conductive layer 120 can be used as component bit lines. For example, the component can be dynamic random access memory, draped read-only memory or other memory cell components, depending on the type of the component. However, since this part is out of the scope of the present invention, the manufacturing steps of the matched components will be omitted here.

I j Finally, a wet-etching process is performed next to remove the barrier layer Π 0 and remove it due to the loss of support. For the results, please refer to the schematic diagram of the cross-section I shown in Figure 5. Another way is to use chemical / mechanical The polishing process is used to remove the conductive layer 12 on the banks of the trench 115, and the barrier layer 110 is used as an etching stop layer. Spreading to the bottom of the transverse heterogeneous conductance part: the lower part of the trench is only limited to the point where the electrical conductance is limited — _ I Ming C The penetration of the original question is so large that it can not be measured. The less the problem is, the less the problem is, the less the problem is, the less the ratio is. The ruler can be used to reduce the number of channels and grooves. || It is the system of 2 C. The silicon 2 surface 1 or the surface layer of the ship is added with gold to increase the usefulness. It will not} not 3 but C, 'This sedimentation method accumulates sedimentary electricity is gold β 0 to. Because of this, the wall side trench is formed in layer 469531. 5. Description of the invention (6) 丨 Some special benefits, such as no mushroom side on the side wall of the trench, especially when the conductor layer is thick, in addition, the conductor must be connected. Layer 1 2 0 will also be easier. (4) The mask of the present invention needs only one time, so the manufacturing process is simple. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 9 469531 Schematic illustration of the preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figures: Figure 1 shows a conventional method for manufacturing a mask with buried bit lines Schematic diagram of the cross-section of a read-only memory (MASK ROM). FIG. 2 is a schematic cross-sectional view of forming a barrier layer and then lithography and etching to form a trench according to the method of the present invention. FIG. 3 is a schematic cross-sectional view of an IMP process and ion implantation according to the method of the present invention. Figure 4 shows a schematic cross-sectional view of the method according to the invention after thermal annealing. Figure 5 shows a schematic cross-sectional view of the method according to the invention after removing the barrier layer.

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Claims (1)

46 95 3 1_ I. Scope of patent application 1. A method for manufacturing a conductive tape using ionic metal plasma deposition, the method includes at least the following steps: forming a barrier layer on a substrate; patterning the resist through lithography and etching The barrier layer defines a trench; the patterned barrier layer is used as a hard mask to etch the substrate to form the trench; a conductor layer is deposited in a specific direction on the barrier layer and the bottom of the trench; an ion cloth is applied A conductive impurity is implanted in the conductor layer; and a thermal annealing process is performed to drive the conductive impurity into a substrate under the bottom of the trench to form a conductive tape. ! 2. The method according to item 1 of the scope of patent application, wherein the above substrate contains at least one rare substrate. 3. The method according to item 1 of the scope of patent application, wherein the above barrier layer includes at least an oxide layer and a gasified stone layer. 4. The method according to item 1 of the patent application range, wherein the above barrier layer includes at least a monoxide layer. 5. The method according to item 1 of the patent application range, wherein the above-mentioned specific direction deposition is deposited by an ion metal plasma deposition method. Page II 4 6 9 b 3 1 VI. Application for Patent Scope 6. For the method of applying for the scope of the first item of the patent scope, wherein the above-mentioned conductor layer includes at least one yin guang, multiple crystalline yin xi layer or a rich metal layer One kind. 7. The method of claim 1 in which the above-mentioned conductive impurities are one of the groups consisting of free boron, BF 2+, arsenic, or phosphorus atoms. 8. The method according to item 1 of the patent application range, wherein the above-mentioned thermal annealing temperature is performed at a temperature between 700 and 900 ° C. 9. A method for manufacturing a conductive tape using ionic metal plasma deposition, the method comprising at least the following steps: forming a barrier layer on a semiconductor substrate; patterning the barrier layer through lithography and etching to define a trench; using the The patterned barrier layer is a hard mask to etch the semiconductor substrate to form the ditch, and a silicon layer is deposited on the barrier layer and the bottom of the trench by an ion metal plasma deposition method; an ion implantation is applied. Conductive impurities are implanted on the silicon layer; and a thermal annealing process is performed to drive the conductive impurities into the semiconductor substrate under the bottom of the trench to form a conductive strip; and chemically / mechanically polished Process to remove the silicon layer / barrier layer. I 1 0 The method according to item 9 of the scope of patent application, wherein the above barrier layer includes at least an oxide layer and a nitride layer. Page 12 469531 VI. Scope of patent application I 1 1. The method according to item 9 of the scope of patent application, wherein the above barrier layer includes at least a layer of oxide. 1 2. The method according to item 9 of the scope of patent application, wherein the above-mentioned conductive impurity | is one of the groups consisting of free boron, BF 2+, arsenic or phosphorus atoms. 1 3. The method according to item 9 of the scope of patent application, wherein the above-mentioned thermal annealing temperature is performed at a temperature between 700 and 900 ° C. Page 13