TW293105B - - Google Patents

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Publication number
TW293105B
TW293105B TW085105158A TW85105158A TW293105B TW 293105 B TW293105 B TW 293105B TW 085105158 A TW085105158 A TW 085105158A TW 85105158 A TW85105158 A TW 85105158A TW 293105 B TW293105 B TW 293105B
Authority
TW
Taiwan
Prior art keywords
bus
microprocessor
processor
memory
computer system
Prior art date
Application number
TW085105158A
Other languages
English (en)
Chinese (zh)
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW293105B publication Critical patent/TW293105B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083Power or thermal control instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3287Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1028Power efficiency
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
  • Power Sources (AREA)
TW085105158A 1994-12-23 1996-04-30 TW293105B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/363,735 US5530932A (en) 1994-12-23 1994-12-23 Cache coherent multiprocessing computer system with reduced power operating features

Publications (1)

Publication Number Publication Date
TW293105B true TW293105B (enExample) 1996-12-11

Family

ID=23431494

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085105158A TW293105B (enExample) 1994-12-23 1996-04-30

Country Status (10)

Country Link
US (1) US5530932A (enExample)
EP (1) EP0799444B1 (enExample)
KR (1) KR987001105A (enExample)
CN (1) CN1145869C (enExample)
AU (1) AU4962196A (enExample)
BR (1) BR9510532A (enExample)
IL (1) IL116353A (enExample)
RU (1) RU2171490C2 (enExample)
TW (1) TW293105B (enExample)
WO (1) WO1996032671A1 (enExample)

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US7424576B2 (en) * 2001-05-02 2008-09-09 Intel Corporation Parallel cachelets
US6976181B2 (en) * 2001-12-20 2005-12-13 Intel Corporation Method and apparatus for enabling a low power mode for a processor
US7165135B1 (en) * 2002-04-18 2007-01-16 Advanced Micro Devices, Inc. Method and apparatus for controlling interrupts in a secure execution mode-capable processor
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US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US6922756B2 (en) * 2002-12-19 2005-07-26 Intel Corporation Forward state for use in cache coherency in a multiprocessor system
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US7689848B2 (en) * 2004-06-21 2010-03-30 Koninklijke Philips Electronics N.V. Power management adapted to compute average length of time that a processor is idle during each processing cycle from synchronization signals
US7685365B2 (en) * 2004-09-30 2010-03-23 Intel Corporation Transactional memory execution utilizing virtual memory
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JP4286826B2 (ja) * 2004-10-15 2009-07-01 株式会社ソニー・コンピュータエンタテインメント マルチプロセッサシステムで多重構成をサポートする方法及び装置
WO2006045790A1 (de) * 2004-10-25 2006-05-04 Robert Bosch Gmbh Verfahren und vorrichtung zur modusumschaltung und zum signalvergleich bei einem rechnersystem mit wenigstens zwei verarbeitungseinheiten
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US7502948B2 (en) 2004-12-30 2009-03-10 Intel Corporation Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores
RU2290706C1 (ru) * 2005-05-14 2006-12-27 Научно-исследовательский институт системных исследований Российской Академии Наук Устройство чтения из кэш-памяти
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US7870337B2 (en) * 2007-11-28 2011-01-11 International Business Machines Corporation Power-aware line intervention for a multiprocessor snoop coherency protocol
US8266337B2 (en) * 2007-12-06 2012-09-11 International Business Machines Corporation Dynamic logical data channel assignment using channel bitmap
US8010822B2 (en) * 2008-03-28 2011-08-30 Microsoft Corporation Power-aware thread scheduling and dynamic use of processors
US8725953B2 (en) * 2009-01-21 2014-05-13 Arm Limited Local cache power control within a multiprocessor system
US8566628B2 (en) * 2009-05-06 2013-10-22 Advanced Micro Devices, Inc. North-bridge to south-bridge protocol for placing processor in low power state
US20110112798A1 (en) * 2009-11-06 2011-05-12 Alexander Branover Controlling performance/power by frequency control of the responding node
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CN101958834B (zh) * 2010-09-27 2012-09-05 清华大学 支持高速缓存一致的片上网络系统及数据请求方法
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JP5699756B2 (ja) * 2011-03-31 2015-04-15 富士通株式会社 情報処理装置及び情報処理装置制御方法
US8934279B2 (en) * 2011-05-16 2015-01-13 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space
US8949514B2 (en) * 2011-05-16 2015-02-03 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for both code and data space
US9910823B2 (en) * 2011-05-16 2018-03-06 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetch
US9588881B2 (en) 2011-05-16 2017-03-07 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses
WO2011157136A2 (zh) * 2011-05-31 2011-12-22 华为技术有限公司 一种数据管理方法、装置及数据芯片
US20130117511A1 (en) * 2011-11-08 2013-05-09 Arm Limited Data processing apparatus and method
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CN104657286B (zh) * 2013-11-19 2019-05-10 中兴通讯股份有限公司 一种分级存储方法及装置
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Also Published As

Publication number Publication date
IL116353A (en) 1999-03-12
EP0799444A1 (en) 1997-10-08
CN1145869C (zh) 2004-04-14
AU4962196A (en) 1996-10-30
IL116353A0 (en) 1996-03-31
CN1171159A (zh) 1998-01-21
KR987001105A (ko) 1998-04-30
EP0799444A4 (en) 1998-03-25
BR9510532A (pt) 1998-07-14
US5530932A (en) 1996-06-25
EP0799444B1 (en) 2003-12-03
WO1996032671A1 (en) 1996-10-17
HK1003667A1 (en) 1998-11-06
RU2171490C2 (ru) 2001-07-27

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