BR9510532A - Sistema de computador de múltiplos processadores com coerência de cache possuindo características operacionais de redução de energia - Google Patents

Sistema de computador de múltiplos processadores com coerência de cache possuindo características operacionais de redução de energia

Info

Publication number
BR9510532A
BR9510532A BR9510532A BR9510532A BR9510532A BR 9510532 A BR9510532 A BR 9510532A BR 9510532 A BR9510532 A BR 9510532A BR 9510532 A BR9510532 A BR 9510532A BR 9510532 A BR9510532 A BR 9510532A
Authority
BR
Brazil
Prior art keywords
cache
computer system
processor computer
operational power
saving features
Prior art date
Application number
BR9510532A
Other languages
English (en)
Portuguese (pt)
Inventor
John Crawford
Douglas M Carmean
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR9510532A publication Critical patent/BR9510532A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
  • Power Sources (AREA)
BR9510532A 1994-12-23 1995-12-20 Sistema de computador de múltiplos processadores com coerência de cache possuindo características operacionais de redução de energia BR9510532A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/363,735 US5530932A (en) 1994-12-23 1994-12-23 Cache coherent multiprocessing computer system with reduced power operating features
PCT/US1995/016601 WO1996032671A1 (en) 1994-12-23 1995-12-20 A cache coherent multiprocessing computer system with reduced power operating features

Publications (1)

Publication Number Publication Date
BR9510532A true BR9510532A (pt) 1998-07-14

Family

ID=23431494

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9510532A BR9510532A (pt) 1994-12-23 1995-12-20 Sistema de computador de múltiplos processadores com coerência de cache possuindo características operacionais de redução de energia

Country Status (10)

Country Link
US (1) US5530932A (enExample)
EP (1) EP0799444B1 (enExample)
KR (1) KR987001105A (enExample)
CN (1) CN1145869C (enExample)
AU (1) AU4962196A (enExample)
BR (1) BR9510532A (enExample)
IL (1) IL116353A (enExample)
RU (1) RU2171490C2 (enExample)
TW (1) TW293105B (enExample)
WO (1) WO1996032671A1 (enExample)

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5669003A (en) * 1994-12-23 1997-09-16 Intel Corporation Method of monitoring system bus traffic by a CPU operating with reduced power
US5752045A (en) * 1995-07-14 1998-05-12 United Microelectronics Corporation Power conservation in synchronous SRAM cache memory blocks of a computer system
US5713029A (en) * 1995-09-29 1998-01-27 International Business Machines Corporation Information handling system including doze mode control
US5703790A (en) * 1996-02-27 1997-12-30 Hughes Electronics Series connection of multiple digital devices to a single power source
US5724611A (en) * 1996-04-25 1998-03-03 Vlsi Technology, Inc. Automatic cache controller system and method therefor
US5752265A (en) * 1996-06-13 1998-05-12 Compaq Computer Corporation Memory accessing in a multi-processor system using snooping
US5742781A (en) * 1996-08-09 1998-04-21 Hitachi America, Ltd. Decoded instruction buffer apparatus and method for reducing power consumption in a digital signal processor
US5801961A (en) * 1996-12-03 1998-09-01 Moore Epitaxial, Inc. Power management system for a semiconductor processing facility
US6014751A (en) * 1997-05-05 2000-01-11 Intel Corporation Method and apparatus for maintaining cache coherency in an integrated circuit operating in a low power state
US6085330A (en) * 1998-04-07 2000-07-04 Advanced Micro Devices, Inc. Control circuit for switching a processor between multiple low power states to allow cache snoops
US6105141A (en) * 1998-06-04 2000-08-15 Apple Computer, Inc. Method and apparatus for power management of an external cache of a computer system
US6347379B1 (en) * 1998-09-25 2002-02-12 Intel Corporation Reducing power consumption of an electronic device
US6438622B1 (en) 1998-11-17 2002-08-20 Intel Corporation Multiprocessor system including a docking system
JP3798563B2 (ja) 1999-01-06 2006-07-19 株式会社東芝 命令キャッシュメモリ
US7529799B2 (en) * 1999-11-08 2009-05-05 International Business Machines Corporation Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system
EP1157370B1 (en) * 1999-11-24 2014-09-03 DSP Group Switzerland AG Data processing unit with access to the memory of another data processing unit during standby
US6453373B1 (en) * 1999-12-30 2002-09-17 Intel Corporation Method and apparatus for differential strobing
US6766460B1 (en) * 2000-08-23 2004-07-20 Koninklijke Philips Electronics N.V. System and method for power management in a Java accelerator environment
US6845432B2 (en) * 2000-12-28 2005-01-18 Intel Corporation Low power cache architecture
US6925634B2 (en) * 2001-01-24 2005-08-02 Texas Instruments Incorporated Method for maintaining cache coherency in software in a shared memory system
US7424576B2 (en) * 2001-05-02 2008-09-09 Intel Corporation Parallel cachelets
US6976181B2 (en) * 2001-12-20 2005-12-13 Intel Corporation Method and apparatus for enabling a low power mode for a processor
US7165135B1 (en) * 2002-04-18 2007-01-16 Advanced Micro Devices, Inc. Method and apparatus for controlling interrupts in a secure execution mode-capable processor
US6843013B2 (en) * 2002-04-22 2005-01-18 Jorge Enrique Cutini Trigger safety lock for pistols and trigger assembly
US6691071B2 (en) * 2002-05-13 2004-02-10 Motorola, Inc. Synchronizing clock enablement in an electronic device
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US6922756B2 (en) * 2002-12-19 2005-07-26 Intel Corporation Forward state for use in cache coherency in a multiprocessor system
GB2403561A (en) * 2003-07-02 2005-01-05 Advanced Risc Mach Ltd Power control within a coherent multi-processor system
US7155623B2 (en) * 2003-12-03 2006-12-26 International Business Machines Corporation Method and system for power management including local bounding of device group power consumption
EP1779219B1 (en) * 2004-06-21 2008-04-30 Koninklijke Philips Electronics N.V. Power management
US7685365B2 (en) * 2004-09-30 2010-03-23 Intel Corporation Transactional memory execution utilizing virtual memory
JP2006113767A (ja) * 2004-10-14 2006-04-27 Sony Corp 情報処理システム、および、情報処理方法、並びに、プログラム
WO2006041218A2 (en) * 2004-10-15 2006-04-20 Sony Computer Entertainment Inc. Methods and apparatus for supporting multiple configurations in a multi-processor system
KR20070062568A (ko) * 2004-10-25 2007-06-15 로베르트 보쉬 게엠베하 적어도 2개의 처리 유닛들을 갖는 컴퓨터 시스템에서 모드전환 및 신호 비교를 위한 방법 및 장치
JP4669007B2 (ja) * 2004-10-25 2011-04-13 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング 少なくとも２つの処理ユニットを有する計算機システムにおいて切替及びデータを比較する方法及び装置
US7502948B2 (en) * 2004-12-30 2009-03-10 Intel Corporation Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores
RU2290706C1 (ru) * 2005-05-14 2006-12-27 Научно-исследовательский институт системных исследований Российской Академии Наук Устройство чтения из кэш-памяти
DE102005037248A1 (de) * 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Steuerung eines Speicherzugriffs bei einem Rechnersystem mit wenigsterns zwei Ausführungseinheiten
DE102005037250A1 (de) * 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Steuerung eines Speicherzugriffs bei einem Rechnersystem mit wenigstens zwei Ausführungseinheiten
US7870337B2 (en) * 2007-11-28 2011-01-11 International Business Machines Corporation Power-aware line intervention for a multiprocessor snoop coherency protocol
US8266337B2 (en) * 2007-12-06 2012-09-11 International Business Machines Corporation Dynamic logical data channel assignment using channel bitmap
US8010822B2 (en) 2008-03-28 2011-08-30 Microsoft Corporation Power-aware thread scheduling and dynamic use of processors
US8725953B2 (en) * 2009-01-21 2014-05-13 Arm Limited Local cache power control within a multiprocessor system
US8566628B2 (en) * 2009-05-06 2013-10-22 Advanced Micro Devices, Inc. North-bridge to south-bridge protocol for placing processor in low power state
US20110112798A1 (en) * 2009-11-06 2011-05-12 Alexander Branover Controlling performance/power by frequency control of the responding node
US8533505B2 (en) * 2010-03-01 2013-09-10 Arm Limited Data processing apparatus and method for transferring workload between source and destination processing circuitry
CN101958834B (zh) * 2010-09-27 2012-09-05 清华大学 支持高速缓存一致的片上网络系统及数据请求方法
US8806232B2 (en) 2010-09-30 2014-08-12 Apple Inc. Systems and method for hardware dynamic cache power management via bridge and power manager
JP5699756B2 (ja) * 2011-03-31 2015-04-15 富士通株式会社 情報処理装置及び情報処理装置制御方法
US8934279B2 (en) * 2011-05-16 2015-01-13 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space
US8949514B2 (en) * 2011-05-16 2015-02-03 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for both code and data space
US9910823B2 (en) * 2011-05-16 2018-03-06 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetch
US9588881B2 (en) 2011-05-16 2017-03-07 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses
WO2011157136A2 (zh) * 2011-05-31 2011-12-22 华为技术有限公司 一种数据管理方法、装置及数据芯片
US20130117511A1 (en) * 2011-11-08 2013-05-09 Arm Limited Data processing apparatus and method
US9471492B2 (en) * 2013-05-31 2016-10-18 Intel Corporation Scatter/gather capable system coherent cache
CN104345861B (zh) * 2013-08-07 2017-05-24 联想(北京)有限公司 一种数据处理方法和装置及电子设备
CN104657286B (zh) * 2013-11-19 2019-05-10 中兴通讯股份有限公司 一种分级存储方法及装置
US10482016B2 (en) * 2017-08-23 2019-11-19 Qualcomm Incorporated Providing private cache allocation for power-collapsed processor cores in processor-based systems
US11182106B2 (en) * 2018-03-21 2021-11-23 Arm Limited Refresh circuit for use with integrated circuits
US11847006B2 (en) * 2020-01-02 2023-12-19 Texas Instruments Incorporated Integrated circuit with debugger and arbitration interface

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5119485A (en) * 1989-05-15 1992-06-02 Motorola, Inc. Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
US5167024A (en) * 1989-09-08 1992-11-24 Apple Computer, Inc. Power management for a laptop computer with slow and sleep modes
US5287525A (en) * 1989-11-29 1994-02-15 Linear Technology Corporation Software controlled power shutdown in an integrated circuit
JPH061463B2 (ja) * 1990-01-16 1994-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
US5303362A (en) * 1991-03-20 1994-04-12 Digital Equipment Corporation Coupled memory multiprocessor computer system including cache coherency management protocols
US5421027A (en) * 1991-08-12 1995-05-30 Motorola, Inc. Method and apparatus for generating a pin interrupt request in a digital data processor using a dual function data direction register
GB2260631B (en) * 1991-10-17 1995-06-28 Intel Corp Microprocessor 2X core design
US5359723A (en) * 1991-12-16 1994-10-25 Intel Corporation Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only
US5313591A (en) * 1992-06-25 1994-05-17 Hewlett-Packard Company Computer bus arbitration for N processors requiring only N unidirectional signal leads
EP0624844A2 (en) * 1993-05-11 1994-11-17 International Business Machines Corporation Fully integrated cache architecture

Also Published As

Publication number Publication date
AU4962196A (en) 1996-10-30
IL116353A (en) 1999-03-12
WO1996032671A1 (en) 1996-10-17
EP0799444B1 (en) 2003-12-03
HK1003667A1 (en) 1998-11-06
CN1171159A (zh) 1998-01-21
EP0799444A4 (en) 1998-03-25
TW293105B (enExample) 1996-12-11
IL116353A0 (en) 1996-03-31
US5530932A (en) 1996-06-25
KR987001105A (ko) 1998-04-30
CN1145869C (zh) 2004-04-14
EP0799444A1 (en) 1997-10-08
RU2171490C2 (ru) 2001-07-27

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Legal Events

Date Code Title Description
FB36 Technical and formal requirements: requirement - article 36 of industrial property law
FF Decision: intention to grant
HHFI Decision: rectification
FG9A Patent or certificate of addition granted
B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

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