AU4962196A - A cache coherent multiprocessing computer system with reduce d power operating features - Google Patents

A cache coherent multiprocessing computer system with reduce d power operating features

Info

Publication number
AU4962196A
AU4962196A AU49621/96A AU4962196A AU4962196A AU 4962196 A AU4962196 A AU 4962196A AU 49621/96 A AU49621/96 A AU 49621/96A AU 4962196 A AU4962196 A AU 4962196A AU 4962196 A AU4962196 A AU 4962196A
Authority
AU
Australia
Prior art keywords
reduce
computer system
power operating
operating features
cache coherent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU49621/96A
Other languages
English (en)
Inventor
Douglas M. Carmean
John Crawford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU4962196A publication Critical patent/AU4962196A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
  • Power Sources (AREA)
AU49621/96A 1994-12-23 1995-12-20 A cache coherent multiprocessing computer system with reduce d power operating features Abandoned AU4962196A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US363735 1994-12-23
US08/363,735 US5530932A (en) 1994-12-23 1994-12-23 Cache coherent multiprocessing computer system with reduced power operating features
PCT/US1995/016601 WO1996032671A1 (en) 1994-12-23 1995-12-20 A cache coherent multiprocessing computer system with reduced power operating features

Publications (1)

Publication Number Publication Date
AU4962196A true AU4962196A (en) 1996-10-30

Family

ID=23431494

Family Applications (1)

Application Number Title Priority Date Filing Date
AU49621/96A Abandoned AU4962196A (en) 1994-12-23 1995-12-20 A cache coherent multiprocessing computer system with reduce d power operating features

Country Status (10)

Country Link
US (1) US5530932A (enExample)
EP (1) EP0799444B1 (enExample)
KR (1) KR987001105A (enExample)
CN (1) CN1145869C (enExample)
AU (1) AU4962196A (enExample)
BR (1) BR9510532A (enExample)
IL (1) IL116353A (enExample)
RU (1) RU2171490C2 (enExample)
TW (1) TW293105B (enExample)
WO (1) WO1996032671A1 (enExample)

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US7424576B2 (en) * 2001-05-02 2008-09-09 Intel Corporation Parallel cachelets
US6976181B2 (en) * 2001-12-20 2005-12-13 Intel Corporation Method and apparatus for enabling a low power mode for a processor
US7165135B1 (en) * 2002-04-18 2007-01-16 Advanced Micro Devices, Inc. Method and apparatus for controlling interrupts in a secure execution mode-capable processor
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KR20070062568A (ko) * 2004-10-25 2007-06-15 로베르트 보쉬 게엠베하 적어도 2개의 처리 유닛들을 갖는 컴퓨터 시스템에서 모드전환 및 신호 비교를 위한 방법 및 장치
JP4669007B2 (ja) * 2004-10-25 2011-04-13 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング 少なくとも２つの処理ユニットを有する計算機システムにおいて切替及びデータを比較する方法及び装置
US7502948B2 (en) * 2004-12-30 2009-03-10 Intel Corporation Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores
RU2290706C1 (ru) * 2005-05-14 2006-12-27 Научно-исследовательский институт системных исследований Российской Академии Наук Устройство чтения из кэш-памяти
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US9910823B2 (en) * 2011-05-16 2018-03-06 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetch
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CN104657286B (zh) * 2013-11-19 2019-05-10 中兴通讯股份有限公司 一种分级存储方法及装置
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Also Published As

Publication number Publication date
IL116353A (en) 1999-03-12
WO1996032671A1 (en) 1996-10-17
EP0799444B1 (en) 2003-12-03
HK1003667A1 (en) 1998-11-06
CN1171159A (zh) 1998-01-21
BR9510532A (pt) 1998-07-14
EP0799444A4 (en) 1998-03-25
TW293105B (enExample) 1996-12-11
IL116353A0 (en) 1996-03-31
US5530932A (en) 1996-06-25
KR987001105A (ko) 1998-04-30
CN1145869C (zh) 2004-04-14
EP0799444A1 (en) 1997-10-08
RU2171490C2 (ru) 2001-07-27

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