TW285766B - - Google Patents
Info
- Publication number
- TW285766B TW285766B TW085100785A TW85100785A TW285766B TW 285766 B TW285766 B TW 285766B TW 085100785 A TW085100785 A TW 085100785A TW 85100785 A TW85100785 A TW 85100785A TW 285766 B TW285766 B TW 285766B
- Authority
- TW
- Taiwan
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
- H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP00150495A JP3234732B2 (ja) | 1995-01-09 | 1995-01-09 | レベル変換回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW285766B true TW285766B (zh) | 1996-09-11 |
Family
ID=11503312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085100785A TW285766B (zh) | 1995-01-09 | 1996-01-23 |
Country Status (7)
Country | Link |
---|---|
US (1) | US5614843A (zh) |
EP (1) | EP0721254B1 (zh) |
JP (1) | JP3234732B2 (zh) |
KR (1) | KR0182663B1 (zh) |
CN (1) | CN1215923A (zh) |
DE (1) | DE69624016T2 (zh) |
TW (1) | TW285766B (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5684429A (en) * | 1995-09-14 | 1997-11-04 | Ncr Corporation | CMOS gigabit serial link differential transmitter and receiver |
US5793225A (en) * | 1996-01-02 | 1998-08-11 | Pmc-Sierra, Inc. | CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments |
US5724361A (en) * | 1996-03-12 | 1998-03-03 | Lsi Logic Corporation | High performance n:1 multiplexer with overlap control of multi-phase clocks |
US5978379A (en) | 1997-01-23 | 1999-11-02 | Gadzoox Networks, Inc. | Fiber channel learning bridge, learning half bridge, and protocol |
US6084439A (en) * | 1997-07-02 | 2000-07-04 | Cypress Semiconductor Corp. | Peak detector circuit with extended input voltage range |
US6054874A (en) * | 1997-07-02 | 2000-04-25 | Cypress Semiconductor Corp. | Output driver circuit with switched current source |
US7430171B2 (en) | 1998-11-19 | 2008-09-30 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
JP3467441B2 (ja) | 1999-12-01 | 2003-11-17 | Necエレクトロニクス株式会社 | バッファ回路 |
US6353335B1 (en) * | 2000-02-09 | 2002-03-05 | Conexant Systems, Inc. | Negative feedback, self-biasing PECL receivers |
US6356114B1 (en) | 2001-01-16 | 2002-03-12 | International Business Machines Corporation | High speed receiver with integrated CMOS and PECL capability |
US7082178B2 (en) * | 2001-12-14 | 2006-07-25 | Seiko Epson Corporation | Lock detector circuit for dejitter phase lock loop (PLL) |
US7129750B2 (en) * | 2003-07-30 | 2006-10-31 | Stmicroelectronics Pvt. Ltd. | CMOS to PECL voltage level converter |
US7091754B2 (en) * | 2004-06-28 | 2006-08-15 | Exar Corporation | CMOS LvPECL driver with output level control |
JP6094747B2 (ja) | 2013-03-26 | 2017-03-15 | セイコーエプソン株式会社 | 出力回路、半導体集積回路、振動デバイス、電子機器、および移動体 |
US9379709B2 (en) | 2014-06-30 | 2016-06-28 | Finisar Corporation | Signal conversion |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4437171A (en) * | 1982-01-07 | 1984-03-13 | Intel Corporation | ECL Compatible CMOS memory |
US4999519A (en) * | 1987-12-04 | 1991-03-12 | Hitachi Vlsi Engineering Corporation | Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier |
US5264744A (en) * | 1989-11-21 | 1993-11-23 | Hitachi, Ltd. | Complementary signal transmission circuit with impedance matching circuitry |
JP2975122B2 (ja) * | 1990-12-26 | 1999-11-10 | 富士通株式会社 | レベル変換回路 |
US5149992A (en) * | 1991-04-30 | 1992-09-22 | The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University | MOS folded source-coupled logic |
US5132572A (en) * | 1991-08-12 | 1992-07-21 | Advanced Micro Devices, Inc. | High-speed CMOS-to-ECL translator circuit |
JP3079675B2 (ja) * | 1991-08-22 | 2000-08-21 | ソニー株式会社 | レベル変換回路 |
US5365127A (en) * | 1993-10-18 | 1994-11-15 | Hewlett-Packard Company | Circuit for conversion from CMOS voltage levels to shifted ECL voltage levels with process compensation |
-
1995
- 1995-01-09 JP JP00150495A patent/JP3234732B2/ja not_active Expired - Fee Related
-
1996
- 1996-01-05 DE DE69624016T patent/DE69624016T2/de not_active Expired - Fee Related
- 1996-01-05 US US08/583,510 patent/US5614843A/en not_active Expired - Fee Related
- 1996-01-05 EP EP96100117A patent/EP0721254B1/en not_active Expired - Lifetime
- 1996-01-08 KR KR1019960000190A patent/KR0182663B1/ko not_active IP Right Cessation
- 1996-01-09 CN CN96104094.7A patent/CN1215923A/zh active Pending
- 1996-01-23 TW TW085100785A patent/TW285766B/zh active
Also Published As
Publication number | Publication date |
---|---|
DE69624016T2 (de) | 2003-06-18 |
EP0721254A2 (en) | 1996-07-10 |
EP0721254B1 (en) | 2002-10-02 |
US5614843A (en) | 1997-03-25 |
JP3234732B2 (ja) | 2001-12-04 |
CN1215923A (zh) | 1999-05-05 |
KR0182663B1 (ko) | 1999-04-15 |
DE69624016D1 (de) | 2002-11-07 |
JPH08191243A (ja) | 1996-07-23 |
EP0721254A3 (en) | 1997-08-06 |