TW256013B - Installation board - Google Patents

Installation board

Info

Publication number
TW256013B
TW256013B TW083108917A TW83108917A TW256013B TW 256013 B TW256013 B TW 256013B TW 083108917 A TW083108917 A TW 083108917A TW 83108917 A TW83108917 A TW 83108917A TW 256013 B TW256013 B TW 256013B
Authority
TW
Taiwan
Prior art keywords
lsi
component
installation board
logic
memory component
Prior art date
Application number
TW083108917A
Other languages
English (en)
Inventor
Osamu Miura
Akio Takahashi
Takao Miwa
Masahiro Suzuki
Ryuji Watanabe
Original Assignee
Hitachi Seisakusyo Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Seisakusyo Kk filed Critical Hitachi Seisakusyo Kk
Application granted granted Critical
Publication of TW256013B publication Critical patent/TW256013B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
TW083108917A 1994-03-18 1994-09-26 Installation board TW256013B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104715921A (zh) * 2013-12-17 2015-06-17 三星电机株式会社 电容器内嵌基板及其制造方法

Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798286A (en) * 1995-09-22 1998-08-25 Tessera, Inc. Connecting multiple microelectronic elements with lead deformation
US6423571B2 (en) 1994-09-20 2002-07-23 Hitachi, Ltd. Method of making a semiconductor device having a stress relieving mechanism
US6028364A (en) * 1994-09-20 2000-02-22 Hitachi, Ltd. Semiconductor device having a stress relieving mechanism
JP2842378B2 (ja) * 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
JP3322575B2 (ja) * 1996-07-31 2002-09-09 太陽誘電株式会社 ハイブリッドモジュールとその製造方法
JP3695893B2 (ja) * 1996-12-03 2005-09-14 沖電気工業株式会社 半導体装置とその製造方法および実装方法
US6277728B1 (en) * 1997-06-13 2001-08-21 Micron Technology, Inc. Multilevel interconnect structure with low-k dielectric and method of fabricating the structure
US5869895A (en) * 1997-12-15 1999-02-09 Micron Technology, Inc. Embedded memory assembly
US6132852A (en) * 1998-03-13 2000-10-17 Hitachi, Ltd. Multilayer wiring substrate and method for production thereof
WO2000002247A1 (de) * 1998-07-06 2000-01-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren und vorrichtung zur herstellung eines verbundes zwischen einem trägerkörper und mindestens einer darin enthaltenen komponente
US6239980B1 (en) * 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6316278B1 (en) * 1999-03-16 2001-11-13 Alien Technology Corporation Methods for fabricating a multiple modular assembly
KR101084525B1 (ko) 1999-09-02 2011-11-18 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
KR100823767B1 (ko) * 1999-09-02 2008-04-21 이비덴 가부시키가이샤 프린트배선판 및 프린트배선판의 제조방법
JP3670917B2 (ja) * 1999-12-16 2005-07-13 新光電気工業株式会社 半導体装置及びその製造方法
JP3677429B2 (ja) * 2000-03-09 2005-08-03 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
US6775150B1 (en) * 2000-08-30 2004-08-10 Intel Corporation Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture
JP2002230065A (ja) * 2001-02-02 2002-08-16 Toshiba Corp システムｌｓｉ開発装置およびシステムｌｓｉ開発方法
US7498196B2 (en) 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
US20020175402A1 (en) * 2001-05-23 2002-11-28 Mccormack Mark Thomas Structure and method of embedding components in multi-layer substrates
FR2826780A1 (fr) * 2001-06-28 2003-01-03 St Microelectronics Sa Dispositif semi-conducteur a structure hyperfrequence
US7218527B1 (en) * 2001-08-17 2007-05-15 Alien Technology Corporation Apparatuses and methods for forming smart labels
US6528735B1 (en) 2001-09-07 2003-03-04 International Business Machines Corporation Substrate design of a chip using a generic substrate design
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US6673698B1 (en) * 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
JP4209130B2 (ja) * 2002-04-09 2009-01-14 株式会社ザナヴィ・インフォマティクス 多層モジュール基板
CN1659810B (zh) * 2002-04-29 2012-04-25 三星电子株式会社 直接连接信号传送系统
US7750446B2 (en) 2002-04-29 2010-07-06 Interconnect Portfolio Llc IC package structures having separate circuit interconnection structures and assemblies constructed thereof
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3625815B2 (ja) * 2002-11-12 2005-03-02 沖電気工業株式会社 半導体装置とその製造方法
JP4489411B2 (ja) * 2003-01-23 2010-06-23 新光電気工業株式会社 電子部品実装構造の製造方法
US7135780B2 (en) * 2003-02-12 2006-11-14 Micron Technology, Inc. Semiconductor substrate for build-up packages
DE10355925B4 (de) * 2003-11-29 2006-07-06 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul und Verfahren seiner Herstellung
US20060001145A1 (en) * 2004-07-03 2006-01-05 Aptos Corporation Wafer level mounting frame with passive components integration for ball grid array packaging
US20060278976A1 (en) * 2004-09-02 2006-12-14 Koninklijke Phillips Electronics N.C. Semiconductor device, method and manufacturing same, identification label and information carrier
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
US8335084B2 (en) * 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US7300824B2 (en) * 2005-08-18 2007-11-27 James Sheats Method of packaging and interconnection of integrated circuits
TWI308382B (en) * 2006-07-25 2009-04-01 Phoenix Prec Technology Corp Package structure having a chip embedded therein and method fabricating the same
TWI300978B (en) * 2006-08-07 2008-09-11 Phoenix Prec Technology Corp A plate having a chip embedded therein and the manufacturing method of the same
JP4862641B2 (ja) * 2006-12-06 2012-01-25 株式会社デンソー 多層基板及び多層基板の製造方法
US7759212B2 (en) * 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
TW200930173A (en) * 2007-12-31 2009-07-01 Phoenix Prec Technology Corp Package substrate having embedded semiconductor element and fabrication method thereof
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
JP2010080801A (ja) * 2008-09-29 2010-04-08 Hitachi Ltd 半導体装置
US20100133682A1 (en) * 2008-12-02 2010-06-03 Infineon Technologies Ag Semiconductor device
WO2010064467A1 (ja) * 2008-12-05 2010-06-10 イビデン株式会社 多層プリント配線板、及び、多層プリント配線板の製造方法
US8362368B2 (en) * 2009-04-27 2013-01-29 Ultrasource, Inc. Method and apparatus for an improved filled via
TW201041469A (en) * 2009-05-12 2010-11-16 Phoenix Prec Technology Corp Coreless packaging substrate, carrier thereof, and method for manufacturing the same
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8350381B2 (en) * 2010-04-01 2013-01-08 Infineon Technologies Ag Device and method for manufacturing a device
US8927339B2 (en) 2010-11-22 2015-01-06 Bridge Semiconductor Corporation Method of making thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US8343808B2 (en) 2010-11-22 2013-01-01 Bridge Semiconductor Corporation Method of making stackable semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US20120126399A1 (en) 2010-11-22 2012-05-24 Bridge Semiconductor Corporation Thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US8841171B2 (en) 2010-11-22 2014-09-23 Bridge Semiconductor Corporation Method of making stackable semiconductor assembly with bump/flange heat spreader and dual build-up circuitry
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US9439289B2 (en) * 2012-01-12 2016-09-06 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9799627B2 (en) * 2012-01-19 2017-10-24 Semiconductor Components Industries, Llc Semiconductor package structure and method
US8749075B2 (en) * 2012-09-04 2014-06-10 Infineon Technologies Ag Integrated circuits and a method for manufacturing an integrated circuit
US9704809B2 (en) * 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
JP2015095587A (ja) * 2013-11-13 2015-05-18 日本特殊陶業株式会社 多層配線基板
US9502270B2 (en) 2014-07-08 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US9431319B2 (en) * 2014-08-01 2016-08-30 Linear Technology Corporation Exposed, solderable heat spreader for integrated circuit packages
JP2016207940A (ja) * 2015-04-27 2016-12-08 イビデン株式会社 電子部品内蔵配線板及びその製造方法
US9543249B1 (en) * 2015-09-21 2017-01-10 Dyi-chung Hu Package substrate with lateral communication circuitry
US10586757B2 (en) 2016-05-27 2020-03-10 Linear Technology Corporation Exposed solderable heat spreader for flipchip packages
JP6625491B2 (ja) * 2016-06-29 2019-12-25 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法
KR101963292B1 (ko) 2017-10-31 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
TWI718011B (zh) * 2019-02-26 2021-02-01 日商長瀨產業股份有限公司 嵌入式半導體封裝及其方法
CN111063671B (zh) * 2019-12-05 2021-11-09 珠海格力电器股份有限公司 一种芯片
US11410934B2 (en) * 2020-04-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Substrate and semiconductor device package and method for manufacturing the same
TWI800104B (zh) * 2021-11-19 2023-04-21 欣興電子股份有限公司 晶片封裝結構及其製作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322778A (en) * 1980-01-25 1982-03-30 International Business Machines Corp. High performance semiconductor package assembly
US4672421A (en) * 1984-04-02 1987-06-09 Motorola, Inc. Semiconductor packaging and method
JPS63239898A (ja) * 1987-03-27 1988-10-05 株式会社日立製作所 多層配線基板の形成方法
JPH02246144A (ja) * 1989-03-20 1990-10-01 Fujitsu Ltd 電子部品パッケージ及びその電源接続修復方法
JPH03211757A (ja) * 1989-12-21 1991-09-17 General Electric Co <Ge> 気密封じの物体
DE4115043A1 (de) * 1991-05-08 1997-07-17 Gen Electric Dichtgepackte Verbindungsstruktur, die eine Kammer enthält
US5200810A (en) * 1990-04-05 1993-04-06 General Electric Company High density interconnect structure with top mounted components
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5049978A (en) * 1990-09-10 1991-09-17 General Electric Company Conductively enclosed hybrid integrated circuit assembly using a silicon substrate
JPH0582717A (ja) * 1991-09-24 1993-04-02 Toshiba Corp 半導体集積回路装置
DE4135654A1 (de) * 1991-10-29 2003-03-27 Lockheed Corp Dichtgepackte Verbindungsstruktur, die eine Abstandshalterstruktur und einen Zwischenraum enthält
EP0547807A3 (en) * 1991-12-16 1993-09-22 General Electric Company Packaged electronic system
US5391917A (en) * 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104715921A (zh) * 2013-12-17 2015-06-17 三星电机株式会社 电容器内嵌基板及其制造方法

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CN1045865C (zh) 1999-10-20
KR950035553A (ko) 1995-12-30
CN1193886A (zh) 1998-09-23
CN1102017C (zh) 2003-02-19
CN1115169A (zh) 1996-01-17

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