CN1102017C - 安装基板 - Google Patents

安装基板 Download PDF

Info

Publication number
CN1102017C
CN1102017C CN97125918A CN97125918A CN1102017C CN 1102017 C CN1102017 C CN 1102017C CN 97125918 A CN97125918 A CN 97125918A CN 97125918 A CN97125918 A CN 97125918A CN 1102017 C CN1102017 C CN 1102017C
Authority
CN
China
Prior art keywords
wiring
substrate
base plate
installation base
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN97125918A
Other languages
English (en)
Other versions
CN1193886A (zh
Inventor
三浦修
高桥昭雄
三轮崇夫
铃木正博
渡辺隆二
片桐纯一
大幸洋一
今井勉
赤星晴夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of CN1193886A publication Critical patent/CN1193886A/zh
Application granted granted Critical
Publication of CN1102017C publication Critical patent/CN1102017C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

提供了一种用于通用的大型计算机和高速信息处理机的薄型高密度安装基板。所述薄型安装基板在安装着仅形成有元件的存储器LSI和逻辑LSI的陶瓷基板上、设有进行两个LSI的信号传送的多层布线层。所述LSI内部没有多层布线层。

Description

安装基板
本发明涉及安装基板，具体地说，本发明涉及用于大规模集成电路的安装基板。
本发明具有使大型通用计算机、工作站、高速信息处理机等所用的大规模集成电路元件(LSI)的微型组件基板高密度化同时可廉价制造的优点。本发明作为向其它电子设备的应用有用于使局部区域网络(LAN)与个人计算机连接的LSI微型组件等等。例如，按照本发明，在个人计算机上作为能驱动LAN的微型组件基板(LAN卡)，可以装入个人计算机内。而且，随着个人计算机高功能化，必须有大容量的存储器卡。在这种场合，也可以利用本发明的安装基板的概念。
大型通用计算机、工作站、高速信息处理机用的LSI微型组件基板等安装基板，为使LSI之间的信号传输高速化越来越存在着要能将多个LSI高密度安装且在基板内的信号延迟要小等越来越重要的课题。但是，迄今还没有这样的技术既能满足基板的这些要求又使成本降低，又能制作出适应便携化的要求使尺寸减小的基板。
随着大型电子计算机的高速化，要求它所用的印刷电路板的高多层化、高密度化。作为用以达到高密度化的安装方式，有将LSI芯片直接搭载在多层印刷电路板上的方法(下面简称为裸片安装)。作为直接搭载LSI的基板，陶瓷系列基板材料已实用化(作为一实例有：″A New Set of Printed-Circuit Technogies for theIBM3081 processor Unit″IBM·J·RES·DEVELOP：Vol·26，No·1，Jan·1982)。但是，由于陶瓷系列材料自身的介电常数高、基板的成形温度高，需要使用比铜电阻高的钨、钼作为布线导体，所以有对电信号传播速度不利的缺点。作为新的安装方法，特别希望用能使用铜作为布线导体而且用介电常数低的有机高分子材料作为绝缘层的多层电路板。但在现有技术中，形成绝缘层以及使其平坦化，需要很长的工艺时间，且成品率难以提高。
特别是随着计算机高速化，信息处理机的工作频率将变为更高的频率。尤其是在有开放式总体结构的高速信息处理机中，其工作频率性变为从500MHZ到10GHZ的高频。与此相对应，要求使信号布线电路更短，使布线绝缘的绝缘膜材料有低的介电常数且为厚膜。最适合此特性要求的材料有聚酰亚胺。使用聚酰亚胺的安装基板、多层布线板等等在特开昭63-239898等中已经介绍过。然而，与上述高速信息处理机相应的LSI的安装基板，特别是担当LSI间传送的多层布线板的特性阻抗要求在50-250Ω的范围。为实现此要求，作为绝缘层，聚酰亚胺的厚度要求在10-50μm。为使阻抗匹配，绝缘层的膜厚不均匀性要小，各层的平坦性要好。在这种情况下，在LSI的多层布线的工艺中所见到的那种逐次多层化的方法中，要使聚酰亚胺绝缘膜的膜厚保持均一性是困难的。此外，即使在安装基板的制造技术中，在现有技术中要使安装基板高性能化也还存在着许多问题。例如，作为安装基板，现在薄膜、厚膜混合基板受到人们重视而正进行开发。这种薄膜、厚膜混合基板是在用厚膜工艺形成的厚膜上再用薄膜工艺形成多层薄膜。所谓厚膜是用厚膜工艺用W、Mo等形成布线层再叠层烧结的陶瓷基板。所谓薄膜，是用聚酰亚胺作为层间绝缘层、Cu、Al作为导电层，用薄膜工艺形成的。在此薄膜、厚膜混合基板中，薄膜布线部中的聚酰亚胺的介电常数比陶瓷小，由于能使用低阻的Cu、Al，而且使用半导体工艺，所以能使信号传输高速化和高密度化。但是，随着计算机的高性能化，每单位面积安装的门电路数增加，与此相应，薄膜布线层的叠层数也要增加。关于形成薄膜多层布线的技术，已有一些文献报导。在其基本工艺中应用了在陶瓷基板、硅基板上通过对光刻胶膜的曝光、显影形成过渡孔和聚酰亚胺层的图案的薄膜工艺。这种薄膜工艺适用于布线的微细化。但此工艺由于是一层一层地形成导体和过渡孔的所谓逐次叠层方式，故在形成叠层数多的薄膜布线时，有需要很长时间的缺点。而且，在此工艺中，由于在最后工艺阶段产生的次品使整个基板都成为次品，因而有成品率低，制造成本高这样的缺点。在薄膜布线中，为将布线电阻抑制到低水平，倘使布线宽度微细化，就要使布线厚度增加以确保所需要的截面积。绝缘层的厚度大体与布线膜厚度相等，从布线的特性阻抗(Zo)的匹配方面来看正是所要求的。而且有必要使多布线层的绝缘膜完全均匀平坦，多层的绝缘层厚度不均匀性抑制到5％以下。然而，用现有的方法，要使布线层的厚度与线宽度相同或在其以上，即使使用流动性的聚酰亚胺漆，也难以确保其平坦性。因此，在聚酰亚胺漆热硬化形成聚酰亚胺膜后，要用研磨、擦光或抛光等方法使聚酰亚膜平坦化，还要进行使下部导体布线露出等工艺。特别是在这一系列工艺中，工艺时间随着对最终布线层表面平坦性精度要求而增加，成品率难以提高，还存在当叠层数增加时使布线精度变差、断线，短路故障增多等问题。进而，由于有输入输出端子的陶瓷基板和下层的薄膜布线部要反复加热，浸渍到水、药品中，因而存在界面变坏，受到杂质、离子污染使可靠性降低等问题。
本发明的目的是克服现有技术的上述缺点，在大型通用计算机、工作站、高速信息处理机用的LSI的微型组件基板等安装基板中，提供一种能高密度地安装多个LSI、可使信号传输高速化、而且成本低，可按便携式的要求缩小尺寸的基板。还提供一种即使在多层数的薄膜布线层的基板中也能使成品率提高，而且能用短时间形成薄膜布线层的结构。
为了解决上述问题，本发明提供了一种安装基板，它具有至少一个存储器大规模集成电路元件、至少一个逻辑大规模集成电路元件、用于安装它们的基板，以及形成在上述基板上的多层布线电路层，其特征在于：上述存储器大规模集成电路元件和上述逻辑大规模集成电路元件的信号电路形成于上述基板上的多层布线电路层中，通过上述存储器大规模集成电路元件以及上述逻辑大规模集成电路元件的外部端子，与上述存储器大规模集成电路元件和上述逻辑大规模集成电路元件电连接。
下面说明能使成品率提高，而且能传送高速信号的低成本制造安装基板的方法。
在制造安装基板信号电路的多层布线层的工艺中，作为多层绝缘膜的制造方法，使用了予先烘聚酰亚胺，可保证膜厚均匀的绝缘膜片。为保持层内的平坦性，通过加热、加压，与有流动性和粘接性的绝缘膜片的组合形成二层片。设前者的聚酰亚胺片为(A)，后者的片为(B)，则片(A)的膜厚在加热、加压工艺中不变化。另一方面，假定将片(B)层内的布线膜的布线/布线间的空间完全充填后的膜厚并设定初期的膜厚。使这样得到的最终的片(B)的膜厚和片(A)的膜厚两者相加，即是多层的绝缘层的膜厚。通过用这样方法提供具有所要求的一定膜厚的绝缘层，特性阻抗就可以设定在50-250Ω范围内。由于与缩小尺寸相对应，为使信号布线电路的长度缩短，本发明还提供了使布线微细化的工艺。因此，本发明的制造上述多层布线基板的工艺的特征是包括如下步骤：
(1)通过加热、压涂，使导体布线部平坦化，形成具有上述导体布线厚度的规定倍数的绝缘层，
(2)用激光器或蚀刻法在上述(1)的绝缘层上开终止孔；
(3)在上述(2)的终止孔上用电镀或者蒸发、溅射、CVD等方法埋设上述多层布线基板层间连接用的布线，以获得与上述(1)的绝缘层组成的平坦化的布线层；
(4)用相减或加成法在上述(3)的布线层上形成一定厚度的导体布线后，重复上述(1)、(2)、(3)工序，使之多层化。
由此使得可以应用布线节距为1μm-50μm的布线规则。
对于MCM(多芯片组件)已提出了许多方法。这些方法按布线基板的种类、结构分类。由于硅技术的进步，芯片的工作速度迅速提高。然而因为安装在电路基板上，工作速度受限制，成为决定组件和电路基板系统速度的主要原因。为此，使在迄今为止的表面安装方式中，难以确保高速区域的传输特性。因此，为了尽可能地缩短在组件中发生的延迟时间，在一个组件中搭载尽可能多的裸片，作为缩短延迟时间的方法，有多芯片微型组件。作为其中的一个，特别是为发挥工作站这样的高速处理用的微处理机(MPU)的高速性能，已发表了使薄膜多层布线形成在Si on Si(硅上硅)结构的MCM和陶瓷基板上的MCM等。但在现有的方法中，Si基板的布线成品率与此MCM的产品成品率直接有关。因此，作为提高此MCM成品率的方法，在此硅基板的布线膜上通过将分体制作预先选出的好的多层布线膜层叠粘结，以确保MCM的成品率。
特别重要的是，为了在LSI高度集成化，及尺寸扩大情况下维持LSI的成品率，LSI内部的布线只限于P、N元件等的功能元件电路，而担当其余的LSI内部、LSI间的信号传送的电路另外布线，先单独制作，随后再粘结到硅、陶瓷等基板上，与LSI电连接。这种另外的布线由于是用电阻小的铜布线，能提供比LSI内部的布线电阻小的布线电阻。用这样一连串的制造方法，能提供一种安装基板，其特征是：在安装有至少一个存储器集成电路元件和至少一个逻辑集成电路元件的基板上形成的多层布线层中，上述多层布线层能和上述基板在上述集成电路元件间进行电连接，特性阻抗为50Ω-250Ω，其布线节距为1μm-50μm的布线规则，而且由于有比上述集成电路元件低的布线电阻，所以能在工作频率为500MHZ-10GHZ范围传输匹配信号。
本发明采用在半导体安装基板的绝缘膜上用高平坦性、耐热的粘接片的办法，能制作安装高速工作的LSI的布线基板。
作为构成LSI的基本要素，有晶体管、二极管等有源元件，电阻、电容等无源元件、使这些元件电绝缘的隔离层、使这些元件相连结的布线等。在这些构成要素中，由于技术的飞跃进步，在制作有源元件、无源元件、隔离层的过程中，其成品率和可靠性已大幅度地提高。另一方面，与这三者相比，布线形成技术提高的不够。特别是现在，LSI有高速大型化的倾向，决定这样的大型高集成芯片的产品成品率的大体上是布线形成中的多层化技术。这是因为绝缘层(SiO2)平坦化和布线精细加工的困难所致。现在一般是用铝布线。但这种布线随着高集成化要求布线精细化时，发生电子徙动频度增加了。进而在高速工作的LSI中，将产生因布线电阻造成的延迟问题。
在解决这些问题时，有这样的方法，即将布线部分引出到LSI外部，使用比铝电阻低的能形成厚膜的金或铜作为布线金属，在绝缘层上使用平坦性高的聚酰亚胺树脂，形成布线。这样一来，由于布线引到外部，与设在LSI内部的情况(～10Ω/cm)相比，布线电阻能大幅度降低(～0.5Ω/cm)。还因为使用金、铜，能防止电子徙动的发生。
在需要高速工作的LSI中，为减少层间电容量，绝缘层的厚度要厚些，在聚酰亚胺树脂的热硬化过程中，Si基板的挠曲度增大，产生了在安装芯片时不能确保平整度的问题。作为解决这些问题的手段，预先准备好已形成布线的片(布线部分是另外制作的)，将此片在低温下粘接到LSI上这样方法。应用这种方法，可使多层布线部的绝缘层厚度在10μm以上，假定在在微带传输线的情况，则可将布线阻抗设定为50-250Ω。
能使布线的特性阻抗匹配，其绝缘层使用片材的布线基板，有印刷电路基板。在前者中为维持尺寸的稳定性，由于将玻璃织品混入片材中，故通孔的微小化、布线的微细化都有一定的限度。
因缩小尺寸使工作站性能提高，特别是在使用RISC(ReducedInstruction Set Computer)系统的工作站中，VLSI芯片自身的性能直接代表系统的性能。为了获得芯片的这一性能，需要满足两点安装要求：
①减少从芯片到芯片的信号延迟。
②增大特性阻抗而且减小其变动。
特别是，在要求工作频率超过500MHZ的高速工作的区域，芯片/芯片间关键路径的长度将成为决定周期环时间的最重要因素。以往，解决这样问题的手段有将多个芯片安装到叫做SOS(Silicon On Silicon)的大型硅片上的安装法。但用此方法，由于使用铝做布线，布线电阻在10Ω/cm以上，由于电阻大，所以在高频区域将产生噪音等问题。因此，要求有这样一种安装方法，即能用低电阻而且长度短的布线，要易于薄膜化，此外，从减小特性阻抗变化这一点上说，要求绝缘层厚且能保持厚度的均匀性。
高速计算机用的微处理机(MPU)以高时钟频率工作，在CUP和高速缓冲存储器间用高速总线连结。在现有的系统中，在印刷电路基板上使MPU和存储器连接，但用这种连接法有一定限度，对系统性能也产生一定的限制。为解决这些问题，将芯片以裸片状态装载在MUP与存储器之间，使芯片间的安装时所产生的延迟小，作为抑制组件寄生电感的方法有多芯片微型组件(MCM)。作为使这种方法更进一步高度化的方法，有将MPU和存储器的各部芯片内的布线向外部引出，而且用比铝电阻低的铜薄膜形成布线的方法。用此方法也能使芯片/芯片间的关键路径的长度缩短。特别是像已有技术那样，在芯片内形成布线的场合，芯片/芯片间的布线，由于只能利用芯片装载部(有源区)以外的部分，受到布图的限制。因此，芯片内只制作晶体管、二极等有源元件，电阻、电容等无源元件，以及使这些元件电绝缘的隔离层，在另外制作的布线部分，在后工序与芯片连接，则在芯片上也能形成布线，提高了电路布图的通用性。由于能解决制造工艺中难度最高的布线工艺，芯片的成品率大幅度提高，从而能提供价格低廉的LSI。
图1A-图1D示出了本发明的高密度安装基板的制作方法。
图2E-图2H示出了本发明的高密度安装基板的制作方法。
图3示出了本发明的高密度安装基板。
图4是将本发明的高密度安装基板的布线部标准化成微带线路的图。
图5示出了布线的特性阻抗和布线层的厚度t与绝缘层的厚度h之比t/h的关系图。
图6示出了本发明的高密度安装基板的一个例子。
图7示出了本发明的高密度安装基板的制作方法。
图8是本发明的高密度安装基板的剖面图。
图9是本发明的用于LAN的LSI模块基板的模式图。
图10示出了应用本发明的安装基板的存储器卡的一个例子。
图11示出了现有的用逐次薄膜形成法制作安装基板的方法。
实施例
参照图1和图2说明本发明的薄型高密度安装基板及其制造方法。本发明的薄型高密度安装基板31如图2H所示，由基板3、埋入设于基板3上的锪孔部(spot facing portion)2中的逻辑LSI4和存储器LSI5、6，以及设置在它们上面的多层布线电路层23构成。在图1和图2所示的实例中，多层布线电路层23由下部布线部23a和上部布线部23b构成。关于它们的详细结构，与制造方法一起说明。
如图1所示，制备一厚0.8mm大小为5cm×5cm的陶瓷制的基板3。在此基板3上，内层电路1设置在其内部，而且设置有埋置LSI用的锪孔部2。装载其上的LSI有逻辑LSI4和存储器LSI5、6。这些LSI4，5，6的内部结构未画出，但任何一个都有有源元件、无源元件和隔离层。但是，在LSI4，5，6上未设置用以使内部元件间连接的布线。代替它的是，如图1B所示，设置在LSI外部用以连接各元件的外部输出端子8，使作为外部输出端28的一部分的接触部分露在外部。LSI4，5，6分别埋置在相应的锪孔部2中，而且用金膏7固定在基板3上。有源元件有晶体管、二极管等。无源元件有电阻、电容等。隔离层是用以使元件间电隔离的绝缘层。
接着如图1C所示，制备用以形成逻辑LSI4如存储器LSI5，6的信号电路的布线片9。布线片9有绝缘层9C和设置在其上下的铜布线9a、9b。此布线片9放置在基板3上，其间夹有耐热粘接片10。在此状态下加热到250℃用压力粘接到基板3上。耐热粘接片10可以用日立化成工业株式会社生产的N-4。这样一来如图1D所示，耐热粘接片10变成耐热粘接层11，填充在布线片9和基板3之间。这时，耐热粘接层11也充填在外部输出端子8之间和铜布线9a之间的空间。
下面参照图2对以下工序进行说明。
如图2E所示，在外部输出端子8的正上方和基板表面的表面电路15的正上方分别设置用以形成连接导体的开口12、13。这些开口12、13例如是用受激准分子激光器在绝缘层9C和耐热粘接层11上设置通孔形成的。随后在设置有开口12、13的，外部输出端子8的正上方和基板表面的表面电路15的正上方，通过无电极化学镀铜，使铜生长。由此，如图2F所示，将铜填充到开口12、13而形成连接导体16、17。在布线片9上预先设置备用电路18和备用焊盘19时，在此工序同样通过无电极化学镀铜，形成连接导体20，进行必要的连接。由此形成下部布线部23a。
接着，为形成上部布线部23b，如图2G所示，将布线片21放置在下部布线部23a上，其间夹有耐热性片24，与下部布线部23a同样，加热到250℃，热压粘接。在此，布线片21是将传输信号用的铜布线21a、21b设置在绝缘层21c两面形成的。这些铜布线21a、21b分别以布线宽度/间隙为20/20μm，厚度20μm构成。耐热片24使用与图1C中所用的耐热片10相同的材料。加热后成为耐热粘接层22。
然后，像上述那样用受激准分子激光器在绝缘层21C和耐热粘接层22上设置开口，通过无电极化学镀铜形成连接导体27。这时，设置在下部布线部23a上面的铜布线的一部分起着连接焊盘25的功能。因而，通过连接导体27使铜布线21b和连接焊盘25电连接。
最后，在基板3的背面，用焊锡30将连接电源用的输出脚29连接在作为内层电路的端部的露出的外部输出端子28上。
通过上述一系列工序能获得高速信息处理机用的厚度1mm以下的薄型高密度安装基板31。
对像上述这样制得的安装基板31进行LSI驱动试验的结果表明能在500MHZ-1GHZ的工作频率驱动。由于应用本发明，可认为即使用工作频率10GHZ的LSI也能驱动。
图3示出了本发明的薄型高密度安装基板32的不同的制造方法。作为将逻辑LSI33和存储器LSI34、35粘接到陶瓷基板36的锪孔部37上的方法，除了用上述金膏焊锡等金属粘料粘接固定的方法外，还可用耐热硅橡胶、合成橡胶等非金属粘接方法。图3示出了使用作为应力缓冲剂的耐热硅橡胶38将LSI33、34、35固定在陶瓷基板36锪孔部37上的安装基板。
在本发明的薄型安装基板中，由于绝缘层使用一定厚度的耐热粘接片，通常可将绝缘层的厚度设定为一定的值，并可将特性阻抗(Zo)抑制在设计值的5％以内。这样一来，对反射损失小，工作频率在500MHZ以上的电路也容易做到，能高速进行信号传输。
图4是表示将本发明的安装基板的多层布线电路标准化成微带电路的图。如果布线形状为长宽比是1的矩形(图中t＝w)则布线的特性阻抗(Zo)可用布线层39的厚度t与绝缘层40的厚度h之比t/h的函数表示。
图5示出了t/h与Zo的关系。t/h＝0.01即布线层厚度为1，绝缘层厚度为100时，Zo约250Ω；t/h＝0.1即布线层厚度为1绝缘层厚度为10时，Zo约150Ω；t/h＝1即布线层与绝缘层厚度相同时，Zo约60Ω。
图6表示用耐热粘接片44将布线层41、厚度t为20μm绝缘层42、厚度h为40μm的布线片43热压粘接到陶瓷基板45上而得到的本发明的安装基板46。
本基板的特性阻抗(Zo)如由图5求出，则在t/h＝0.5时Zo约100Ω。在本基板中可任意改变耐热粘接片和绝缘层片的厚度。按照现在的片材规格，可以得到h＝10μm-200μm布线层，如用薄膜光刻技术，选择电镀技术，剥离等干法工艺，能形成t＝1μm-50μm。根据这些数值，t/h＝0.005-5是本基板设计的允许范围。在这种情况下，本基板的特性阻抗(Zo)为250Ω-50Ω。而且在本基板中，假定使布线层厚度为20μm，片厚例如为40μm，多层布线的层数为4层，则在多层布线部的厚度为180μm，陶瓷基板的厚度为0.8mm时，安装基板整体的厚度为0.98mm，从而能提供1mm以下的基板。
下面用图7说明具有使用本发明的耐热粘接片叠层而成的多层布线的安装基板的制造方法。在有内层布线47的陶瓷板48上用溅射法形成二层膜49(Cr/Cu：0.2μm/5μm)。再设置抗蚀胶50，并借助腐蚀得到布线图形51后，再通过将低热膨胀性的聚酰亚胺膜和有粘接性的粘接膜这两层膜热压粘接，使粘接膜填充到布线图形中，同时使之平坦化，得到绝缘层52。随后，用准分子激光器(KrF：248nm)，用掩模投影法形成25μm的终止孔53，再用化学镀铜法，将导体布线54形成在开口部。通过重复以上工序，在图8所示的陶瓷基板55上得到共6层的多层布线56。
最后，如图8所示，用焊锡59，使存储器大规模集成电路(以下称为存储器LSI)和逻辑大规模集成电路(以下称为逻辑LSI)电连接，外部连接端子60设置在陶瓷基板上，得到与大型通用计算机和高速信息处理机相适应的安装基板61。
图9是将本发明的安装基板的概念应用于在个人计算机中能使用的LAN用的LSI组件基板(LAN插板)上的一个例子。
存储器LSI的组件71和逻辑LSI组件72用连接用外部端子73，通过片上的多层信号布线电路74、基板75，借助外部接线端子76连接到个人计算机上。
图10是将本发明的安装基板的概念应用到个人计算机用的存储器卡上的实例。存储器LSI77与片上多层信号布线电路78电连接，通过基板79，借助外部连接端子80连接到个人计算机上。为了保护将镀膜81镀覆在LSI上。
下面作为比较例用图11说明用现有的逐次薄膜形成法制成的安装基板的制作实例。
首先，用溅射法将铜布线用的基底薄膜(铬/铜/铬三层，厚0.5μm)62形成在硅基板63上。随后形成光刻胶图形62，通过电镀铜形成信号电路66和层间连接用的连接导体柱64。接着，在除去光刻胶后，用剥蚀除去基底薄膜，再进行图形分离，就得到第一层布线67。其后在涂敷绝缘膜用聚酰亚胺的漆胶后，通过硬化，得到聚酰亚胺膜(厚20μm)。再通过研磨使聚酰亚胺膜平坦化，使连接导体部64的铜布线露出头，这就可露出连接部69。重复上述一系列工序得到了安装基板70。在此工艺中由于硅基片的挠曲超过200μm，不能与供电用的基板连接。

Claims (6)

1.一种安装基板，它有至少一个存储器大规模集成电路元件、至少一个逻辑大规模集成电路元件、用以安装上述元件的基板，以及形成在上述基板上的多层布线电路层，其特征在于：上述存储器大规模集成电路元件和上述逻辑大规模集成电路元件的信号电路形成在上述基板上的多层布电路层中，通过上述存储器大规模集成电路元件和上述逻辑大规模集成电路元件的外部端子，与上述存储器大规模集成电路元件和上述逻辑大规模集成电路电连接。
2.如权利要求1所述的安装基板，其特征在于：所述多层布线电路层上配备有上述存储器大规模集成电路元件和上述逻辑大规模集成电路元件的备用电路。
3.如权利要求1所述的安装基板，其特征在于：所述多层布线电路层的所述信号布线的电阻比上述存储器大规模集成电路元件和所述逻辑大规模集成电路元件的布线电阻小。
4.如权利要求1所述的安装基板，其特征在于：所述多层布线电路层的特性阻抗为50Ω～250Ω，布线节距为1μm～5μm。
5.如权利要求1所述的安装基板，其特征在于：所述多层布线电路层能进行工作频率在500MHz～10GHz范围的匹配信号传输。
6.如权利要求1所述的安装基板，其特征在于：所述基板的厚度在1mm以下。
CN97125918A 1994-03-18 1997-12-22 安装基板 Expired - Fee Related CN1102017C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP4823594 1994-03-18
JP48235/1994 1994-03-18
JP48235/94 1994-03-18

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN95104091A Division CN1045865C (zh) 1994-03-18 1995-03-17 安装基板

Publications (2)

Publication Number Publication Date
CN1193886A CN1193886A (zh) 1998-09-23
CN1102017C true CN1102017C (zh) 2003-02-19

Family

ID=12797789

Family Applications (2)

Application Number Title Priority Date Filing Date
CN95104091A Expired - Fee Related CN1045865C (zh) 1994-03-18 1995-03-17 安装基板
CN97125918A Expired - Fee Related CN1102017C (zh) 1994-03-18 1997-12-22 安装基板

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN95104091A Expired - Fee Related CN1045865C (zh) 1994-03-18 1995-03-17 安装基板

Country Status (4)

Country Link
US (1) US5565706A (zh)
KR (1) KR950035553A (zh)
CN (2) CN1045865C (zh)
TW (1) TW256013B (zh)

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798286A (en) * 1995-09-22 1998-08-25 Tessera, Inc. Connecting multiple microelectronic elements with lead deformation
US6423571B2 (en) 1994-09-20 2002-07-23 Hitachi, Ltd. Method of making a semiconductor device having a stress relieving mechanism
KR100398714B1 (ko) * 1994-09-20 2003-11-14 가부시끼가이샤 히다치 세이사꾸쇼 반도체장치및그의실장구조체
JP2842378B2 (ja) * 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
JP3322575B2 (ja) * 1996-07-31 2002-09-09 太陽誘電株式会社 ハイブリッドモジュールとその製造方法
JP3695893B2 (ja) * 1996-12-03 2005-09-14 沖電気工業株式会社 半導体装置とその製造方法および実装方法
US6277728B1 (en) 1997-06-13 2001-08-21 Micron Technology, Inc. Multilevel interconnect structure with low-k dielectric and method of fabricating the structure
US5869895A (en) 1997-12-15 1999-02-09 Micron Technology, Inc. Embedded memory assembly
US6132852A (en) * 1998-03-13 2000-10-17 Hitachi, Ltd. Multilayer wiring substrate and method for production thereof
WO2000002247A1 (de) * 1998-07-06 2000-01-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren und vorrichtung zur herstellung eines verbundes zwischen einem trägerkörper und mindestens einer darin enthaltenen komponente
US6239980B1 (en) * 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6316278B1 (en) 1999-03-16 2001-11-13 Alien Technology Corporation Methods for fabricating a multiple modular assembly
EP2081419B1 (en) * 1999-09-02 2013-08-07 Ibiden Co., Ltd. Printed circuit board and method of manufacturing printed circuit board
CN101232776B (zh) 1999-09-02 2011-04-20 揖斐电株式会社 印刷布线板
JP3670917B2 (ja) * 1999-12-16 2005-07-13 新光電気工業株式会社 半導体装置及びその製造方法
JP3677429B2 (ja) * 2000-03-09 2005-08-03 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
US6775150B1 (en) * 2000-08-30 2004-08-10 Intel Corporation Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture
JP2002230065A (ja) * 2001-02-02 2002-08-16 Toshiba Corp システムｌｓｉ開発装置およびシステムｌｓｉ開発方法
US7498196B2 (en) 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
US20020175402A1 (en) * 2001-05-23 2002-11-28 Mccormack Mark Thomas Structure and method of embedding components in multi-layer substrates
FR2826780A1 (fr) * 2001-06-28 2003-01-03 St Microelectronics Sa Dispositif semi-conducteur a structure hyperfrequence
US7218527B1 (en) * 2001-08-17 2007-05-15 Alien Technology Corporation Apparatuses and methods for forming smart labels
US6528735B1 (en) 2001-09-07 2003-03-04 International Business Machines Corporation Substrate design of a chip using a generic substrate design
US6673698B1 (en) * 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
JP4209130B2 (ja) * 2002-04-09 2009-01-14 株式会社ザナヴィ・インフォマティクス 多層モジュール基板
US7750446B2 (en) 2002-04-29 2010-07-06 Interconnect Portfolio Llc IC package structures having separate circuit interconnection structures and assemblies constructed thereof
CN1659810B (zh) * 2002-04-29 2012-04-25 三星电子株式会社 直接连接信号传送系统
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3625815B2 (ja) * 2002-11-12 2005-03-02 沖電気工業株式会社 半導体装置とその製造方法
JP4489411B2 (ja) * 2003-01-23 2010-06-23 新光電気工業株式会社 電子部品実装構造の製造方法
US7135780B2 (en) * 2003-02-12 2006-11-14 Micron Technology, Inc. Semiconductor substrate for build-up packages
DE10355925B4 (de) * 2003-11-29 2006-07-06 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul und Verfahren seiner Herstellung
US20060001145A1 (en) * 2004-07-03 2006-01-05 Aptos Corporation Wafer level mounting frame with passive components integration for ball grid array packaging
US20060278976A1 (en) * 2004-09-02 2006-12-14 Koninklijke Phillips Electronics N.C. Semiconductor device, method and manufacturing same, identification label and information carrier
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
US8335084B2 (en) * 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US7300824B2 (en) * 2005-08-18 2007-11-27 James Sheats Method of packaging and interconnection of integrated circuits
TWI308382B (en) * 2006-07-25 2009-04-01 Phoenix Prec Technology Corp Package structure having a chip embedded therein and method fabricating the same
TWI300978B (en) * 2006-08-07 2008-09-11 Phoenix Prec Technology Corp A plate having a chip embedded therein and the manufacturing method of the same
JP4862641B2 (ja) * 2006-12-06 2012-01-25 株式会社デンソー 多層基板及び多層基板の製造方法
US7759212B2 (en) * 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
TW200930173A (en) * 2007-12-31 2009-07-01 Phoenix Prec Technology Corp Package substrate having embedded semiconductor element and fabrication method thereof
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
JP2010080801A (ja) * 2008-09-29 2010-04-08 Hitachi Ltd 半導体装置
US20100133682A1 (en) * 2008-12-02 2010-06-03 Infineon Technologies Ag Semiconductor device
WO2010064467A1 (ja) * 2008-12-05 2010-06-10 イビデン株式会社 多層プリント配線板、及び、多層プリント配線板の製造方法
US8362368B2 (en) * 2009-04-27 2013-01-29 Ultrasource, Inc. Method and apparatus for an improved filled via
TW201041469A (en) * 2009-05-12 2010-11-16 Phoenix Prec Technology Corp Coreless packaging substrate, carrier thereof, and method for manufacturing the same
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8350381B2 (en) * 2010-04-01 2013-01-08 Infineon Technologies Ag Device and method for manufacturing a device
US8343808B2 (en) 2010-11-22 2013-01-01 Bridge Semiconductor Corporation Method of making stackable semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US20120126399A1 (en) 2010-11-22 2012-05-24 Bridge Semiconductor Corporation Thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US8927339B2 (en) 2010-11-22 2015-01-06 Bridge Semiconductor Corporation Method of making thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US8841171B2 (en) 2010-11-22 2014-09-23 Bridge Semiconductor Corporation Method of making stackable semiconductor assembly with bump/flange heat spreader and dual build-up circuitry
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US9439289B2 (en) * 2012-01-12 2016-09-06 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9799627B2 (en) * 2012-01-19 2017-10-24 Semiconductor Components Industries, Llc Semiconductor package structure and method
US8749075B2 (en) * 2012-09-04 2014-06-10 Infineon Technologies Ag Integrated circuits and a method for manufacturing an integrated circuit
US9704809B2 (en) * 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
JP2015095587A (ja) * 2013-11-13 2015-05-18 日本特殊陶業株式会社 多層配線基板
KR20150070810A (ko) * 2013-12-17 2015-06-25 삼성전기주식회사 캐패시터 내장 기판 및 그 제조 방법
US9502270B2 (en) * 2014-07-08 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US9431319B2 (en) * 2014-08-01 2016-08-30 Linear Technology Corporation Exposed, solderable heat spreader for integrated circuit packages
JP2016207940A (ja) * 2015-04-27 2016-12-08 イビデン株式会社 電子部品内蔵配線板及びその製造方法
US9543249B1 (en) * 2015-09-21 2017-01-10 Dyi-chung Hu Package substrate with lateral communication circuitry
US10586757B2 (en) 2016-05-27 2020-03-10 Linear Technology Corporation Exposed solderable heat spreader for flipchip packages
JP6625491B2 (ja) * 2016-06-29 2019-12-25 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法
KR101963292B1 (ko) 2017-10-31 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
TWI718011B (zh) * 2019-02-26 2021-02-01 日商長瀨產業股份有限公司 嵌入式半導體封裝及其方法
CN111063671B (zh) * 2019-12-05 2021-11-09 珠海格力电器股份有限公司 一种芯片
US11410934B2 (en) * 2020-04-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Substrate and semiconductor device package and method for manufacturing the same
TWI800104B (zh) * 2021-11-19 2023-04-21 欣興電子股份有限公司 晶片封裝結構及其製作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322778A (en) * 1980-01-25 1982-03-30 International Business Machines Corp. High performance semiconductor package assembly
US4672421A (en) * 1984-04-02 1987-06-09 Motorola, Inc. Semiconductor packaging and method
JPS63239898A (ja) * 1987-03-27 1988-10-05 株式会社日立製作所 多層配線基板の形成方法
JPH02246144A (ja) * 1989-03-20 1990-10-01 Fujitsu Ltd 電子部品パッケージ及びその電源接続修復方法
JPH03211757A (ja) * 1989-12-21 1991-09-17 General Electric Co <Ge> 気密封じの物体
DE4115043A1 (de) * 1991-05-08 1997-07-17 Gen Electric Dichtgepackte Verbindungsstruktur, die eine Kammer enthält
US5200810A (en) * 1990-04-05 1993-04-06 General Electric Company High density interconnect structure with top mounted components
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5049978A (en) * 1990-09-10 1991-09-17 General Electric Company Conductively enclosed hybrid integrated circuit assembly using a silicon substrate
JPH0582717A (ja) * 1991-09-24 1993-04-02 Toshiba Corp 半導体集積回路装置
DE4135654A1 (de) * 1991-10-29 2003-03-27 Lockheed Corp Dichtgepackte Verbindungsstruktur, die eine Abstandshalterstruktur und einen Zwischenraum enthält
EP0547807A3 (en) * 1991-12-16 1993-09-22 General Electric Company Packaged electronic system
US5391917A (en) * 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging

Also Published As

Publication number Publication date
US5565706A (en) 1996-10-15
KR950035553A (ko) 1995-12-30
CN1115169A (zh) 1996-01-17
CN1193886A (zh) 1998-09-23
CN1045865C (zh) 1999-10-20
TW256013B (en) 1995-09-01

Similar Documents

Publication Publication Date Title
CN1102017C (zh) 安装基板
KR970005707B1 (ko) 다층 배선 기판, 이 기판을 이용한 반도체 장치 및 다층 배선 기판의 제조방법
US7161810B2 (en) Stacked chip electronic package having laminate carrier and method of making same
US6992896B2 (en) Stacked chip electronic package having laminate carrier and method of making same
US5488542A (en) MCM manufactured by using thin film multilevel interconnection technique
JPH0220848Y2 (zh)
KR100188620B1 (ko) 전자적 패키지
US7532453B2 (en) Built-in capacitor type wiring board and method for manufacturing the same
US5768108A (en) Multi-layer wiring structure
US6967398B2 (en) Module power distribution network
EP1358675A2 (en) Electronic assembly comprising substrate with embedded capacitors and methods of manufacture
CN1484840A (zh) 多层阵列电容及其制作方法
CN1662122A (zh) 具有散热性能的多层电路板及其制作方法
US5350886A (en) Mounting substrate
CN1279157A (zh) 多层基板
US6888218B2 (en) Embedded capacitor multi-chip modules
US7023707B2 (en) Information handling system
GB2189084A (en) Integrated circuit packaging
JPH07307434A (ja) 実装基板
Balde Multichip packaging and the need for new materials
JPH03215995A (ja) 多層配線モジュール
EP0735806A1 (en) Package board
JPH10135637A (ja) セラミック多層配線基板
JP3272831B2 (ja) 多層配線基板、及びこれを用いた半導体装置
EP1577945A2 (en) Module power distribution network

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee