TW253946B - Data processor with branch prediction and method of operation - Google Patents

Data processor with branch prediction and method of operation

Info

Publication number
TW253946B
TW253946B TW083102651A TW83102651A TW253946B TW 253946 B TW253946 B TW 253946B TW 083102651 A TW083102651 A TW 083102651A TW 83102651 A TW83102651 A TW 83102651A TW 253946 B TW253946 B TW 253946B
Authority
TW
Taiwan
Prior art keywords
branch
data processor
target address
address cache
branch target
Prior art date
Application number
TW083102651A
Other languages
English (en)
Inventor
P Black Bryan
Denman Marvin
A Kearney Mark
Peter Song Seungyoon
Original Assignee
Ibm
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Motorola Inc filed Critical Ibm
Application granted granted Critical
Publication of TW253946B publication Critical patent/TW253946B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
TW083102651A 1994-02-04 1994-03-25 Data processor with branch prediction and method of operation TW253946B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US19229294A 1994-02-04 1994-02-04

Publications (1)

Publication Number Publication Date
TW253946B true TW253946B (en) 1995-08-11

Family

ID=22709074

Family Applications (1)

Application Number Title Priority Date Filing Date
TW083102651A TW253946B (en) 1994-02-04 1994-03-25 Data processor with branch prediction and method of operation

Country Status (3)

Country Link
US (1) US5761723A (zh)
JP (1) JP2744890B2 (zh)
TW (1) TW253946B (zh)

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US5812838A (en) * 1997-03-13 1998-09-22 International Business Machines Corporation Branch history table
US6834338B1 (en) * 2000-02-18 2004-12-21 Texas Instruments Incorporated Microprocessor with branch-decrement instruction that provides a target and conditionally modifies a test register if the register meets a condition
US7134005B2 (en) * 2001-05-04 2006-11-07 Ip-First, Llc Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
US6886093B2 (en) * 2001-05-04 2005-04-26 Ip-First, Llc Speculative hybrid branch direction predictor
US20020194462A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
US20020194461A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Speculative branch target address cache
US7165169B2 (en) * 2001-05-04 2007-01-16 Ip-First, Llc Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
US6895498B2 (en) * 2001-05-04 2005-05-17 Ip-First, Llc Apparatus and method for target address replacement in speculative branch target address cache
US7707397B2 (en) * 2001-05-04 2010-04-27 Via Technologies, Inc. Variable group associativity branch target address cache delivering multiple target addresses per cache line
US7165168B2 (en) * 2003-01-14 2007-01-16 Ip-First, Llc Microprocessor with branch target address cache update queue
US7200740B2 (en) * 2001-05-04 2007-04-03 Ip-First, Llc Apparatus and method for speculatively performing a return instruction in a microprocessor
JP4027620B2 (ja) * 2001-06-20 2007-12-26 富士通株式会社 分岐予測装置、プロセッサ、及び分岐予測方法
US7234045B2 (en) * 2001-07-03 2007-06-19 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US6823444B1 (en) * 2001-07-03 2004-11-23 Ip-First, Llc Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap
US7162619B2 (en) * 2001-07-03 2007-01-09 Ip-First, Llc Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
US7203824B2 (en) * 2001-07-03 2007-04-10 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US7159097B2 (en) * 2002-04-26 2007-01-02 Ip-First, Llc Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts
JP3843048B2 (ja) * 2002-06-28 2006-11-08 富士通株式会社 分岐予測機構を有する情報処理装置
US7185186B2 (en) * 2003-01-14 2007-02-27 Ip-First, Llc Apparatus and method for resolving deadlock fetch conditions involving branch target address cache
US7143269B2 (en) * 2003-01-14 2006-11-28 Ip-First, Llc Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor
TWI249131B (en) * 2003-01-14 2006-02-11 Ip First Llc Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor
US7152154B2 (en) * 2003-01-16 2006-12-19 Ip-First, Llc. Apparatus and method for invalidation of redundant branch target address cache entries
US7178010B2 (en) * 2003-01-16 2007-02-13 Ip-First, Llc Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
US7237098B2 (en) * 2003-09-08 2007-06-26 Ip-First, Llc Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US7360023B2 (en) * 2003-09-30 2008-04-15 Starcore, Llc Method and system for reducing power consumption in a cache memory
US20050278505A1 (en) * 2004-05-19 2005-12-15 Lim Seow C Microprocessor architecture including zero impact predictive data pre-fetch mechanism for pipeline data memory
US7890735B2 (en) * 2004-08-30 2011-02-15 Texas Instruments Incorporated Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
US7752426B2 (en) * 2004-08-30 2010-07-06 Texas Instruments Incorporated Processes, circuits, devices, and systems for branch prediction and other processor improvements
US7673122B1 (en) 2005-09-29 2010-03-02 Sun Microsystems, Inc. Software hint to specify the preferred branch prediction to use for a branch instruction

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DE3382152D1 (de) * 1982-12-09 1991-03-07 Sequoia Systems Inc Sicherstellungsspeichersystem.
JPH0695306B2 (ja) * 1986-01-07 1994-11-24 日本電気株式会社 命令先取り装置
JPS62159233A (ja) * 1986-01-07 1987-07-15 Nec Corp 命令先取り装置
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5093778A (en) * 1990-02-26 1992-03-03 Nexgen Microsystems Integrated single structure branch prediction cache
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache
JP2560889B2 (ja) * 1990-05-22 1996-12-04 日本電気株式会社 マイクロプロセッサ
EP0463965B1 (en) * 1990-06-29 1998-09-09 Digital Equipment Corporation Branch prediction unit for high-performance processor
JPH0820950B2 (ja) * 1990-10-09 1996-03-04 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチ予測型分岐予測機構
US5265213A (en) * 1990-12-10 1993-11-23 Intel Corporation Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction
US5414822A (en) * 1991-04-05 1995-05-09 Kabushiki Kaisha Toshiba Method and apparatus for branch prediction using branch prediction table with improved branch prediction effectiveness
US5319760A (en) * 1991-06-28 1994-06-07 Digital Equipment Corporation Translation buffer for virtual machines with address space match
EP0628184B1 (en) * 1992-02-27 1998-10-28 Samsung Electronics Co., Ltd. Cpu having pipelined instruction unit and effective address calculation unit with retained virtual address capability
US5423011A (en) * 1992-06-11 1995-06-06 International Business Machines Corporation Apparatus for initializing branch prediction information
US5423048A (en) * 1992-08-27 1995-06-06 Northern Telecom Limited Branch target tagging

Also Published As

Publication number Publication date
US5761723A (en) 1998-06-02
JP2744890B2 (ja) 1998-04-28
JPH08249181A (ja) 1996-09-27

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