TWI249131B - Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor - Google Patents

Abstract

An apparatus for killing an instruction after it has already been loaded into an instruction queue of a microprocessor is disclosed. The apparatus includes control logic that detects a condition in which the instruction must not be executed, such as a branch instruction misprediction; however, the control logic determines the condition too late to prevent the instruction from being loaded into the instruction queue. The control logic generates a kill signal indicating the instruction must not be executed. A kill queue receives the kill signal and stores its value. The kill queue maintains its entries in parallel with the instruction queue entries so that when the instruction queue subsequently outputs the instruction, the kill queue also outputs the value of the kill signal associated with the instruction. If the kill signal value output from the kill queue is true, then the microprocessor invalidates the instruction and does not execute it.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to an instruction buffer in a microprocessor, and more particularly to an instruction after an instruction is loaded into an instruction buffer. delete. The present invention is a related application, which claims priority to U.S. Patent Application Serial No. 60/440,063, filed on Jan. 14, 2003, which is incorporated herein by reference for APPARATUS AND METHOD FOR KILLING INSTRUCTIONS DETERMINED INVALID AFTER INSTRUCTION FORMATTING IN A MICROPROCESSOR EMPLOYING A BRANCH TARGET ADDRESS CACHE IN AN EARLY PIPELINE STAGE 〇 〇 快 快 快 微处理器 微处理器 APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP APP Prior Art Modern microprocessors are pipeline microprocessors. They can operate multiple instructions simultaneously in different modules or pipeline stages of the microprocessor. H e η nessy and Patterson define pipeline technology as "implementation technique for overlapping execution of multiple instructions in their co-authors 1f --<<computer structure: quantification method", second edition, John L. Hennessy, David A. Patterson, Morgan Kaufmann, San Francisco, CA, 1 99 6. They also provide an excellent visual explanation of the pipeline technology as follows: A pipeline is like a pipeline. There are many pipelines in the production of automobiles. In the phase, each stage is equipped with a component for the car. Each phase operates in parallel with the other phases, but each assembles a different car. In a computer pipeline, each step completes part of the instruction. Like a pipeline,

12829twf1.ptc Page 9 1249131 Case No. 93100761 曰 Amendment 5, Invention Description (2) Different steps and steps are called integral to form a phase synchronization microprocessor, the instruction is from a car line, the whole line In the cycle, a pipeline completes the pipeline phase in a micro time, and finally the other end is input. (An operation _ a buffer space between the sections. Operation, when the buffer is on, means that the memory is connected to the address and The order is based on a general efficiency and a commonly used instruction can be used in it, for example, but the tube can be used to make the buffer order missing one can receive a target address. In order to avoid the buffer before and after the buffer, the pipeline can cause the energy of the sub-address. In addition, there is a low cycle in the generator stage of the pulse cycle processor stage. The pipeline-free device, its pipeline line execution end is fast. This is the execution. The impact of the pipeline gas command is obtained, 'if it is different, or if it is commanded, the work will be done because of Bubbles are commonly used in the stage. Take note of the stage. Ο When the bubble is produced, let this point determine that the commanded line piece is flowing from one end. The general line stage is not lowered. There is a command phenomenon) Different. Entering the waterline, the car can also enter, that part. For each phase, the car passing through the pipeline can go in one clock to the next, such as the one. The operation is a slight result of a certain operation. The cycle in the steam, the clock idle mechanism phenomenon is in the different stages of the pipeline structure is a queue structure. When a command speed is different, a buffer (such as the low end) is required to execute the instruction. When there is no instruction in the memory, the instruction is in the memory and the instruction is provided in the memory, so the reason for reducing the cache is Branch instruction. When it must determine the target of the branch instruction instead of the next instruction from the branch instruction as a conditional branch instruction (such as whether to execute this branch instruction),

12829twfl.ptc Page 10 1249131 _ Case No. 93100761_年月日日 Fix _ V. Invention Description (3) In addition to determining the target address, the processor must also determine whether this branch instruction will be executed. Since the target address and/or the pipeline stage that determines whether to execute the branch instruction is after the pipeline phase of the fetch instruction, the pipeline bubble may be generated thereby. Instruction buffering does reduce the number of pipeline bubbles, but modern microprocessors typically use a branch prediction mechanism to predict in advance whether the target address and/or branch instructions will be executed to further reduce this problem. However, if the branch prediction is incorrect, the instruction fetched regardless of the prediction is the next sequential instruction or the target address instruction, and this instruction should not be executed, otherwise an error will be generated. Correcting an incorrect branch instruction prediction is an example of the need to delete an instruction that has been loaded into the microprocessor, that is, the error branch instruction should not be executed by the pipeline. However, the actual situation may be that the instruction has to be deleted after it has been written to the instruction buffer. Therefore, there is a need for a solution to implement the deletion of instructions written to the instruction memory. SUMMARY OF THE INVENTION The present invention provides an instruction deletion apparatus for deleting an instruction to load a microprocessor instruction queue in a first clock cycle and output from a bottom end of a queue in a next clock cycle. The method includes: a delete signal for transmitting a value generated in a third clock cycle after the first clock cycle; and a delete queue for use in combination with the delete signal for loading the third clock cycle The signal value is deleted and outputted at the next clock cycle; a validity signal generated during the second clock cycle is used in conjunction with the delete queue to indicate whether the instruction needs to be executed by the microprocessor. If deleted

12829twf1.ptc Page 11 1249131 _ Case No. 93100761_年月日日 Correction _ V. Invention Description (4) If the value of the delete signal outputted in the second clock cycle is true, the validity signal value is false. In another aspect, the invention provides a method of deleting instructions in a microprocessor. The method includes: loading an instruction into the first queue during the first clock cycle, generating a delete signal in the next clock cycle, and loading the value of the delete signal into another queue; in the third clock cycle Output this instruction from the bottom of the first queue and determine if the signal value in the second queue is true. If this value is true, execute this instruction. In another aspect, the invention provides a microprocessor. The method includes: a first queue for receiving instructions for instruction buffering; and a logic for combining with the first array to find that the instruction is not executable by the microprocessor, the logic generating a signal indicating that the value is true In this case, the signal is generated after the instruction is received by the first queue; the second queue is used in conjunction with the logic to load the true value signal and output the signal simultaneously in the first array output command. The microprocessor responds to the true value signal and invalidates the corresponding instruction. In another aspect, the present invention provides a computer-usable transmission medium for storing a data signal, the data signal comprising a computer-readable code, the computer-readable code being read and executed by a computer to enable a device A delete operation of an instruction to load a microprocessor command queue in the first clock cycle and output from the bottom end of the queue in the next clock cycle can be implemented. The computer readable code includes: a first piece of code, which is used by a computer to read and execute a signal for deleting and transmitting a signal generated by a third clock cycle; the second code is read by a computer. When the data is fetched and executed, the delete column is used together with the delete signal, and the delete signal generated in the third clock cycle is loaded.

12829twf1.ptc Page 12 1249131 SS_Ml〇〇761 V. Invention description (5) --±_I-曰$ X__ Two clock cycle to read and execute this output to generate ^ value output, the third program Code, by Lei Yue "< use, this validity signal in the ~= validity signal, and delete queue = whether will be executed by the microprocessor clock cycle, and used to illustrate the deletion of the output of the finger I The signal is true, if the deletion is listed in the second clock cycle ^ An excellent & second of this invention, the validity signal value will be false. A requirement such as a predictive mechanism allows it to be executed correctly using a sequence of instructions and as a fraction. The process in the microprocessor pipeline of the other ~7 delete function can be generated later, and the advantage is that the present invention causes the letter buffer column to be deleted. The field requires additional pipeline stages to store instructions and other purposes, features, and advantages to better understand the embodiments, and in conjunction with the drawings, the details of the present invention are readily apparent. The details are as follows: Embodiment: A schematic diagram of the structure of a microprocessor 100 is shown. Microprocessor 100 is a pipeline processor with multiple pipeline stages. The schematic shows a partial phase 'including an instruction phase (I s s a g e ) 155, an extraction phase (F-stage) 153, a translation phase (X-stage) 155 and a temporary phase (R-stage) 157. I-stage 1 5 1 includes a stage for extracting instruction bytes from memory or cache memory. In one example, I-stage 1 51 includes multiple stages. F-stage 1 53 includes a stage for formatting an unformatted instruction byte. The X-stage 155 includes a stage for converting macro instructions into microinstructions. R-stage 157 includes a temporary load of operands from the scratchpad file.

12829twfl.ptc Page 13 1249131 Case No. 93100761 曰 Repair" V. Description of invention (6) Storage stage. The execution stages of the microprocessor 1 〇 等, such as address generation, data, execution, storage, and result write back, after other R - s t a g e 1 5 7 are not listed in Figure 1. The microprocessor 100 includes an instruction cache memory 1 0 4 in I - s t a g e 1 5 1 . The instruction cache memory 1 〇 4 buffers the instructions fetched from the § 己 体 与 与 微处理器 微处理器 微处理器 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The instruction cache memory 1 〇 4 receives a currently selected address 1 8 1 , and accordingly selects an instruction byte 167 having a capacity of a cache line and outputs it. In one example, the instruction cache memory 104 is a multi-stage cache memory, that is, the instruction cache memory 104 requires multiple clock cycles to correspondingly select the address and output a fast. Take the line. Microprocessor 100 also includes a multiplexer 1 7 8 within I-stage 151. The multiplexer 1 7 8 provides the currently selected address 1 8 1 . The multiplexer 1 7 8 receives the next target address 1 7 9, which is obtained by adding the current target address 1 8 1 to the size of the cache line output by the instruction cache memory 104 memory. The multiplexer 1 7 8 will also receive a corrected address 177. This address clearly indicates the address used by the branch prediction for the microprocessor 100 correction error. The multiplexer 1 7 8 also receives a predicted branch target address of 1 7 5 . The microprocessor 100 also includes a branch target address cache memory B T A C 1 0 6 in the I-stage 151, and the cache memory is coupled to the multiplexer 178. The BTAC 106 responds to the current target address 181 and generates a predicted branch target address 175. The BTAC 106 buffers the branch target address and branch instruction address of the executed branch instruction. In one example, B T A C 1 0 6 includes a 4-way combined cache memory and each of the selected combinations

12829twf1.ptc Page 14 1249131 Case No. 931007fi1 Revision 5. Invention Description (7) Contains multiple items for storing the target address and branch prediction information for the predicted branch instruction. In addition to the predicted branch target address 157, BTAC 1 0 6 also outputs branch prediction related information 1 94. In one example, the BTAC information 194 includes an offset bit indicating the first byte of the predicted branch instruction of the cache line currently selected for the address 1 8 i; a piece of information indicating the predicted branch instruction Whether to span half of the cache line; one valid bit for each item in the selected item; a piece of information indicating which of the selected combinations is the least recently used path; a piece of information indicating which of the selected paths is The least recently used item; and a prediction as to whether a branch instruction will be executed. The microprocessor 100 also includes control logic 1 〇 2. If the current target address 181 matches the valid cache address of an executed branch instruction in the BTAC 106 and BTAC 1 预测 6 predicts that the branch instruction will be executed, the control logic 102 controls the multiplexer 1 78 to select the BTAC target address 1 75. If the wrong branch prediction occurs, control logic 1 〇 2 controls the multiplexer 1 7 8 to select the corrected address 1 7 7 . Otherwise, control logic 1 〇 2 will control multiplexer 1 7 8 to select the next target address 179. Control logic 102 also accepts BTAC information. 194 ° Microprocessor 100 also includes predecode logic 1 0 in its I-stage 151, and predecessor logic 1 0 8 is used in conjunction with instruction cache 1 〇 4. The pre-decoding logic 1 0 8 receives the instruction cache 丨〇 4 provided by the instruction bit tuple 1 6 7 cache line and B T A C information 1 9 4, and generates pre-decode information 1 6 9 accordingly. In one example, the pre-decoded information 169 includes one bit associated with each instruction byte, which is used to predict whether the byte is

12829twfl.ptc Page 15 1249131 --- Case No. 93100761 __ Year Month 曰 Correction __ V. Invention Description (8) BTAC 1 〇6 operation code of the branch instruction predicted to be executed; predict the next according to the predicted instruction length A plurality of bits of an instruction length; a bit associated with each instruction bit group, the bit element is used to predict whether the byte is the prefix of the instruction; and the prediction of the output of the branch instruction. Microprocessor 100 also includes an instruction byte buffer 112 in its F-Stage 153, which is used in conjunction with pre-decoding logic 1 〇 8. The instruction byte buffer 1 1 2 receives the pre-decode information 1 6 9 ' from the pre-decode logic 1 〇 8 and receives the instruction byte 1 167 from the instruction cache 丨〇 4. The instruction byte buffer 1 1 2 provides pre-decode information to control logic 1 0 2 via signal 196. In one example, the instruction byte buffer 丨丨2 is capable of buffering the instruction byte of the four cache lines and associated pre-decode information. Microprocessor 100 also includes instruction byte buffer control logic 1 1 4 that is used in conjunction with instruction byte buffer 1 1 2 . The instruction byte buffer control logic 1 1 4 controls the flow of the instruction byte of the input and output instruction byte buffer 丨丨2 and the associated pre-decoded information material. The instruction byte buffer control logic 114 also receives the BTAC information 194. Microprocessor 100 also includes an instruction formatter 1 1 6 in its F-stage 153 for use with instruction byte buffer 丨丨2. The instruction formatter u 6 receives the instruction byte and the predecoded message 165 from the instruction byte buffer 1 1 2 and thereby generates a format instruction 丨97. That is, the instruction formatter u 6 refers to the string of an instruction byte from the instruction byte buffer 1 1 2, determines which bytes contain the next instruction and the instruction length, and formats the next instruction as Command 1 9 7 output. In the example shown in Figure 1, the instruction format 116 includes a combinational logic that consults the instruction byte

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Page 16 1249131 __ Case No. 93100761_ Year Month Day Correction _ V. Invention Description (9) The instruction byte 1 1 5 provided by the processor 1 1 2 outputs the formatted instruction 1 in the same clock cycle. 9 7. In one example, the formatted instruction provided by the formatted instruction 197 includes instructions that are sufficiently compliant with the X 8 6 structure instruction combination. In one example, the formatted instructions are also referred to as microinstructions that are converted by the macro instructions and that are executable by the microprocessor 1000 pipeline execution stage. The formatted instruction 197 is generated within the F-stage 153. Each time the instruction formatter 1 16 outputs a formatted instruction 197, the instruction formatter 116 generates a true F_new_instr 152 signal to indicate that the formatted instruction 197 contains a valid formatted instruction. In addition, the instruction formatter 116 outputs the relevant information of the formatted instruction 197 via a signal F_instr_info 198 and supplies this signal to the control logic 1 〇 2. In one example, the signal F - instr - inf ο 1 9 8 includes: a prediction information (if the instruction is a branch instruction), the prediction information indicating whether the branch instruction is executed; the prefix of an instruction; the address of the instruction Whether it is in the microprocessor branch address buffer memory; whether the instruction is a far direct branch instruction; whether the instruction is a far indirect branch instruction; whether this is The instruction is a call branch instruction; whether the instruction is a return branch instruction; whether the instruction is a far return branch instruction; whether the instruction is unconditional An unconditional branch instruction; and whether the instruction is a conditional branch

12829twf1.ptc Page 17 1249131 _ Case No. 93100761 _年月日日_修正 _ V. Invention description (10) instruction ). In addition, the instruction formatter 1 16 outputs the address of the formatted instruction via the current instruction index C I P signal 1 8 2 , which is equal to the address of the previous instruction plus the previous instruction length. The microprocessor 100 also includes a formatted command queue F I Q 1 8 7 in its X-stage 155. The formatted command queue 1 8 7 receives the formatted command 1 9 7 from the instruction formatter 1 1 6 . The formatted command queue 1 8 7 also passes an early signal (ear 1 y 0 ) 1 9 3 output strip formatted instruction. In addition, the formatted command queue 1 8 7 receives information relating to the formatted instruction obtained by the formatted command 197 from the control logic 1 〇 2 via a signal X_r e 1 - i n f ο 1 8 6 . X_rel_info 186 is generated within X-stage 155. The formatted command queue 187 also outputs its associated information of the formatted command output by the earl y signal 193 via the lateO signal 191. The formatted instructions 1 8 7 and X _ r e 1 _ i n f 〇 1 8 6 will be explained in detail below. Microprocessor 100 also includes control logic 1 1 8 of the formatted instruction queue F I Q . The FIQ control logic 1 1 8 receives the signal F_new_instr from the instruction formatter 1 16 152cFIQ control logic 118 generates a true value signal FIQ _ fu 1 1 1 9 9 and when the formatted command queue 1 8 7 is full, This signal is sent to the instruction formatter 1 16 . The F I Q control logic 1 1 8 also generates an e sh i f t signal 1 6 4 for controlling the rotation of the instructions in the formatted command queue 1 8 7 . The FIQ control logic 118 also generates a plurality of e load signals 1 62 for controlling the loading of instructions from the formatted instruction 197 to the empty formatted instruction queue 187. In one example, F I Q control logic 1 18 generates an e load signal 162 for each of the formatted instruction queues 187. in

12829twfl.ptc Page 18 1249131 __ Case No. 93100761___Year Month J_ίΐί:___ V. Invention Description (11) In one example, the formatted command queue 1 8 7 includes 12 items, each item is stored ^ ^ The formatted macro 4a order. However, in order to make the schematic clear and concise, the formatted command queues in Figures 1 to 3 show only three items; therefore, Figure 1 shows three e load signals 1 62, which can be labeled e 1 〇ad [ 2 : 0 ] 〇 FIQ Control Logic 11 8 also maintains a valid bit 1 3 4 for each formatted instruction queue 1 8 7 item. The example shown in Figure 1 contains three valid bits, denoted as FV2, FV1, and FVO qFVO 134, respectively, corresponding to the formatted instruction queue 1 87 lowest-end item; FV 1 1 34 and the formatted instruction The queue 1 8 7 corresponds to the intermediate item; and the FV 2 1 3 4 corresponds to the formatted command column 1 8 7 highest-end item. The F I Q control logic 1 1 8 also outputs a signal F _ v a 1 i d 1 8 8 , which in one example is F V 0 w 1 3 4 . The valid bit 1 3 4 indicates whether the formatted instruction queue 1 8 7 corresponds to whether the item contains a valid instruction. The F I Q control logic 1 1 8 also receives an XIQ-ful1 signal 1 95. Microprocessor 100 also includes an instruction translator 138 in its X-stage 155 for use with the formatted command queue 187. The instruction translator 1 3 8 receives a formatted instruction from the formatted instruction queue 187 via an early lyO signal 193 and translates the formatted macro instruction into one or more microinstructions 1 7 1. In one example, the microprocessor 1 includes a reduced instruction set computer (r I SC ) core for executing the original or ▼ simplified instruction set. In the example shown in FIG. 1, the instruction translator 138 includes Lu, combinatorial logic: to receive the formatted macro instruction 'by early〇 193' and output the translated micro-instruction in the same clock cycle丨7 1. which is,

12829twf1.ptc Page 19 1249131 — Case number 93100761 _^^_g_Correction _ V. Description of the invention (12) Regardless of whether the input of the t-translator 138 contains a valid macro instruction, it will be in every clock cycle. Translate the input information. The microprocessor 100 also includes a translated instruction X 1 Q 1 5 4 in its X-stage 155 for use with the instruction translator 138. X I Q 1 5 4 Buffer The microinstruction 171 〇xiq 154 received by the instruction translator 138 also buffers the relevant information received by the formatted instruction queue 1 8 7 through the 1 a t e 0 signal 1 9 1 . This information is related to the formatted macro instruction prior to the translation of the microinstruction 17 1 and is therefore also associated with the microinstruction 丨7 1 . This related information is used by the execution stage of microprocessor 10 to execute the associated microinstruction 丨7 1 . In one example, X I Q 1 5 4 includes 4 items, while in another example, X I q 1 5 4 includes 6 or 8 items, respectively. However, for the sake of brevity and clarity, X I Q 1 5 4 shown in Figure 1 contains only 3 items. Microprocessor 100 also includes XIQ control logic 156 for use with XIQ 154. The XIQ control logic 156 receives the F-valid signal 188 and generates an XIQ_full signal 195. The XIQ control logic 156 also generates an X-load signal 164 to control the translated microinstructions 171 and related information to be loaded into the X I Q 1 5 4 . The X I Q control logic 1 56 also generates an X_sh i f t signal 1 1 1 to control the downward transfer of the microinstruction within X I Q 1 54. The XIQ control logic 156 also maintains a valid bit 1 4 9 for each input of the XIQ 154. The example shown in Figure 1 includes 3 valid bits, labeled XV 2, XVI and XV0, respectively. XV0 149 corresponds to the valid bit of the low-end item of XIQ 1 54; XVI 149 corresponds to the effective bit of the middle item of XI Q 154; X V 2 1 4 9 corresponds to the effective bit of the high-end item of XI Q 1 5 4 . The X I Q control logic 1 5 6 also outputs an X _ v a 1 i d signal 1 4 8, which in one example is X V 0 1 4 9 . The valid bit 1 4 9 indicates an internal X I Q 1 5 4 corresponding

12829twf1.ptc Page 20 1249131 Case No. 93100761 _Ά 修正 Amendment 5. Does the project of the invention (13) contain a valid translated microinstruction. The microprocessor 100 also includes a 2-input multi-working 172' in its X-Stagel 55 that is attached to the XIQ 154. The multiplexer 172 operates as a bypass multiplexer that selectively bypasses the X I Q 1 5 4 . The multiplexer 丨 7 2 receives the output of the XIQ 154 at one input and the input signals of the XIq 154 at the other end, such as the microinstruction 171 and the later 191. The multiplexer 172 selects an input it accepts under the control of a control signal 丨6 1 input from the XIQ control logic 156 and outputs it to an execution stage register in the 3 tagel 57. 6. If the execution stage register 丨7 6 state is to receive an instruction 'and when the instruction translator 丨3 8 outputs the micro instruction 丨n 乂丨q 1 5 4 is empty, then the f i7 2 is in the x 1Q control logic 1 5 6 Control the bypass X 1 Q 1 5 4. The microprocessor 1A further includes a valid bit register RV 189, which receives the χ-vai id signal 148 from the XIQ control logic 156, and stores the instructions in the execution stage register 7 6 micro-instructions and related information is valid. The formatted command queue 1 87 includes an early queue 32 for storing the formatted macro instruction received by the modified command signal 丨97; a corresponding late queue 146, It is used to store related information received through the /, X_r el a: info signal 186. Figure i shows the early queue

1249131^号931007fi1 年月曰 Revision 5, invention description (14) _ — LE 0 ° LE 0 is the low-end item of the late stage 1 4 6; [e 1 is the mid-end item of the late stage 1 4; LE2 is The high-end project of the late stage 1 46. The content of le〇 is provided as an output signal 181^〇 191. The crying format/detailed command queue 1 8 7 also includes a scratchpad 1 8 5 . The temporary memory is 1 8 5 receives the 5 \ signal 164 from the F 1 Q control logic 1 1 8 at the end of the first clock cycle, and outputs the first clock cycle through a 1 shift signal 168 at the next clock cycle. The value of the received _^ signal 164. The command column 1 8 of the upper f also includes 3 registers 1 8 3 . The register 1 8 3 receives the el〇ad[2: 〇] 142 from the FIQ control logic 1 18 at the end of the pulse period to output the eload received by the 11〇ad[2:〇] signal pulse period. [2:0] The "2.01 Ren' Zf 185 and 183 of signal 162 respectively output the eshift signal 164 and eload delayed by one clock cycle in J. 庳微指人=ί,中,X一rel一inf0 186 includes: The length of the macro instruction used to translate into a pair; a set of this macro; this] Ϊ i, the description of the cache line; a storage location of this macro instruction; and in ϊΐ ϋ ϋ: Current position; the instruction of this macro instruction refers to the prediction that the branch prediction is 为7 is predicted as the branch instruction and the various phases are in two 彳κ, this information is the correction of the branch prediction. Information related to branch predictions and corrections includes: a branch branch history table information that predicts whether a branch is going to be executed; a portion; a linear instruction indicator that uses a branch instruction that is executed by ^ ί 以 to predict the separation Describing linear instruction indicators for mutual exclusion or logical calculus, and whether the instruction is A branch pattern is performed; in minutes

1249131 _ case number 93100761

V. Description of the invention (15) The second branch sample used for backtracking in the case of a prediction error >

The flag bit of the branch instruction feature, such as: this branch instruction: no, Zhu Ming = instruction, a call instruction, - return to the stack, two::: knife branch, an indirect branch, and the prediction of the branch instruction result is I The predictor does; the relevant BTAC 1 0 6 predictions of the various times ^ I 2 select the address 1 8 1 corresponds to a BTAC 1 0 6 internal address shell / this pair if the backup address is valid 'branch instruction is It is predicted that execution or non-execution, the execution of the most recently used project of the BTAC 106 combination selected by the bit target address 181 requires the BTAC 106 to be updated, and the "people-item", ie, BTAC 1 should be replaced. 〇6 output of the target address in the 'X-re 1—inf 〇 186 part of the peak of the previous clock on the 'the same time as the ee in this macro instruction is 由 丨 3 2 ΐϋΪίί1.93 provides information about the subsequent clock cycle. The microprocessor 100 also includes a delete queue, such as ^/, / in the X-Stagel 55, to the FIQ control logic 118. The delete queue H5 stores a delete signal 1 4 1 generated by = Helmet 1 〇 2. The control logic 1 0 2 generates a value delete signal 141 to indicate that the formatted command signal 丨97 received by the early queue 132 in the previous stage can be used by the microprocessor. 100 execution. Delete 伫5, '/ 3 items, which are marked as ΚΕ2, KE1, and ΚΕ〇, respectively, and correspond to the “List of 各 各 各 各 各 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨, κ Ε 1 is the middle item of the delete column, ΚΕ 2 is deleted \ 宁 spoon ==

1249131 _ Case No. 93100761 _ This Month 倐 ___ V. Invention Description (16) Top entry item. As shown in Figures 4, 5 and 6, the content of ΚΕ0 is provided by the output signal k i 1 1 0 1 4 3 . Delete queue 1 4 5 Receive 1 1 〇 a d [ 2 : 0 ] Signal 1 4 2, 1 s h i f t Signal 1 6 8 and e s h i f t Signal 1 6 4, used to control the loading and conversion of the delete column 1 4 5 . The deletion queue will be further explained in the following description of Figures 4, 5 and 6. Control logic 102 generates a true value signal based on the different conditions found from BTAC information 194, predecode Jnf0 196, F-instr_info 198, and current command indicator 182. One situation is to detect that the BTAC 1 06 mispredicts a branch instruction. In one example, BT AC 1 6 6 incorrectly predicts the length of the branch instruction, such as the predicted instruction length being different from the length confirmed by instruction formatter 1-6, resulting in erroneous prediction of the branch instruction. In one example, BTAC 106 causes a misprediction of a branch instruction by erroneously predicting that a normal instruction is a branch instruction. For example, BTAC 06 predicts an instruction as a branch instruction, and instruction formatter 161 confirms its non-branch instruction. In one example, BTAC 106 causes erroneous prediction of the branch instruction due to erroneous prediction of the address of the branch instruction, such as the instruction offset bit ^ predicted by BTA C 1 0 6 is used to do this by BTAC 1 0 6 The sum of the predicted selected address 1 8 1 is not equal to the instruction address 1 8 2 generated by the formatter 1 16 .一种 In one example, when BTAC 1 0 6 is predicted, the error pre-command and subsequent instructions must be deleted; therefore, control logic 1 0 2 generates a true deletion for each instruction that needs to be deleted. Signal 1 4 1. The control logic 1 0 2 generates a delete signal 丨 4 1 after a command is supplied to the instruction formatter n 6 . In addition, the control logic 丨〇 2 pass, = an invalid signal 1 47 to provide information to invalidate the β Τ α ^ which produces the erroneous prediction

1249131 _ extravagance 93100761 a _±——3-§ amendment _ five, invention description (17) 1 0 6 items. After the control logic 1 0 2 invalidates the BTAC 1 0 6 item for error prediction, the control logic 102 controls the multiplexer 1 78 to select the corrected address 1 77 to reacquire the incorrectly predicted instruction and its subsequent instructions. To correct the original error prediction. Because the error prediction item in BTAC 06 is invalid at this time, BTAC 1 0 6 will no longer predict that the last error-predicted instruction is the executed branch instruction; therefore, 'whether or not this instruction is a branch instruction, it will It is formatted by the instruction formatter 1 16 and interpreted by the instruction translator 1 3 8 and executed by the execution phase of the microprocessor pipeline 100. Another type of control logic 1 0 2 generates a true value delete signal 1 4 1 in that control logic 102 causes microprocessor 100 to employ a target generated by BTAC 106 in response to a prediction that one of its branch instructions will be executed. Address. In this case, any subsequent instructions fetched by the instruction cache 1 〇 4 and transferred to the instruction byte buffer 1 1 2 must be deleted; therefore 'control logic 1 0 2 for each The instruction to be deleted generates a true value delete signal 1 4 1 . Control logic 1 0 2 generates this delete signal 1 4 1 at a clock cycle after the instruction is supplied to instruction formatter 1 16 . In one example, the instruction formatter 116 is capable of formatting 2 macro instructions in one clock cycle. If b T A C 1 0 6 predicts that the _th of the two instructions is a branch instruction to be executed, the control logic 丨〇 2 deletes the second instruction. Figure 2 is a block diagram showing the structure of the early queue 1 1 2 of the formatted command block 187 shown in Figure 1 in accordance with the present invention. The early queue 1 3 2 includes a 3 ^ selection-scratchpad, and the three selections - the registers are sequentially connected to form a queue. The three options - the scratchpad include the items EE2, eei shown in Figure 1,

1249131

EEO 〇 Early selection of the top of the 132 column - the temporary machine 2 1 2 and a temporary storage 5 | 22 2, the output of the multiplexer 212 of the input of the 屮崭 匕 多 多 多 2 2 = = = : : : :f is written as (4), which is used to receive the formatted command shown in Figure 1 = 19, which is the input end of the input terminal = = = input terminal, used to receive the input of the register ER "22". If el〇ad[2] 162 is true 'multiplexer 212 will select the load i = , the formatted command signal 197 on the input; otherwise, the multiplexer Ί 琏 保持 保持 保持 保持The register ER2 2 ^ = 2 22 is on a clock cycle (clk) 2 0 2 on: m; the output of Z 1 2. The selection of the middle segment of the early queue 132 - the register includes a 3-input multiplexer 211 and a register 221, the register is labeled ER1, and is used for outputting of the workpiece 211. The multiplexer 211 includes a load data input terminal for receiving the formatted command signal 197. The multiplexer 2 The 丨丨 further includes a hold data input terminal for receiving the output of the register ER1 221. The device 211 further includes a conversion data input terminal for receiving the output of the register er2 2 2 2. The multiplexer 211 receives The doadu signal 162 shown in Fig. 1 is a control input. The multiplexer 211 also receives the eshift signal 164 shown in Fig. 1 as a control signal. If e 1 〇ad [ 1 ] 1 6 2 is true, the multiplexer 2 1 j U, The formatted command signal on the data input end of the bin is 1 9 7; if esh = t and 164 are true, the multiplexer 211 selects the output of the conversion data input = 2 2 2; otherwise, the multiplexer 2 1 2 is selected to keep the data rounded on

1249131 Amendment 曰 Case No. 93100761 V. Invention Description (19) 1 Output of ER1 221. The register ER1 221 loads the output of the multiplexer 211 at the rising edge of a clock cycle cIk 202. The selection of the bottom of the first stage 132 - the scratchpad includes a multi-type 210 of 210 and a register 22 0, the register is labeled 肫〇, which is used to receive the output of 210. The multiplexer 21A includes a load data input terminal, and a guaranteed command signal 197. The multiplexer 210 also includes a crying terminal for receiving the round-out of the register ER 〇 2 2 0. Multiplex 2^ 1 & includes the factory ^ change data input terminal, used to receive the register ER1 to suppress I input. The evening work device 210 receives the el〇ad[〇] signal 162 shown in FIG. 2 (4) Receive the eshi shown in Figure 1 "Signal 164, control j5 唬. If el〇ad[〇] 162 is true, then the formatted command on the input of the load data is 9 °. . . f cry ΕΙΠ Select the conversion data The output of the TOER1 221 is temporarily stored on the input terminal; otherwise, the output of the register ER0 2 2 0 on the multiplexer input end is pulsed. The rising edge of the 〇2 is loaded into the multi-working T 2 20 - The time of the secondary 2 20, the result as the early 〇 signal ^ 〇 = 〇. The register Figure 3 shows the structure of the late 仵 146 of the column 187 shown in Figure 1 according to the present invention ° j,; two temporary storage-multiplexer, the three temporary storage one multiplex; the column 146 includes three columns. The three temporary storage one multi-work test:: sequentially connected to form a 伫LE〇. For the inclusion of the items LE2, LE1, and the late stage of the late stage 1 4 6 of the temporary storage - 吝 抑 抑 312 312 and a temporary register 3 22, including two 2-input multi-sentences Only show that the tongue is LR2, used to pick up

1249131

Case No. 93100761 V. Invention Description (20) = Multiple Output: The multiplexer 312 includes - load data input to receive 1 "6; ^; 111 £ 186 as shown in Figure 1. The multiplexer 312 is also The lean input is used to receive the output of the register LR2 322. Xigong w 3 1 2 Receive 1 1 〇ad [ 2 ] "No. 1 4 2 as a control input. If l loaj[2] 142 is true, multiplexer 312 selects load data input i -1nf0186; otherwise, multi-guard 312 selects the output of register LR2 322 holding data entry 钿. The register LR2 3 2 2 loads the output value of the multiplexer 312 at the rising edge of the clock period clk 2 0 2 shown in FIG. The temporary storage-multiplexer in the middle of the late queue 146 includes a 3-input worker, 3H and a scratchpad 321, which is labeled lri for the output of 夕:, 311. The multiplexer 311 includes a load data input interface for receiving the X_ref_inf〇 186 shown in FIG. The multiplexer 311 also has a data input terminal for receiving the output of the register LR] 3 2 i. The multiplexer 3 1 1 also includes a conversion data input for receiving the output of the temporary ^2^32. The multiplexer 311 receives the U〇ad[1] signal 142 as a control input. The multiplexer 311 also receives the lshi ft signal 168 as a control input. If the value of 1 load[ 1 ] 142 is true, the multiplexer 31 i selects the output of the LR2 322 in the load 186; ^^lshift 1 6 δ/Λ Λ 益 311; otherwise the multiplexer 311 selects to keep The output of the register LR1 321 on the data input. The register LR1 3'21 loads the multiplexer 3n output value at the rising edge of the clock period clk 2 0 2 shown in FIG. The temporary storage-multiplexer at the bottom of the late array 146 includes a 3-input multiplexer 310 and a scratchpad 32〇, and the register is labeled 1^〇 for connection.

1249131 Case number 93100761

-a- ' \lij Receives the output of multiplexer 310. The multiplexer 310 includes a load data terminal for receiving the X-ref_info 186 shown in FIG. Multiplexer 310, $spoon A hold data input for receiving the register LR 〇 3 2 〇. The multiplexer 310 also includes a conversion data input for receiving the output of the crying LR1 321 . The multiplexer 310 receives the 11 〇ad[〇] signal 142 as a binary input. The multiplexer 310 also receives the lshi ft signal 168 as a control input. If lload[0] 142 is true, then multiplexer 31 selects X_ref_info 186 on the load side; if lshift 168 is true, then 'action 3 1 0 selects LR 1 The output of 3 2 1; otherwise the multiplexer 3 i selects the output of the register LR0 320 on the end of the feed input. The register LR1 32〇 loads the output value of the multiplexer 31〇 at the rising edge of the clock cycle cik 2 0 2 shown in FIG. Multiplex 3 1 0 will be the result in Figure j! a t e 〇 signal 丨 g J output. - Figure 4 shows a schematic view of the first example of the deletion queue 145 shown in Figure i in accordance with the present invention. The structure of the deleted array example in Fig. 4 is similar to the structure of the middle and late array 146. The delete queue includes three temporary storage-multiple-duplex, and the temporary storage-duplexer includes a 2-input multi-state 412 and a register 422, and the register is marked as KR2. Used to receive output. The multiplexer 412 includes a load data input and a delete signal 141. The multiplexer 412 also includes a hold-before input ' used to receive the output of the register KR2 422. The multiplexer |12, HoadM] signal 142 is used as the control signal. If the value of u〇ad[2] 142 is |, the multiplexer 412 selects the delete signal on the load data input, and 3% of the temporary storage-multiplexer are sequentially connected to form a queue. 3 temporary storage - multiplex ι includes the items KE2, KE1 * KE 所示 shown in Figure 1.

1249131 曰 Case No. 931007B1 V. Inventive Note (22) The second eve::4:2 selects the output of the register KR 2 4 2 2 on the input of the lean material. The register KR2 42 2 loads the output value of the multiplexer 412 at the rising edge of the clock cycle 202 shown in FIG. = In addition to the 歹 歹 ^ middle section of the temporary storage multi-guard includes a 3 input ^ 411 and a register 421, this register is the output of the multiplexer 4 。. The multiplexer 411 includes a load data for receiving the delete signal 141. The worker 411 further includes a second data input terminal for receiving the output of the register KR1 421. Multiplex ^^^^^: 4, the nine input end, used to receive the register KR2 422 output, ΐ 4 η ? receive 11 〇 a d [1] signal 14 2 as a control wheel. Multiplex; 4 2 Ϊ 6; ^ ^ ^ ^ ^ Π oad [ 1 ] 141 , · If 1 shift ° 168 value ^ is the delete signal output on the input of the medium straight load; otherwise multiplexed cry 41? ϊ ίί" The tool 411 selects the rising edge of the 421 ^ ^ Α ^ ^ ^ ^ ^ # ^KRl 2〇2 of the KR2 42 2; the workpiece 411: 2 out of the median, the clock cycle cik 2 4 to 2 temporary storage - multiplexed f including, input multi-receiver multiplexer "O's turn out 7 multiplex 2 for the terminal" used to receive the delete signal! 4 !. Multiple J 2 data input = human terminal, used to receive temporary storage = 〇 also includes individual. Multiplex H is connected to t", which is used to receive the register of the register Km 421... Also 2 = = ^ 唬 168 as the control input. If ll〇ad[0] 12829twfl.ptc Page 30 1249131

The ly value is true, and the multiplexer 410 selects the load data input; if the lshift 168 value is true, the multiplexer 41. KR1Jf21^ is selected; the tiger/multiple/+410 selects the output of the scratchpad kr〇 320 on the data input end. The register KR0 42 loads the output value of the multiplexer 41A at the rising edge of the clock period cik 02 shown in FIG. The multiplexer 41 outputs the result as k 1 1 1 0 signal 1 4 3 in Fig. 1. - Figure 5 shows a block diagram of a second example of the delete queue 丨45 shown in Figure 1 in accordance with the present invention. The delete queue 丨 4 5 includes three selections - the scratchpad and the fourth multiplexer are connected to each other to form a queue. These three choices—temporary 1^ include the items KE2, KE1, and ΚΕ0 in Figure 1. The selection of the top of the delete queue 145 - the scratchpad includes a 2-input multiplexer 5 12 and a register 5 22, the register being labeled KR2 for receiving the output of the multiplexer 5 1 2 . The multiplexer 5丨2 includes a load data input terminal, and receives the delete signal 丨4 i shown in FIG. The multiplexer 5丨2 also includes an output for holding the lean input terminal' for receiving the register KR2 5 2 2 . The multiplexer 5 1 2 receives the 1 1 0 a d [ 2 ] signal 丨 4 2 shown in Fig. 1 as a control signal. If lload [2] 142 is true, multiplexer 5 12 selects the delete signal 1 4 1 on the load data input; otherwise, the multiplexer 5丨2 selects the hold register KR2 52 2 on the data input. Output. The register KR2 5 2 2 loads the output value of the multiplexer 5丨2 at the rising edge of a clock cycle, at which time the pulse period is marked as cik. The selection of the middle segment of the column 145 is included. The register includes a 3-input The multiplexer 5j1 and a register 521, the register is labeled KR1, for receiving the output of the multiplexer 511. The multiplexer 511 includes a load data input terminal

Page 31 1249131 Case No. 5. Invention Description (24) Use ^ to receive the deletion #1 1 1 1. The multiplexer 5丨j also includes an output for holding data, and an output for receiving the register KR1 521. The multiplexer 511 also includes

Incoming: one, change data input, used to receive the output of the register KR2 5 2 2 = work fast 5 1 1 Receive the 丨丨〇ad [丨] signal 丨 4 2 shown in Figure 1 as the control letter ~. The multiplexer 51 1 also receives the 丨sh丨f t signal 丨6 8 shown in Fig. 1 as a control input. If lload[l] 142 is true, the multiplexer 511 selects the load data, the input delete signal 141; if the lshift signal 168 is true, the output of the KR2 522 is selected; otherwise, the multiplexer 511 selects the hold The output of the scratchpad KR1 521 on the input. The register KR1 521 loads the output value of the multiplexer 511 at the rising edge of the Clk period Clk 202. In addition to the selection of the bottom of the column 145 - the register includes a 2-input multi-function 5 10, a register 52 〇 labeled KR (), and a 2-input multiplexer 5 〇 9. The multiplexer 5 〇 9 pack: 5" 负载 load data input terminal for receiving the delete signal 141. The multiplexer 5〇9 includes: a hold data input terminal for receiving the register KR〇 52〇, and a 1 load(4) signal (4) shown in FIG. 1 as the control ==. If iload[0] 142 is true, multiplexer 5〇9 selects the load signal = delete signal 141 on the input; otherwise the multiplexer 5〇9 holds the output of register J = register KR 0 52 0 . The multiplexer 51 includes a = feed input for receiving the output of the multiplexer 5〇9, which outputs the output of the multiplexer 5Π. The multiplexer 510 receives the eshift ^ number 1 64 as a control input. If the es h丨f t signal 丨 6 4 is true, the device 5 1 0 selects the output of the multi-guard 5 i i on the conversion data input terminal ^ otherwise

1249131 ___ Case No. 931007 (Π_年月日日__ V. Invention Description (25) The tool 510 selects to keep the output of the multiplexer 509 on the data input. The register KR 0 5 2 0 is in the clock cycle. The rising edge of cik 20 2 loads the output value of multiplexer 510. Figure 6 shows a schematic diagram of a third example of the delete queue 1 4 5 shown in Figure 1 in accordance with the present invention. 5 is similar to the deletion of the column 1 4 5 in Fig. 5, and the corresponding elements are also marked with similar serial numbers. The deletion of the 4 series shown in Fig. 6 is different from the value shown in Fig. 5 in the following points. The input ΚΕ0 of the 1/4 column also includes four logic gates: one inverter 6 0 2, two 2 input gates and gates 6 〇 4 and 6 0 6 , and a 2 input gate or gate 6 0 8 . The device 6 0 2 receives the 1 1 〇ad [ 0 ] signal 1 4 2 and supplies its output to a AND gate 604. The gate 604 receives the output of the register KR0 520 and uses it as the second _ input. Gate 6 0 6 receives 1 1 〇ad [ 0 ] signal 1 4 2 as its input, and receives the delete signal 1 4 1 as its other input. The outputs of the two gates 6 〇 4 and 6 0 6 For the input of the OR gate 6 〇 8 or the result of the gate 6 0 8 is output as the ki 1 1 〇 signal 1 4 3 of the delete queue 1 4 5 shown in FIG. 1 instead of the delete queue 145 shown in FIG. Output of multiplexer 509. Figure 7 shows a schematic diagram of the logic for generating the F-va 1 id signal 188 shown in Figure 1 of the present invention in FIQ control logic 181. This logic includes an inverter 7 1 2 and a 2-input gate 7 1 4. The inverter 7 1 2 receives the ki 1 1 〇 signal 1 43 shown in Figure 1 and supplies its output to the gate 7 1 4 as its input. The other input of 1 4 is the valid bit FV0 134 of the formatted instruction queue 187 shown in Figure 1. Therefore, the valid bit FV0 134 is defined by the killO_ signal so that the XIQ control logic 丨5 6 can know The instruction provided to the instruction translator 丨38 by the ear iy 〇 signal 193 is an invalid instruction, such as: deleted.

12829twf1.ptc Page 33 1249131 修正 Amendment 931 931Q07B1 V. Inventions (26) Directive. The addition of w f 8 shows a flow chart of the operation principle of the garment arrangement according to the microprocessor 1 0 0 command shown in Fig. 1 of the present invention. The process starts with block 8 〇 2. The instruction formatter 116 shown in Figure 1 will group the instruction bits.

Control logic: ίΪί 2, the formatted instruction is marked by FIQ in Figure V: =, zone Ϊ 8; 24V "time Γ cycle occurs, delete nickname 14 shown in Figure 1;: not = 102 generates - a true value at the time of the early manned row 132 instruction must be continued === in the previous clock cycle block 8 04 is deleted under the clock cycle i - f is deleted. In one example, Clock 2. The flow advances to 8 妗 6 妗 cycles, which is marked in block 8 0 6 in Figure 8, and deletes the value of 伫 column 141. This value is deleted in the file 彳 '2 0 In the signal, the flow proceeds to the decision function area to select the low-end invalid item. In the decision function block 8 08, you enter the formatted command column 187, and the condition is to block the block 80 2 Whether the bit is in the formatted command, for example, the finger that needs to be deleted. This command is in the lowest end item S of the command ^^87 $ after formatting. The process proceeds to the lowest end item of the decision function block 8丨2; In the middle, the flow block 818. If not, the flow advances to the zone in the decision function block 8 1 2, and the fine I J break condition is the delete signal 141 value 12829twf1.ptc Page 34 1249131

Case No. 931007m V. Invention Description (27) Whether it is true. If true, the process proceeds to block 816. Block 814, otherwise, flow • In block 814, a k^110 signal 143, shown in Figure i, is generated, and a value of false is generated by defining the FIQ effective bit ^^ 134. The F_valid signal 188 is shown as 1 and is used to implement the deletion of the instruction. The flow ends at block 8 1 4 . In the block 816, a killO # 唬 143 shown in the figure 假 is generated, so if FV0 134 is true, it is also true. The flow ends at block 8 1 6 . In one example, a 804 to block 816 all occur in the second clock cycle after the JY 攸 &; Γ Γ Γ 8 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 删除 删除 删除. Flow proceeds to decision function block 82 2 . In the decision function block 8 2 2, the judgment condition is that the instruction of the formatted command queue 187 is loaded, and the input is η ^ , and the slave is from 1 " J ? 7 , for example, the need to be deleted. 々, 位 No bit is placed at the lowest end of the command queue 187 after formatting. If the flow is proceeding to the decision function block 824; otherwise, the flow returns to the block 8 1 8 〇, and the energy zone 4 824 is judged to be the lowest end item of the delete queue. If yes, the flow proceeds. Go to block 8 2 6 ; the flow proceeds to block 8 2 8. At block 8 2 6, a value of true is generated for the kiu〇 signal 143 ' shown in Figure J, by defining the FIQ effective bit FV0 134 To generate a false value of the F_valid signal 188 ' shown in Figure 1 and delete it. The flow ends at block 8 2 6 .

1249131 j more positive

Case No. 93100761, Invention Description (28) In block 8 2 8, a value of false k 丨丨 will be generated. If FVO 134 is true, then F_valid 188 諕; since block 828 ends. In one example, each slave block "8". The loop in the zone occurs in the next clock 1 block 828 dock 3 adjacent to clock 2, or another adjacent clock cycle, I want to, in order to transfer to the lowest order item of the instruction sequence 1 1 格式化 格式化 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除 删除5 clock cycles, := set the work ^ is represented by logic high level. Figure 9 shows the following | In Figure 9, 'formatter, 1 1 6 production $ - a new formatted giant When the green XIQ I54 status is dissatisfied, for example, XIQ I54 can be scribbled from the person; 138 receives the macro ♦; after formatting, the command 187 is empty. When the instruction translator 138 translates the σ 式 的 macro instruction and generates a new micro instruction 1 7 1 , the XIQ is empty. Thus, XIQ control logic 156 evaluates the value of L-valu signal 188 with x-vaHd signal 148 instead of storing F_va 1 88 as a valid bit 149 as shown in FIG. As shown in the figure, in the first clock cycle 1, the instruction formatter 丨i 6 generates a F-new-instr signal 152 as shown in FIG. 1 to illustrate the formatting in FIG. The command signal 197 contains a valid new formatted macro instruction. Since the command queue 丨8 7 is empty after formatting, the FIQ control logic 118 in Fig. 1 generates a value of the true e〇ad[〇] signal 162, which will format the post-instruction signal 丨9 7 effective new Formatted macro

12829twf1.ptc Page 36 1249131 _ Case No. 93100761_Year Month Day Chromium t_ V. Invention Description (29) After the instruction is loaded, the instruction will load the empty item e e 0 at the bottom of the sequence. As shown in the figure, in the same instance, the delete signal 1 4 1 , k i 1 1 〇 signal 143, F - valid 188, X_valid 148 and valid bit rv 189 are both false. In the second clock cycle 2, the valid bit FV0 134 of the item ΕΕ0 of the formatted instruction sequence 1-8 in Fig. 1 is set to indicate whether ΕΕ0 contains a valid instruction. At the rising edge of clock cycle 2, a register 183 in Figure 1 loads eload[0] 162 and outputs a value of ll〇ad[0] 142. As shown in the figure, since el〇ad[0] 162 is true, a new instruction is loaded into ER0 220 and output to the early〇 signal 193 in FIG. 1 as an input to the instruction translator 1 3 8 in FIG. The instruction translator 1 3 8 translates the new macro instruction and provides the resulting microinstruction 1 7 1 to X I Q 1 5 4 . Additionally, as shown, control logic 102 generates new information relating to new instructions on X_rei_inf0 186. Since lload[0] 142 is true, as shown in the figure, multiplexer 410 selects the load data input terminal, and outputs the related information contained in X_r el_inf 〇1 86 to lateO 191 as xiq 154 and as shown in FIG. Input to the 172. Further, because the instruction translator 138 has translated the new instruction in the second clock cycle, the FIQ control logic 1 1 8 produces a true value on the e sh ift signal 1 64 in FIG. 1 so that the instruction can be in the third The clock cycle shifts out the formatted command queue 1 8 7. Also during the second clock cycle 2, control logic 1 〇 2 finds that a new instruction generated during the first clock cycle must be deleted, and thus produces a true value for the second half of the second clock cycle. The delete signal 141 is shown in FIG. Because in the second half of clock 2, 11〇&(1[0] 142 and delete signals are both

12829twf1.ptc Page 37 1249131

Further, because of the truth, according to FIG. 4 to FIG. 6, the kiii〇 signal 143 is also true for the killO signal of 143 bits. According to FIG. 7, F~va, and ud 188 are not shown in the figure, because F-val id i 88 is false, and ^ is taken at the end of the second clock cycle when X val id 148 is false. ",, 2, after the inlfl period 3, because the new instruction: the transfer of the format edge 134 is false. The rise of the third clock cycle iV / i ten Q (four) control logic 156 will be translated after the micro-instruction 71 and the instruction related information device m provided by the lateO 191. In addition, the middle register 185 loads the eshift signal heart: a sub-true value of 13 匕 "168. Further, a false X - valid 148 at the end of the second clock cycle is loaded into RV 189 ' This signal is false during the third clock cycle. Therefore, the microinstruction 1 7 1 that is generated and loaded into the execution phase of the second phase clock cycle is flagged as invalid, and as expected, is executed by the execution phase of the microprocessor 1 0 0 pipeline. . ^ As can be seen from Figure 9, although the new macro instruction was generated during the first clock cycle and loaded into the formatted instruction, the command is saved 1 8 7 and deleted the dream 1 4 1 until the brother The pulse cycle is generated. The instruction delete device in Figure 1 conveniently sets the macro instruction to be deleted, for example, the flag is invalid, so the execution stage does not execute the instruction that has been deleted. Figure 10 is a timing diagram showing the operation of the instruction deleting apparatus shown in Figure 1 in accordance with the present invention. Figure 1 is similar to Figure 9 except when the instruction formatter 1 16 generates a new formatted macro instruction when X I Q 1 5 4 is full. Because the XIQ 1 5 4 in the example of Figure 10 is the valid bit X ν 2 1 4 9 of the full XIQ 1 5 4 is displayed, and the values of RV 1 8 9 and X — va 1 id 1 4 8 are not displayed. .

1249131 __ Case No. 93100761_Yearly 曰 Chromium if.__ V. Description of invention (31) In clock cycle 1, XIQ__full 195 is true. As shown in Figure 9, instruction formatter 116 generates a new instruction on formatted an instr 197, F_new_i ns tr 1 52 is true. Since the command queue 1 8 7 is empty after formatting, as shown in Figure 9, the FIQ control logic 1 1 8 produces a value of true e 1 oad [ 0 ] signal 1 6 2, which will be valid new The formatted macro instruction loads EE 0 from the formatted command signal 197. The delete signal 141, kill0 signal 143, and F__valid 188 shown in Fig. 1, as shown in Fig. 9, are all false. However, since X I Q 1 5 4 is full, the valid bit XV2 149 is true, that is, input 2 of XIQ 154 is valid. In clock cycle 2, as shown in Figure 9, FV 0 1 3 4 is set to indicate whether EE 0 contains a valid instruction; register 1 8 3 outputs a value of lload[0] 142, new The instruction is loaded into ER0 220 and output as earl y0 signal 193 as input to instruction translator 138; new information about the new instruction is generated as X-rel-info 186; multiplexer 31 selects load The data input terminal 'and outputs the information of the new phase provided by X rel a info 186 as lateO 191 as the wheel release of XIQ 154 and multiplexer 172. However, since X I q 1 5 4 is full at the beginning of the second clock cycle, unlike the case shown in Fig. 9, the F I Q control logic 1 1 8 produces a value e s h i f t signal 1 6 4 which is false. The X I Q control logic 1 5 6 then cancels X I Q — f u 1 1 1 9 5 ' to thereby indicate that the instruction translator 丨 3 8 is ready to translate a new macro instruction during the third clock period. & Similarly, during clock cycle 2, control logic 1 〇 2 finds that a new instruction generated during the first - clock cycle must be deleted, and therefore produces a value of true in the second half of the second clock cycle. Delete signal 1 4 1. Because brother

1249131 Description of Invention (32) In the latter half of clock 2, 1 l〇ad[〇] 142 and the delete signal are both true, and according to Figs. 4 to 6, the kill〇 signal 143 is also true. Further, since the Iill〇 signal 143 is true, it can be seen from Fig. 7 that F_val id 188 is false. Because XIQ 154 is shifted down, XIQ } 54 is no longer "full" in the second clock cycle. XV2 1 4 9 turns false, indicating the command of the X丨qi 5 4 top item, also known as 'by XV 2 1 4 9 items that clearly indicate their effectiveness are no longer valid. In clock cycle 3, since the eshift signal 164 is false at the rising edge of the clock cycle cjk 2 0 2 , the new instruction is held in ER() 220 and is supplied to the instruction translator by ear ly〇1 93.丨38 is translated. Quite, FV0 134 remains true. The instruction translator 138 translates the new macro to the stomach order and provides the translated microinstruction 171 to the XIQ 154. Since u〇ad[〇] 142 is true at the rising edge of the clock cycle elk 2 02, the relevant information provided by a re 1 - 1 nf ο 1 86 in the second clock cycle is loaded into LR〇 "ο. Because at the other time of the pulse period, 11〇 is [0] 142 and lshift 168 is false," as shown in Figure = No, the content of LR 0 32 0, that is, the new information related to the instruction, will be passed through the lateO 191. Provided to XIQ 154. In the second = system logic 118 produces a value of true = ~ Γ instruction to hoke column = instruction at the fourth time (four) keep Γ ί in: pulse V according to Figure 4 to Figure 6, kill ° signal continues "5 input KE0 delete signal 141 is provided at = delete kiiio signal 143. Since kiUQ holds and passes through 1 8 8 for the entire clock cycle 3 裨 3 is true, F-va 1 1 d works within 3 is false to indicate that it is supplied to the instruction translator.

1249131 - t^9310076j__年月口 Di χ V, invention description (33) ' " , instruction 1 93 is invalid instruction. This step is necessary because the control logic 102 generates a true delete signal i4i == day during the period f2, and the command 丨97 generated in the pulse period 1 must be deleted. x v 2 i 4 9 followed by = further] The control logic assigns a false value to the nickname 1 41 (or cancels the delete signal 丨 4 1 ) within the clock cycle 3. In the clock cycle 4, since the new instruction is transferred out of the format, the command queue 1 8 7 , F V 0 1 3 4 turns false. At the rising edge of clock cycle 4, register 185 in Figure i loads eshift signal 164 and outputs a true value through lshift 168. In addition, the X I Q control logic 1 5 6 loads the translated microinstruction 1 7 1 and the instruction related information provided by 1 a t e 0 1 9 1 to the sense q 5 . However, because F_v a 1 i d 1 8 8 is false at the end of clock cycle 3, a false value is loaded into XV2 149 to indicate that the translated microinstruction 171 loaded into XIQ 154 is invalid. Therefore, the microinstruction 1 7 1 generated by the instruction translator 1 38 and loaded into the XIQ 1 5 4 in the clock cycle 3 is marked as invalid, and as expected, when it is output from the XIQ 1 5 4, Executed by the execution phase of the microprocessor 丨〇〇 pipeline. In one example, because the input of X丨Q 1 54 receiving microinstruction 171 is flagged as invalid, it may be overwritten by the next microinstruction. As can be seen from Figure 10, although the new macro instruction was generated during the first clock cycle and loaded into the formatted command queue 1 8 7 , the signal 1 4 1 is deleted until the second clock. The cycle will only be generated. The instruction deletion means in Fig. 1 conveniently enables the macro instruction to be deleted, i.e., marked as invalid, so that the execution stage does not execute the instruction that has been deleted. BRIEF DESCRIPTION OF THE DRAWINGS Figure 11 is a timing chart showing the operation of the instruction deleting apparatus shown in Figure 1 in accordance with the present invention. Except when the instruction formatter 1丨6 produces a new format

12829twfl.ptc Page 41 1249131 _ Case number 93100761__年月日日正正___ V. Invention description (34) After the macro instruction XIQ 1 5 4 is full and the formatted command is 丨8 7 not Outside, the Figure 1 is similar to Figure 10. The value of the delete signal 丨4 1 shown in Figure 1 must be loaded into the delete queue in the format corresponding to the project loaded by the new macro instruction in the formatted command queue 丨8, and the format After the instruction, the corresponding column is shifted downwards to ensure that the value of the correct deletion signal corresponding to the command can be deleted when the command queue 1 87 provides a new macro instruction after formatting. Offer it. The relevant details will be explained below. Therefore, the value of the register KR 1 (labeled as 4 2 1 in FIG. 4, labeled 521 in FIG. 5 and 6, and will be referred to as KR1 421 hereinafter) in the queue 1 4 5 is also deleted. Said in the middle. In the clock cycle 1 'XIQ a full 195 is true. As shown in Figures 9, 1 ', the instruction formatter 116 generates a new instruction on the formatted one instr 197, F - new - instr 152 is true. Because ΕΕ0 contains a valid instruction 'FV0 134 is true; however, as shown, since ΕΕι does not contain a valid instruction, the formatted instruction shown in Figure 1 is listed as the valid bit FV of item EE 1 of 丨8 7 1 1 3 4 is false. Thus, f I Q control logic 1 1 8 produces a value of true eload[ 1 ] signal 1 62, thereby loading a valid new formatted macro instruction of the formatted instruction signal 1 97 into ΕΕι. The letter 7 earlyO 193 provides the instruction stored in ΕΕ0, which is marked as 〇1\ instr in the figure; the signal lateO 191 provides the relevant information of the old finger saved in LE0' This information is marked as 〇1 dinf 〇 as shown. As shown in Fig. 10, the delete signal 141 & kill 〇 signal 143 in Fig. 1 is assuming that the dummy bit X V 2 1 4 9 is true. However, since ρ v 〇 1 3 4 is true, the delete signal 1 4 1 is false, so F a v a 1 i d 1 8 8 is true. K R 1 4 2 1 is for

1249131 Case No. 93100761 修正 Amendment 5. Invention Description (35) False. During clock cycle 2, FV1 134 is set to indicate whether EE1 contains a valid command and F V 0 remains in the set state. The old instructions are saved in ER 0 2 2 0, while the information about the old instructions is stored in LR 0 3 2 0. The register 183 outputs a value of li〇ad[l] 142. The new instruction is loaded into ER1 2 2 1 as shown. The new information associated with the new instruction is generated as X - rel - info 186, and the multiplexer 311 in Figure 3 will select the load data input, which is also provided to the scratchpad LR 1 3 2 1 . Because XIQ 1 54 is full at the beginning of the second clock cycle, FIQ control logic 118 produces an eshi f t signal 1 64 with a value of false. The XIQ control logic 1 56 then falsifies XIQ-f ul 1 1 95, whereby the instruction translator 丨38 will be ready to translate a new macro instruction during the second clock cycle. Also during clock cycle 2, control logic 1 〇 2 finds that a new instruction generated during the first clock cycle must be deleted, and therefore a true value is deleted in the second half of the second clock cycle. Signal 141. KR1 421 remains false. According to Figs. 4 to 6, since the instruction in ΕΕ0 of the command queue 187 after formatting in this example does not need to be deleted, the ki 11〇 signal 143 is false. Further, because ki 110 signal 143 is false, and FV() 134, 188 is false. Because XIQ 154 is shifted down by f吏 ί - ίίί — the clock cycle is no longer full and XV2 149 turns false. The instructions of the top 54 project, that is, the items whose validity is XV2 149, are no longer valid. . 20? Bu in period 3 'Because the eshift signal 164 rises to the meal during the clock cycle clk, the new instruction is kept in ER1 221, and the old instruction

Page 43 1249131

w is at -i / 20 ′ and is provided to the command translation by early0 193 =! FV1 and FV0 1 34 remain true. The instruction interpreter 1 38 sells the macro instruction and provides the translated microinstruction 171 to XIQ. Because in the other time zone of the clock cycle 3, i i〇ad[〇] 142 ^ 1 shift 168 is false, therefore, the content of lr0 32 〇, that is, the old

The old related information of the instruction will be provided to XIQ 54 through 1&4〇191. Since ii〇ad[0] 142 is true at the clock period clk 2〇2 rising edge, ί f is loaded into the LR 1 3 2 by the new correlation signal provided by X-rel-inf0 186 in the second clock cycle. 1. After the start of the third clock cycle, ρ丨q control logic 1-18 produces a true value of eshift signal 164 such that the new instruction is transferred from EE 1 to EE 第 during the fourth clock cycle. Also in the clock cycle 3, since 丨1〇ad[ i ] 142 and the delete signal 141 are true at the end of the clock cycle 2, a true value is loaded ΚΙΠ 421,

as the picture shows. However, according to Figures 4 to 6, the ki 11 〇 signal 丨 43 will remain false. Since FV0 134 remains true, F — valid 188 also remains true. Further, the control logic 丨〇 2 gives a false value to the delete signal 141 at the clock cycle 3. Port JU is in the clock cycle 4, because the new command is transferred from ΕΕΐ to ee〇, so F V1 1 3 4 is false. At the rising edge of the clock cycle 4, the X丨q control logic 156 loads the microinstruction 171 translated by the old instruction and the instruction related information supplied by Ute〇ι 91 into the XIQ 154. In addition, register 185 loads eshift signal 164 and outputs a true value via ishift 168. Since xiq 1 5 4 state is acceptable for another microinstruction, e s h丨f t is true. Because the rising edge e s h i f t signal 1 6 4 is true in the clock cycle c 1 k 2 0 2 , so new

12829twfl.ptc Page 44 1249131 --- Case No. 931007m V. Invention Description (37) The year 曰 π π — 令 令 令 令 令 令 令 令 令 令 ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER 〇 〇 〇 〇 Translation. FV〇 134 remains true. The instruction is translated into a 1 3 8 translation new instruction, and the obtained micro-instruction 丨 7 1 is provided to the 卩 卩 154. Since ishi ft 168 is true during clock cycle 4, the new instruction related information held at LR 1 3 2 1 is selected as the switching data input of multiplexer 3 1 , and is passed through 1 ate0 signal 191 Provided as shown. Similarly, in the clock cycle 4, the value of the delete signal 1 4 1 generated in the clock cycle 2 and stored in the delete block column 1 4 5, that is, the delete bit is transferred from KR1 421 to FIG. 4 KR0 4 2 0 (or KR0 5 2 0 of Figures 5 and 6). Therefore, it can be seen from FIG. 4 to FIG. 6 that it causes a value of 丨丨^ signal 143 to be generated. According to FIG. 7, F-valid 188 is correspondingly turned false. " In the clock cycle 5, because of the new instruction After being formatted, the instruction is queued 187, so FIQ control logic 丨18 clears FV0 134. At the rising edge of clock cycle 5, xiq control logic 156 will be provided by the new instruction translated by the new instruction 1 Π and provided by iate 191 The new instruction related information is loaded into ^ XIQ 154. However, since F - vaUd U8 is false at the end of clock cycle 4, a false value is loaded into XV2 149 to indicate the translation of XIQ 154 after loading. The microinstruction is invalid. Therefore, the microinstruction 1 7 1 generated by the instruction translator 1 3 8 in the clock cycle 3 and loaded into the XI q 1 5 4 is marked as invalid, and as expected, when its &XIQ 154 is output, It is not executed by the execution phase of the microprocessor 1 〇〇 pipeline. In one example, because the item used by χ j q 154 to receive microinstruction 171 is marked as invalid, it may be combined with the next microinstruction. 9 broken As can be seen from Figure 11, although the new macro instruction is in the first clock cycle

12829twfl.ptc Page 45 1249131 Case No. 93100761 V. The invention description (38) has been generated and loaded into format but not generated until the second clock cycle. Private π 仔 1 8 7, delete signal 1 4 1 to make the macro ♦ can be deleted, also the instruction in Figure 1 deletes the shock, the execution phase will not execute the deleted command, the flag is invalid, so Although the present invention and its g, #: 々 细 解释 , , , , , , , , 。 。 。 。 。 。 。 。 。 。 。 。 点 点 点 点 点 点 点 点 点 点 、 For example, although the ρ and 夕 I commands must be deleted in the text, the instruction in the = has been deleted. In addition, although::: still:] In other cases, the macro instruction is translated into the actual two of the micro-instruction, and the fan is one, indicating that the microprocessor makes the computer u!sc) instead, the solution·sc refers to: micro= g: An example of translation into a microinstruction does not deviate from the predictable implementation of the present invention; in addition to implementing the invention by hardware, it can also be read by a computer, computer readable code, data, etc. in _ A computer can be implemented in the media (as can be =). Such computer code can cause the invention, the imitation, or both. For example, this feature can be implemented in a common programming language (such as C, C++, JAVA, and other similar languages); it can also use the GDSII database, hardware description language (HDL), including Veril〇g HDL, VHDL, Altera HDL (AHDL), etc., or other programs and/or circuits (such as schematic) capture tools such as tool memory implementations. The computer code can be stored in any computer-usable (eg readable) media, including peninsula memory, magnetic disk, CD-ROM, CD-ROM, DVD K3M and similar products, or can be placed on a computer as computer data (eg Readable) media (such as carrier or other media including digital \ optical,

12829twfl.ptc Page 46 1249131 _ Case No. 93100761_Yearly 曰 Amendment _ V. Invention Description (39) or analog media). As a result, computer code can be spread across communications networks, including the Internet and corporate intranets. As part of intellectual property, the invention may be embodied in a computer code core, such as a microprocessor core, or in a system-level design, such as a microcontroller system (S0C), and is transferred as part of an integrated circuit product. To the hard body. At the same time, the invention can also be implemented by a combination of hardware and computer code. In the following, those skilled in the art can make some modifications or modifications to the equivalent embodiments by using the above-disclosed technical contents without departing from the technical solutions of the present invention. Any simple corrections, equivalent changes and modifications made to the above embodiments in accordance with the technical spirit of the present invention are still within the scope of the technical solutions of the present invention.

12829twf1.ptc Page 47 1249131 _Case No. 93100761_年月曰 修正 Revision _ Schematic description of the drawing Fig. 1 is a schematic structural view of a microprocessor according to the present invention. Figure 2 is a block diagram showing the first array of command strings formatted in Figure 1 in accordance with the present invention. Figure 3 is a block diagram showing the structure of a second array of command strings formatted in accordance with Figure 1 of the present invention. Fig. 4 is a block diagram showing the first example of the deletion queue shown in Fig. 1 according to the present invention. Figure 5 is a block diagram showing the second example of the delete queue shown in Figure 1 in accordance with the present invention. Figure 6 is a block diagram showing the third example of the delete queue shown in Figure 1 in accordance with the present invention. Figure 7 is a block diagram showing the structure of the FIQ control logic for generating the F_valid signal of Figure 1 in accordance with the present invention. Figure 8 is a flow chart showing the operation of the microprocessor instruction deletion device of Figure 1 in accordance with the present invention. Fig. 9 is a timing chart showing the principle of operation of the instruction deleting apparatus shown in Fig. 1 in accordance with the present invention. Figure 10 is a timing diagram showing the operation of the instruction deleting apparatus shown in Figure 1 in accordance with the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 11 is a timing chart showing the operation of the instruction deleting apparatus shown in Figure 1 in accordance with the present invention. Schematic description: 1 0 0 ··Microprocessor 1 0 2 : Control logic

12829twfl.ptc Page 48 1249131 Case No. 93100761 Brief Description of Patterns 104 Instruction Cache Memory 106 Branch Target Address Cache 108 Predecode Logic 111 X _ Shift Signal 112 Instruction Byte Buffer 1 14 Instruction Bytes Buffer Control 116 Instruction Formatter 118 FIQ Control Logic 132 Early Array 134 Valid Bit 138 Instruction Translator 141 Delete Signal 142 1 1 〇ad Signal 146 Late Queue 148 X_va 1 id Signal 149 Valid Bit 151 I Stage 152 F_new_instr Signal 153 F stage 154 translated instructions queue 155 X stage 156 XIQ control logic 157 R stage 161 control signal _Ά 曰 correction

12829twf1.ptc Page 49 1249131 _ Case No. 93100761_Year Month Day_Revision Diagram Simple Description 1 6 2 : e 1 〇ad Signal 164 : eshift Signal 164 : X_load Signal 1 6 7 : Command Bits 1 6 9, 1 9 6 : Pre-decoding information 1 7 1 : Micro-instruction 1 7 2 , 1 7 8 : Multiplexer 1 7 5 : Predicted branch target address 1 7 6 : Execution stage register 1 7 7 : Correction bit Address 1 7 9 : Next target address 1 8 1 : Current selected address 1 8 2 : Current instruction indicator 1 8 3,1 8 5 : Register 186 : X_rel_info signal 1 8 7 : Formatted command伫Column 188: F_valid signal 1 8 9 : Valid bit register 1 9 1 : Late signal 1 9 3 : Early signal 1 9 4 : Branch prediction related information 195 : XIQ_ful1 Signal 1 9 7 : Formatted instruction 198 : F_instr_info signal

12829twf1.ptc Page 50 1249131 _ Case No. 93100761_ Year Month 曰 Correction _ Simple Description of the Drawing 199 : FIQ_ful1 Signal 2 0 2 : Clock Signals 210 , 211 , 212 , 310 , 311 , 312 , 410 , 411 , 412 , 509, 5 1 0 , 5 1 1 , 5 1 2 ··Multiplexer 220,221,222,320,321,322,420,421,422,520, 5 2 1 ,5 2 2 : register 6 0 2 , 71 2 : Inverter 604 , 606 5 714 : and gate 6 0 8 : or gate

12829twf1.ptc第51页

Claims (1)

1249131 Case No. 93100761 Correction of the installation of the month, in addition to the ^ 0 book of the order of the order of the 》 猬 猬 猬 猬 一 一 一 一 一 & & 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 六 六 六 六 六 六 六 六 周In the case of the first order of the order, the order of the order is the order of the order, and the order is the end of the line. In the period of the Zhou dynasty, the first pre-transmission; the value used, the birth number of the birth letter, the deletion of the week, the third and the third week, the first week before the pulse, into the second, the first month, January, I believe that the number is deleted from the letter to the letter and decoupling. The list of the child's birth and the deletion of the week is the same as the time of the second, as stated in the mc-, J1 column. If the micro-division is deleted, it will be the coupling of the order, and the sign-and-sale form will be used by the letter; if the sexual use is effective, the value of the output will be deleted. . The depreciation is described as the former value. The period is circumscribed by the periodical rr. There are two cases in the first period. The former true range of Fan Li is requested to apply for the root of the Zhou Shumai, the second item, the first and the last period. In the middle of the first ο mid-term, the circumstance of the circumstance of the circumstance, except for the deletion of the same order, the period of the second round of Fan Li’s request for the syllabus of the Zhou dynasty. In the middle of the week, in addition to the deletion of the pre-order, the fashion is also included in the deduction of the order. 1X The following paragraphs Fan Li’s application for the application of the package is included in the second paragraph. In addition to deleting the to the coupling # 信入4 and the order of the order to the time of entry into the period of the period is no. Order the month in the bottom of the item I2829twfI.ptc Page 52 1249131 VI--93100761 _ , Apply for a patent ^ ^ According to the application patent Fan HI Chu / 1 right, the above loading signal is true, then, the brother, the 4: staff, the instruction to delete the device, such as R The cycle is the same clock cycle; the L-one pulse cycle and the aforementioned second time 5 are loaded into the letter of the month, which is a special holiday, and the instruction described in ^f/4f is deleted after the pulse cycle. The second clock cycle of the second phase includes 7:, the instruction to delete the device according to the fourth paragraph of the patent application scope, and 2 according to the preceding: column: used in the aforementioned second clock week a value of 8 to generate the aforementioned validity signal, except for the aforementioned deletion signal outputted by the queue, in addition to the instruction deletion device described in item 1 of the exclusive application of the monthly package, the plurality of items are used for The hard number of the storage of the first eight, except for the signal, corresponds to the number of clock cycles, and according to the patent application, the number of the deleted devices is deleted. The load data round:::- all include a load statement delete signal.鸲 is coupled to the corresponding item to receive ^1 〇, according to the instruction deletion device described in the foregoing plurality of deletions in the patent r3, the data input terminal, each of the retention entities includes one Keep the current value of this corresponding item. The 6th end is coupled to the corresponding item to receive π, according to the instruction to delete the device according to the application of the patented cadre 8th, 12829twfl.ptc page 53 1249131 _ case number 93100761_ year 曰 correction _ 6. Patent application scope Each of the plurality of deletion queue items includes a transfer data input end, and the transfer data input end is coupled to the corresponding item to receive the plurality of delete queue items located above the corresponding item. One of the plural values of the deleted signal from the project. 1 2. The instruction deletion device according to item 8 of the patent application scope, wherein the instruction queue includes a plurality of items for storing a plurality of instructions, and the plurality of deletion queue items are used for storing the plurality of instructions. The value of the aforementioned delete signal corresponding to the plurality of instructions in the column item. 1. The instruction deletion device according to claim 1, wherein the instruction comprises a variable length instruction. The instruction deletion device according to Item 13 of the patent application scope, wherein the variable length instruction comprises an instruction of an X8 6 structure. 15. The instruction deletion device according to claim 13 of the patent application scope, wherein the instruction is provided to the instruction queue by the instruction formatter in the first clock cycle, and the instruction formatter determines the length of the instruction. The instruction deletion device according to claim 1, wherein the instruction is output to the instruction translator by the bottom command item in the second clock cycle to be translated into one or more microinstructions. And selectively executed by the microprocessor according to the aforementioned validity signal. 17. A method of deleting an instruction in a microprocessor, comprising: loading an instruction in a first queue during a first clock cycle; a second clock after the first clock cycle Generating a delete signal; loading a value of the aforementioned delete signal during the aforementioned second clock cycle 12829twf1.ptc Page 54 1249131 _ Case No. 93100761_Yearly revision _ 6. The patent application scope is in a second queue; in a third clock cycle, it is determined whether the aforementioned value in the second queue is true The instruction is output by the bottom end item of the first array in the aforementioned third clock cycle; and if the foregoing value is true, the foregoing instruction is executed. The method of deleting an instruction in a microprocessor according to claim 17, wherein the third clock period and the second clock period are the same clock period. The method of deleting an instruction in a microprocessor according to claim 17, wherein the third clock cycle is a next clock cycle of the second clock cycle. The method of deleting an instruction in a microprocessor according to claim 17 of the patent application scope, further comprising: formatting the foregoing instruction before loading the foregoing instruction into the first queue. The method for deleting an instruction in a microprocessor according to claim 17 of the patent application scope, further comprising: after loading the foregoing instruction in the first queue, determining whether the instruction is in the first Moving downwards within the queue; and if the aforementioned instruction has been shifted downward in the first sequence, after loading the value of the delete signal into the second queue, the value of the delete signal is in the second Move down the column. 2 2. The method for deleting instructions in a microprocessor according to claim 17 of the patent application scope further includes: 12829twf1.ptc Page 55 1249131 _ Case No. 93100761_年月日日_Μ-_ VI. Patent Application Scope Before the above instructions are loaded into the first queue, the above instructions are predicted to be branch instructions; Performing an error prediction of the command; and in response to the erroneous prediction of the foregoing finding, performing the foregoing operation of generating the aforementioned delete signal in the second clock cycle. 2. A method of deleting an instruction in a microprocessor according to the scope of claim 2, wherein a branch address of the microprocessor caches the memory to perform the prediction of the branch instruction. The method of deleting an instruction in a microprocessor according to claim 22, wherein the error prediction of the branch instruction includes an error prediction of the length of the branch instruction. The method of deleting an instruction in a microprocessor according to claim 22, wherein the error prediction of the branch instruction includes an error prediction of the branch instruction address. The method of deleting an instruction in a microprocessor according to claim 22, wherein the error prediction of the branch instruction includes determining that the non-branch instruction is an error prediction of the branch instruction. 2 7. The method for deleting an instruction in a microprocessor according to claim 17 of the patent application scope, further comprising: performing, according to a prediction by a branch instruction, the microprocessor branch processing, the instruction is a branch instruction The next instruction; and after the microprocessor branch is processed, the operation of generating the aforementioned delete signal is performed in the aforementioned second clock cycle. 2 8. Deleted in the microprocessor according to item 17 of the scope of application for patents 12829twf1.ptc Page 56 1249131 _ Case No. 93100761_Yearly revision _ 6. Application of patent scope In addition to the instruction method, wherein the foregoing instruction is the next instruction of the predicted branch instruction, the method further includes: It is found that the aforementioned branch instruction is predicted to be performed, and the operation of generating the aforementioned delete signal is performed in the aforementioned second clock cycle. A microprocessor comprising: a first serial array for receiving an instruction and buffering; a logic coupled to the first queue for discovering that the aforementioned instruction cannot be used by the microprocessor Execution of the foregoing, wherein the foregoing logic produces a true value on a signal, wherein the signal having a true value is generated after the foregoing instruction is received by the first queue; and a second array coupled to The foregoing logic is configured to load the foregoing signal having a true value and then output the foregoing true value simultaneously with the foregoing first array outputting the foregoing instruction, wherein the microprocessor responds to the foregoing signal having a true value and invalidates the foregoing instruction without performing the same carried out. The microprocessor of claim 29, wherein the second serialization comprises: a plurality of storage units for storing the foregoing signals generated by the logic in a corresponding plurality of clock cycles Multiple values. The microprocessor according to claim 30, wherein the first queue includes a plurality of storage units for storing a plurality of instructions, wherein the plurality of storage units of the second array are used for And storing a plurality of signal values corresponding to the plurality of instructions stored in the plurality of storage units of the first queue. 3 2. A computer-usable transmission medium for storing a data message 12829twf1.ptc Page 57 1249131 _ Case No. 93100761_Yearly revision _ 6. Application patent range number, the data signal includes: A computer readable code, used to provide a device to delete when read and executed by the computer An instruction to load a microprocessor command queue in a first clock cycle and output by a bottom-end item in a second clock cycle, and the second clock cycle is after the first clock cycle The computer program code includes: a first code, which is read and executed by the computer to provide a delete signal for transmitting a value generated in a third clock cycle after the first clock cycle; The second code, which is read and executed by the computer, is used to provide a delete queue coupled to the delete signal for loading the value of the delete signal generated by the third clock cycle, and in the second time And outputting the value of the foregoing delete signal in a pulse period; and a third code, which is used by the computer to read and execute to provide a validity signal, coupled to the deletion queue, the validity signal is in the second clock cycle Health, used to indicate whether the instruction is to be executed by the microprocessor, wherein, if the value of the output signal of the deleted in the second clock cycle delete queue true, then the validity signal value is false. 12829twf1.ptc第58页