TWI232403B - Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts - Google Patents

Abstract

An instruction buffering apparatus is disclosed. The apparatus includes an early queue and a late queue. The early queue receives an instruction generated during a first clock cycle. The late queue receives information related to the instruction during a second clock cycle subsequent to the first clock cycle. The early queue receives load/shift control signals for loading/shifting the early queue. Registers receive the early queue load/shift signals and provide delayed versions of the signals to the late queue for controlling loading/shifting the related information in the late queue. The late queue is configured such that when the apparatus is empty, the related information may be provided during the second clock cycle, i.e., in the same clock cycle that its related instruction is provided from the early queue.

Description

1232403 V. Description of the invention (1) Priority information [000 1] This application claims the priority of the following U.S. applications: Case No. 10 / 422,057. The application date is April 23, 2003. [Technical Field to which the Invention belongs] [0 0 0 2] The present invention relates to the field of pipe 1 ining of a microprocessor, and particularly to instruction buffering in a pipelined microprocessor. [Prior art]

[00 0 3] Modern microprocessors are all pipelined microprocessors. That is, several instructions can be executed simultaneously in different blocks or pipeline stages of the microprocessor. Hennessy and Pat Son defined pipeline execution as "an implementation technique in which multiple instructions can be executed on top of each other." See Computer Architecture · Quantitative Methods (Second Edition), 1996 by Morgan Kaufmann, San Francisco, California, Corporate Printing, John L. Hennessy PattersOn. Then they gave the following brilliant explanations of pipeline execution: Pipelines are similar to assembly lines. There are many steps in a car assembly line, each of which contributes to the construction of the car. Each step is performed on the same car, but will run in parallel with the other steps. In the electricity, monthly package pipeline, each step will complete a part of the instruction. Like the assembly line, the = synchronous scale will complete different parts of different instructions in parallel. Each of these steps is called a pipeline stage or pipeline section. These are connected to the next stage and form a pipe finger; they will enter 1232403 from one end. 5. Description of the invention (2) After passing through these stages and leaving from the other end, it is often [0004]. Every time a clock cycle passes, the instruction starts from , Operation. The passage passed to another stage. In the car assembly line, = ° of the official line is a stage where there is no car to be assembled and it is in an idle state: this = H performance will be reduced. Similarly, if the microprocessor is capable of doing this, and the -clock period is idle (commonly known as a pipeline bubble), the processor's performance will decrease. Mo [0 0 0 5] In this specification, each of the microprocessor pipelines can be logically divided into two parts. The upper part will be extracted and solved: the second part is = sent to the lower part of the command. The upper part usually includes instructions: fetching program instructions from δδ memory. Because it takes a long time to extract the second finger from the system memory, the upper part of the household also includes the instruction cache. The second instruction fetches the instructions extracted from the memory to reduce subsequent instructions; The main king prepares these instructions when the execution phase is ready to execute the 4th command. Dian Fan [00 0 6] To avoid bubbles in the execution phase, one method usually used in the upper pipeline is to read the program in advance and fetch multiple program pointers k to the private buffer. The instruction buffer sends the instruction to the execution stage where the instruction is ready to execute. The instruction buffer is often configured as FIFO or queue. [0007] Instruction buffering technology is particularly helpful when one or more of the instructions required in the execution stage are not present in the instruction cache memory. In this case, my brother ’can reduce the impact of how many missing cache lines are

1232403 V. Description of the invention (3) Timing of memory recall. [0008] It is also useful that the instruction buffer can provide instructions to the execution stage. In the case of a program with branch instructions, buffering technology. Modern microprocessors use branch prediction logic to predict whether branch instructions will be taken. If it is taken, the target address of the branch instruction is generated, and the instruction is fetched from this target address instead of the next sequential fetch address and sent to the instruction buffer. [0091] In the case that some processing must be performed before the instruction is sent to the execution stage, the 'instruction buffering is also helpful. For example, in some processors, the instruction set allows the length of the instruction to be a variable number of bytes. Therefore, the processor must decode a string of instruction bytes and determine the type of the next instruction to determine its length. The beginning of each instruction is determined by the long production of the previous instruction. This procedure is often called instruction formatting. Since instruction formatting requires some processing time, it is helpful to format multiple instructions and buffer the formatting instructions in the upper part of the pipeline. "Formatting instructions can be sent to the execution stage for processing. & Amp % # [0010] In addition to the fetch instruction, the information related to the instruction is also extracted in the upper pipeline stage. 'These information is not physical and measurement related information, and the execution phase may be combined = the child's knife pre-calendar, or correcting the wrong prediction. φ = X Updates the branch prediction longitude, which must be processed in the $ command. Another example is the case where the instruction is long. The 7L group is ready to be sent to the instruction buffer. The pointer associated with it must be executed on the processor. Variable-length instructions come. Related information may be generated after the instruction's clock cycle.

Page 10 1232403

V. Description of the invention (4) The orders are sent to the execution stage synchronously. [0011] One solution to this problem is to add another pipeline stage, giving the relevant information more time to buffer and send to the execution stage. However, this approach has the disadvantage of potentially reducing performance. In particular, when a branch instruction is predicted to be wrong, all pipeline stages before the branch instruction that is predicted to be wrong must be cleared of its instructions, and the fetch of instructions must be returned to the branch where the J is wrong. The more stages that need to be emptied, the more likely it is that the execution phase of the microprocessor pipeline will generate bubbles. Therefore, it is desirable to have as few pipeline stages as possible. Therefore, this problem requires a better way.

[Summary of the Invention] [0012] Set the receiving instruction to the buffer buffer and generate this segment. Therefore, for the purpose of providing a set of items, in which only a few items are obtained, the second line, the item, each item is placed in %%, the approach to the problem is to be one clock later than a buffer byte. 'Cycle' will be associated with the finger and punch device. This device includes an item that can be sent to the execution stage in the same clock cycle when the instruction = enables the relevant instruction information to effectively bypass the buffer. If the above is started, a feature of the present invention is The k-buffer device in the buffered pipelined microprocessor is not loaded until the P request is 7 and the relevant Besson device is installed: at least-the clock cycle after the fetch instruction :::. This device includes a first row, which has Γ, 2 storage and 1 ream. This device also includes items related to a corresponding instruction in the second plurality of items in the first plurality of items.

5. Description of the invention (5) ^: This device further includes a plurality of control signals coupled to the first queue, including multiple guarantees: the instructions are in the-queue. This device also has some control signals to load, shift and hold relevant information. Slow = 113. ] In one aspect, a feature of the present invention is to provide a finger (u.a. the buffer includes a plurality of multiplexed registers, Luo ~: eglSter), each of which is used to store an instruction. This instruction buffer also contains a number of temporary and balance information. This instruction buffers the instruction in dm: register to generate a control signal to selectively store one of the instructions ^ temporarily. This instruction buffer also includes-value, and is in the-first; in the first clock cycle, 'receives the value on the control signal and n after the first pulse capture cycle: select; in these multiplexed registers = = Among them, the related information of the two temporary-type wickers. [0014] In another aspect, a processor of the present invention. The microprocessor includes an instruction and a branch instruction for a micro-pulse period, and outputs a branch instruction: = device; used in the first time series, used in the first umbilical cord, using the date α processor and includes a control The logic is used in the second clock cycle after the first clock cycle: Information about the prediction of the branch instruction. A buffer is generated at this place, which is coupled to the instruction formatter, including-the instruction buffers this branch instruction, and receives it in the second clock cycle = period = 1232403 V. Description of the invention (6) ___

The buffer selectively outputs this information during the first clock cycle. Mang Ergong 'is not empty during the second clock cycle, and then during the second clock cycle. [0015] On the other hand, the item of the present invention selectively buffers this information. An entry feature in a microprocessor with a pipeline is to provide a method for using this method to include the second and second information in the first clock cycle. And the second clock period after the first clock period is listed with relevant information. The method also includes judging whether the index is related to this instruction, whether to move out of the queue, and in the first clock cycle period, the order is not removed from the queue, and the correlation is related. Information along with this instruction is sent to the pipeline, bypassing this queue. [0016] On the other hand, the invention has a buffer and a buffer. The instruction buffer includes a first terminal, a finger terminal, a data input terminal, and an ancestor. It has an instruction to receive an instruction in an output cycle, and a 铨, the input terminal to receive the first clock number. . If the value of this control input is], j is used to receive the first control signal input, otherwise it will choose to keep the data lost: the multi-server selects the load data including the first temporary buffer with the crying command buffer and An input terminal, and an output terminal coupled to one of the two output terminals of the first multiplexer. The instruction buffer also includes an output output terminal, which is one of the input terminals of the temporary storage cache material. This instruction buffer also includes the first-night, one input terminal with one input terminal and one or two temporary registers. Round = :: Worker, which has a data input terminal that is lightly connected to the first terminal and a second temporary load. The output of the register is loaded into the input terminal of the Behr wheel at the first clock! 232403 V. Description of the invention (7) _ After the cycle _ + /-Control input terminal: ^: ^ receives information related to the instruction , And if true, then the second multiplex—control signal. If the value of this control input is the data input. These two j, contained) data round-in end 'Otherwise, the round-end end of the data will be selected. The buffer also includes a third register, which has an output end to receive the first- The control signal and an input-control signal generate a second control signal within π :. Therefore, if within the period, the revolving period is true, then in the second clock cycle [οοπΐ: Said an ancient customs information ° Face included in the transmission medium? The invention-item feature is to provide a species-internal brain readable range π, 61 shellfish number. This computer data signal includes the electrical instruction II :; T, the microprocessor provides-a kind of slow] code to get this related information. This code includes the first-Cheng line for the green line, which has a first plurality of items, each one looking-Yu Yi ^ This task code also includes a second code to provide = a line, which has a corresponding In the first plurality of Zhao

"Each item is used to store a corresponding one in the first row; ㈡J i includes a third code to provide a plurality of control signals to tap into the Ding row for loading, shifting and holding The first instruction. This code also includes a fourth code to provide a plurality of temporary registers, receive the control signals, and roll out the system signals delayed by one clock cycle to load, shift, and hold. The related information in the second queue is two. [0018] An advantage of the present invention is that an instruction buffer or queue can be used without adding another pipeline stage to improve the processor's 1232403. V. Description of the invention (8 ) Yes. After cooperating with the following description [0 0 1 9] other features and advantages of the present invention and the accompanying drawings, it will be more prominent. [Embodiment] [〇0 2 4] Please refer to FIG. The block diagram of the microprocessor of the present invention. The microprocessor 100 is a pipelined processor including multiple pipeline stages. The figure shows a part of the stages, that is, stages 5 and F. -Stage 153, X-stage 155 and R-stage 157. Bu stage 151 includes from The stage of fetching instruction bytes in memory or instruction cache. In one embodiment, 'I-phase 151 includes a plurality of phases. F-phase 153 includes formatting a string of unformatted instruction bytes into Phases of formatting instructions. Χ-phase 1 55 includes the phase of translating formatted giant instructions into micro instructions. R-phase 157 includes the register phase of loading operands from the register file. Microprocessor 1 0 The other execution phases of 0 are not shown, such as the address generation phase, data phase, execution phase, storage phase, and result write-back phase that follow R_phase 丨 57. [〇〇25] Microprocessor 1〇〇 Includes the instruction cache memory 104 in the stage 151. The instruction cache memory 104 will cache the instructions fetched from the system memory coupled to the microprocessor 100. The instruction cache memory 丨〇4 Receives a current fetch address 181 to select an instruction byte 167 of a cache line for output. In one embodiment, the instruction cache memory 104 is a multi-level cache memory of k , That is, when the instruction cache memory 104 is more than one Pulse period ’to output the cache line corresponding to the current fetch address 1 81. ΙΗϋ

Page 15 1232403 V. Description of the invention (9) ----- 17Q [0026] The microprocessor 100 also includes a multiplexer in the I-stage 151. The multiplexer 178 will provide the current extraction address 181. The multiplexer 178 will pick up the next sequential fetch address 丨 79, which is the current fetch address 181 plus the size of the cache line stored in the memory 7 04. The multiplexer 78 will also receive a correction address 177, which specifies the address of the desired branch of the microprocessor 100 to correct the branch prediction error. The multiplexer 78 will also receive a predicted branch target address 1 7 5. [0 027] The microprocessor 100 also includes a branch target in the stage 15-address cache memory (BTAC) 106, which is coupled to the multiplexer 178. BTAC 1 0 6 will respond to the current fetch address 丨 8}, and generate the predicted branch target address i ° BTAC 106 will cache the branch target address of the executed branch instruction and the address of the branch instruction itself. In one embodiment, BTAC 106 includes four-way set associative cache, and each way of the selected set contains multiple items for storing the target address and predicting branches. Branch prediction information for instructions. In addition to the prediction target address 175, BTAC 106 also outputs branch prediction related information 194. In one embodiment, the BTAC information 194 includes: an offset for designating the location of the first byte of the branch instruction within the instruction cache line selected by the current fetch address 1 81; an indication To indicate whether the predicted branch instruction crosses the boundary of the half-cache line (hal f-cache 1 i ne); the valid bits of each item in the selected || path; indicate which— in the selected set— The road is a least- recently-used instruction; an indication of which of the selected items of the road is the least recently used; and a prediction as to whether a branch instruction will be taken or not taken.

Page 16

1232403 Description of the Invention (10) [0028] The microprocessor 100 further includes a control logic 102. If the current fetch address 181 matches the effective cache address of a previously executed branch instruction in BTAC 106, and if BTAC 106 predicts that the branch instruction will be taken, then control logic 102 controls multiplexer 178 to select BTAC The target address is 175. If a branch prediction error occurs, the control logic 102 controls the multiplexer 178 to select the correction address 1 7 7. Otherwise, the control logic 102 will control the multiplexer 178 to select the next sequential fetch address 179. The control logic 102 will also receive BTAC information 194. ,.

[0029] The microprocessor 100 also includes pre-decoding logic 108 'in stage 151, which interfaces to the instruction cache memory 104. The pre-decoding logic 108 will receive the cache line of the instruction byte 丨 67 sent by the instruction cache memory 104 and the BTAC information 194 to generate the pre-decoding information 169. In one embodiment, the 'pre-decode information 1 69' includes: a bit associated with each instruction byte, which predicts whether the byte is an opcode (opcode) of a branch instruction that BTAC 106 predicts to take. ) Byte; the bit used to predict the next instruction length is based on the predicted instruction length; the bit associated with each instruction byte predicts whether this byte is a preamble to the instruction Prefix bytes; and prediction of branch instruction results.

[0030] The microprocessor 100 also includes an instruction byte buffer 112 in the F-phase 153, which is coupled to the pre-decoding logic 108. The instruction byte buffer 112 receives pre-decode information 169 from the pre-decoding logic 108 and receives instruction byte 167 from the instruction cache memory 104. The instruction byte buffer 11 2 sends the pre-decoded information to the control logic 102 via a signal 1 96. In one embodiment, the instruction byte buffer 2 can buffer up to four cache lines.

Page 17 1232403 V. Instruction byte (11) and related pre-decoding information. [0031] The microprocessor 100 also includes an instruction byte buffer control logic 1 4 which is coupled to the instruction byte buffer 丨 2. The instruction byte buffer control logic 114 is used to control the instruction byte and related pre-decode information to flow into and out of the instruction byte buffer 112. The instruction byte buffer control logic 114 also receives BTAC information 194. [0032] The microprocessor 100 also includes an instruction formatter 116 in the F-phase 153, which is coupled to the instruction byte buffer 112. The instruction formatter 11 β receives the instruction byte and pre-decode information 1 6 5 from the instruction byte buffer 11 2 and generates a formatting instruction 197 from it. That is, the instruction formatter 116 looks at a series of instruction bytes in the instruction byte buffer device 1 12 to determine which byte includes the next instruction and the length of the next instruction 'and sends the next instruction The output is 0.]: 11 ^ 1 ^ 6 (1-1131 1: 1: 1197. In one embodiment, the formatting instructions provided by [01 ^ 31; 1 ^ (1 "1 ^ 1 ^ 1 97 include It substantially conforms to the instructions with a 6-architecture instruction set. In one embodiment, the formatting instructions are also called giant instructions, which are translated into micro instructions that can be executed by the execution stage of the microprocessor 1000 pipeline. For mat ted_i ns tr 197 is generated in the F-stage 153. Each time the instruction formatter 116 outputs formatted an instr 197, the instruction formatter 116 will generate a true value of F — new — instr signal 152, which is indicated in for mat ted — A valid formatting instruction appears on instr 197. In addition, the instruction formatter 116 will output the relevant information of 〇〇1 & 1 ^ 6 (1 一 丨 1131:]: 197 to the control logic 1 via the signal F_instr_info 198. 〇 2. In the embodiment, F —ins tr_ inf ο 1 98 includes: whether a branch instruction will be taken

Page 18 1232403 V. Description of the invention (12)

Prediction of whether or not to be taken (if the instruction is a branch instruction); the preamble of the instruction; whether the instruction address hits the microprocessor's branch target buffer; whether the instruction is a far direct branch instruction ); Whether the instruction is a far indirect branch instruction; whether the instruction is a call branch instruction; whether the instruction is a return branch instruction; whether the instruction is a far return branch instruction; whether the instruction is an unconditional branch instruction; In addition, the instruction formatter 6 outputs the address of the formatted instruction via the current instruction indicator (C IP) signal 1 8 2. This indicator is the address of the previous instruction plus the length of the previous instruction.

[0 033] The microprocessor 100 further includes a formatting instruction queue (F I Q) 1 8 7 in the X stage 155. The formatting instruction queue 1 8 7 will receive fmatmatted_instr 197 from the instruction formatter 116. Format command queue 187 will also

Format command is output via ear lyO signal 193. In addition, the formatting instruction queue 1 8 7 will receive the information about the formatting instruction received through the control logic 1 02 via the signal X_re 1 — i n f ο 1 8 6 from the control logic 1 02. X-re 1-info 186 was created in X-phase 155. The format command queue 1 8 7 also outputs information related to the format command (which is output via ear 1 y 0 signal 1 93) via 1 a t e 0 signal 1 91. The formatting instruction queue 1 87 and X —re 1 _info 186 will be described in more detail below. [0034] Microprocessor 1 § 100 also includes formatting instruction queue (FIQ) control logic 118. The F IQ control logic 11 8 will receive F_new_ins tr 152 from the instruction formatter 116. When the formatting instruction queue 187 is full, the FIQ control logic 118 will generate a true value of FIQ_full signal 199, which will be sent to the instruction formatter 116 ° The FIQ control logic 118 will also generate an eshift signal 164.

Page 19 1232403 V. Description of the invention (13) Controls the shift of the instructions in the formatting instruction 彳 178. The f IQ control logic 11 8 will also generate a plurality of e 1 oad signals 1 62 to control the action of loading the instruction from formatted_instr 197 into the empty item in the formatting instruction array 187. In one embodiment, the F IQ control logic 118 generates an elOad signal 162 for each item in the formatting instruction queue 187. In one embodiment, the formatting instruction queue 187 includes 12 items, and each item stores a formatting giant instruction. However, for the sake of brevity, Figures 1 to 3 show a formatting instruction queue including three items 1 8 7; therefore, Figure 1 shows three el oad signals 162, which are represented by el oad [2: 0] 162 Means.

[0 0 3 5] The F I Q control logic 11 8 will also record the relevant valid bit 1 3 4 of each of the items in the formatting instruction array 1 8 7. The embodiment shown in FIG. 1 includes three significant bits 134, which are represented by V2, VI and V0. VO 1 34 is the effective bit corresponding to the lowest item in the formatting instruction queue 1 8 7; v 1 1 3 4 is the effective bit corresponding to the middle item in the formatting instruction queue 1 87; V2 1 34 Corresponds to the most significant bit in the format command queue 1 87. The FIQ control logic 118 also outputs an F-valid signal 188, which is V0 134 in one embodiment. The valid bit 134 indicates whether the corresponding entry in the formatting instruction column 1 8 7 contains a valid instruction. The f I Q control logic 118 will also receive a XIQ_full signal 195.

[0036] The microprocessor 100 also includes an instruction translator 138 in the X-phase 155, which is coupled to the formatted instruction queue 187. The instruction translator 138 receives the formatting instruction 'in the early0 signal 193 from the formatting instruction queue 187 and translates the formatting giant instruction into one or more microinstructions 171. In one embodiment, the microprocessor 100 includes a reduced instruction set computer (reduced

Page 20 1232403 V. Description of the invention (14) instruction set computer (RISC) core to execute micro-instructions of nat ive or reduced instruction set.

[0037] The microprocessor 100 further includes a translation instruction queue (XIQ) 154 in the X-phase 155, which is coupled to the instruction translator 138. XIQ 54 buffers the translated microinstructions 171 received by the instruction translator 138. The xiq 154 also buffers the relevant information received from the formatting command line 87 via the lateO signal 191. The information received through the lateO signal 191 is related to the microinstruction 1 7 1 'because it is related to formatting the giant instruction (the microinstruction is paid by transferring 5 中). The execution phase of the micro-processing 100 will use the relevant information 191 to execute the relevant micro-instruction 171. [0038] The microprocessor 100 further includes a xiq control logic 156, which is lightly connected to the XI Q 154 ° XIQ control logic 156 receives an F-valid signal 188 and generates a XIQ_full signal 195. The XIQ control logic 156 also generates X-ioa (j signal 164, to control the action of loading the translated microinstruction 171 and related information 191 into XIQ 154. [0 0 39] The microprocessor 100 also includes X -Multiplexer 172 at the input of phase 155, which is coupled to XI Q 154. Multiplexer 172 is used as a bypass multiplexer to selectively bypass xiq 154. Multiplexer One input of the multiplexer 172 will receive the output of XIQ 154. The other input of the multiplexer 172 will receive the input of XI Q 154, namely microinstruction 171 and late〇191. The multiplexer 172 will control the logic 156 according to XIQ The generated control input 161 is selected, and one of the input terminals is selected and output to the execution stage register 176 in the R stage 57. If the execution stage register 176 is ready to receive the instruction, and the XIQ 154 is in the instruction translator 138 When outputting micro-instruction 171 is empty, ， 1 (3 control 1232403

Control logic 156 controls multiplexer 172, bypassing XIQ 154. The microprocessor 100 also includes a valid bit register 189, which can receive an X-valid signal 148 from the XIQ control logic 156 to indicate whether the micro-instructions and related information stored in the register ία during execution are valid. .

[0 0 4 0] The formatting instruction queue 1 8 7 includes an earlier queue 3 2 to store the formatting giant instruction received via the formatted INS TR signal 197, and includes a corresponding later. Column 146 stores relevant information received via X-re 1 -inf 0 signal 1 86. Fig. 1 shows an earlier queue 132, which is composed of three items, represented by αΕΕ2, ee1 & ee0. ee〇 is the bottom item of the earlier queue 132, EE1 is the middle item of the earlier queue 132, and EE2 is the top item of the earlier queue 132. The content of EE〇 will be sent to the output Λ earlyO 193. The signals eshift 164 and eload [2 ·· 0] 162 are used to control the shifting and loading actions of the earlier queue 132. Similarly, Figure 1 also shows a later queue 146 consisting of three items, represented by wLE2, lei, and LEO. LEO is the bottom item of later queue 146, lei is the middle item of later queue J1 46, and le2 is the top item of later queue 1 4β. The content of le〇 will be sent to the output signal lateO 191.

The formatting instruction queue 187 further includes a register 185. At the end of the clock cycle, the register 185 receives the etuft signal 164 from the FIQ control logic 118 and outputs the value of the eshift signal 164 received during the first clock cycle in the lshift signal 168 in the next clock cycle. . The j-instruction queue 187 also includes three registers 183. At the end of the first clock cycle, the register 183 will receive elOad [2: 〇] flood number 'from the FIQ control logic 118 and in the next clock cycle, it will signal 1 l0ad [2: 0]. 142 outputs

1232403 V. Description of the invention (16) The value of the e 1 oad [2: 0] signal 162 received during the first clock cycle. That is, the 'registers 185 and 183 output eshift signals 164 and eload [2 ·· 0] signals delayed by one clock cycle, respectively. [0042] In one embodiment, X-rel_info 186 includes the length of a formatted giant instruction (the corresponding microinstruction is translated from it); an indication of whether the giant instruction crosses a half-cache line boundary; Shift niches; immediate fields for giant instructions; instruction indicators for giant instructions; and various information related to branch prediction and correction (if the giant instruction is predicted as a branch instruction). * [0 0 4 3] In an embodiment, the branch prediction and correction related information includes: branch history table information used to predict whether a branch instruction is taken or not taken; and used to predict whether a branch instruction is taken Part of the linear instruction index for branch instructions that are taken or not taken; branch samples that are used to perform mutual exclusion or operation with linear instruction indicators that are predicted to take / not taken; used to reply if the branch prediction is incorrect The original second branch sample; various flags used to indicate the relevant characteristics of the branch instruction, such as branch instruction ^ is a conditional branch instruction, a call instruction, the target of the return stack, a relative ^ = branch indirect branch, and a branch instruction Whether the prediction of the result is performed by static prediction = to apply; various information related to the prediction made by BTAC 106, such as whether the current address 181 matches the cached address in BTAC 106, whether the matched address is valid, and whether the branch instruction is expected Of the set of BTAC 106 selected or not, selected by the current $ address 181, C has been the least recently routed. If the execution of the instruction needs to update BTAC 106, the selected BTAC 106 will be selected. Which way to replace, and the destination address output by BTAC 106. 5 of positive. In one real

1232403 V. Description of the invention (17)-The X-rel-inf0186 part of the embodiment will be generated during the previous clock cycle and stored for transmission with related information. The EE0 of the earlier queue 132 is generated by the clock cycle after the earl y signal 193 is sent. [0044] Please refer to FIG. 2, which is a block diagram of the earlier queue 1 32 of the formatting instruction queue 1 8 7 of FIG. 1 of the present invention. [0045] The earlier queue 132 includes three multiplexed registers that are serially connected into a queue. The two multiplexing registers include the items gEE2, ee1, and Ε0 in FIG. 1 [0046] The top multiplexing register in the earlier queue 132 includes a multiplexer 212 with two inputs, and a temporary register The register 222 (represented by ER2) is used to receive the output of the multiplexer 212. The multiplexer 212 includes a loading input terminal for receiving the f0rmatted_instr signal 197 in FIG. The multiplexer 212 also includes a holding input terminal for receiving the output of the register ER2 222. The multiplexer 212 receives the eioad [2] signal 162 in FIG. 1 as a control input flood number. If e i0ad [2] 162 is true, the loading input of multiplexer 212 will select formatted-instr signal 197; otherwise, the hold input of multiplexer 21 2 will select the output of register ER2 222. When the rising edge of the clock signal (represented by elk 202) is encountered, the register ER2 222 will load the value output by the multiplexer 212. [0047] The intermediate multiplexer register in the earlier queue 132 includes a multiplexer 211 with an input terminal and a register 221 (represented by ER1) to receive the output of the multiplexer 211. The multiplexer 211 includes a loading input terminal for receiving a formatted instr signal 197. The multiplexer 211 also includes a

1232403 Five 'invention description (18) Hold input, used to receive the output of register ER1 221. The multiplexer 211 further includes a shift input terminal for receiving the output of the register ER2 222. The multiplexer 211 will receive the eioad [丨] signal 162 in FIG. 1 as the control turn Λ. The multiplexer 211 also receives the eshift signal I " in Fig. 1 as another control input signal. If e 1 oad [丨]! 6 2 is true, the loading input of multiplexer 211 will select formatted —instr signal 197; otherwise, if eshift signal 164 is true, the shift input of multiplexer 211 The terminal will select the output of the register ER2 222; in other cases, the hold input of the multiplexer 211 will select the output of the register ER1 221. ^ ^

Shengyuan, temporarily said! 221 will load the multiplexer 211 in the round == [0048] The multiplexer 21 of the bottom multiplexing temporary input in the earlier queue 132, and the register 2 20 (in ERJ) / 、 Use one to receive the output of the multiplexer 210. The multiplexer 21 includes a loading input terminal, and receives the formatted_instr signal 197 with 乂. The multiplexer 21 asks Bai Sheyi to hold the input terminal for receiving temporary signals. The output of the register ER〇22〇. The multiplexer 21 package, a shift input terminal, is used to receive the output of the register ER1 221. The Xiong η device 210 will receive elOad [〇] in Figure 1. The signal 162 is used as the control input signal. The multiplexer 210 will also receive the esMft signal 164 in Figure J as another control input signal. If el〇ad [〇] 162 is true, the load of the multiplexer 0 The input terminal will select the formatted_instr signal 197; if the m signal 164 is true, the shift input terminal of the multiplexer 21 will select the output of ^ 1 and 221; in other cases, the multiplexer's protection is 3: Select the output of the temporary register ER〇22. When it hits the upper and lower of M 2 0, temporary storage 1§ER0 220 will load the value output by the multiplexer 21 0. The temporary storage

1232403 V. Description of the invention (19) The output of the device ER0 220 is transmitted with earlyO signal 193. [0049] Please refer to FIG. 3, which is a block diagram of the present invention / formatted queue 1 87 and later queue 1 46. [0050] The later queue 146 includes three temporary storage devices connected in series. The three temporary multiplexers include the item LE2 in FIG. 1 and the ui worker evening LEO 〇 [0 0 5 1] The top temporary multiplexer in the later queue 146 includes a multiplexer 312 with two inputs. And the register 3 22 (WLR2 comes to the factory to receive the output of the multiplexer 312. The multiplexer 312 includes a 2 =) for the input end, which is used to receive _ ^ 1_11 ^ 〇186 in Figure 1. The multiplexer 312 further includes a holding input terminal 'for receiving the output of the register LR2 322. The multiplexer 312 receives the 1 load [2] signal 142 in FIG. 1 as a control input signal. If lload [2] 142 is true, the load input of multiplexer 312 will take X-rel-info 186; otherwise, the hold input of multiplexer 312 will select the output of register LR2 322. At the rising edge of cik 202 in FIG. 2, the LR2 322 will load the value output by the multiplexer 312. [0052] The intermediate temporary multiplexer in the later queue 146 includes a multiplexer 311 with three inputs, and a temporary register 321 (represented by LR1) / one to receive the output of the multiplexer 311. The multiplexer 311 includes a loading input terminal for receiving X — rel — info 186. The multiplexer 311 also includes a hold-in terminal for receiving the output of the register LR1 321. The multiplexer 311 further includes a shift input terminal for receiving the output of the register LR2 322. The multiplexer 3 will receive the llad [l] signal 142 in FIG. 1 as a control input signal. If lloacUl] signal 142 is true, the load input of multiplexer 311 will select the range

Page 26 1232403 V. Description of the invention (20) X —rel —info 186; Otherwise, if the lshlft signal 168 is the shift input of the true multiplexer 311, the output of the register LR2 322 will be selected. As for the other shape: The input of the holding wheel of the multiplexer 311 selects the output of the register lr; 32 ;. At the rising edge of elk 202 in FIG. 2, the value output by the register LR1 multiplexer 311. 10 halves [0053] The bottom temporary multiplexer in the later queue 146 includes a multiplexer 310 with three inputs, and a temporary register 32 (indicated by LR0). Output. The multi-guard 310 includes a human input terminal for receiving X_rel_inf0 186. The multiplexer 31o also includes a hold input ^ '^ to receive the output of the temporarily stored HLR0 32o. The multiplexer 31o also includes a shift input terminal for receiving the output of the register LR1 321. The multiplexer 3ii receives the signal “lload [0] signal 142 'as the control input signal. If jloacUO] signal 142 is true, the load input of the multiplexer 31 will select —rel —mfo 186; otherwise If the lshift signal 168 is the shift input of the true multiplexer 310, the output of the register LR1 321 will be selected. As for the other, the hold input of the shape multiplexer 310 will select the output of the register LR032. On the rising edge of elk 202 in Figure 2, the temporary storage of sLR () 32 will load the value of multiple ===. The output of the multiplexer 3 10 is transmitted with the signal 1 91. [0 0 5 4 ] Reference is now made to Figure 4, which is a sequence diagram of the formatted finger operation of Figure 1 of the present invention. Figure 4 shows five clock cycles, each time: = period with the rise of clk signal 202 in Figures 2 and 3 Fate is the beginning. Traditionally, the value of | in Figure 4 is expressed as a high logic level. Figure 4 is a form in which when the instruction formatter 丨 6 generates a new formatting giant instruction, the Page 27, 1232403 V. Description of the invention (21) X IQ 1 54 of Fig. 1 is not filled (that is, micro-instructions can be received from the instruction formatter 丨 6) and the instruction is formatted 仵1 8 7 is empty. [0 0 5 5] During the clock cycle 1, the instruction formatter 6 will generate the F-new-instr signal 152 of the true value in FIG. 1 to indicate a valid new The formatting giant command exists in the formated-instr 197 of FIG. 1, as shown in the figure. Because the formatting instruction queue 丨 87 is empty, the f IQ control logic 118 of FIG. 1 will generate a true value of ei. aci [〇] signal 162 to load this valid new formatting giant instruction from formatted-instr 197 to EE0, which is the lowest empty item in the formatting instruction queue 1 8 7. [0 0 5 6] at the time During pulse period 2, v 〇 3 4 (the valid bit of item EE0 of the formatting instruction queue 187) in FIG. 1 is set to indicate that mo contains a valid instruction. At the rising edge of clock period 2, the figure One of the registers 183 will load eload [0] 162 'and output the true value of H0ad [0] 142. Because eload [0] 162 is true, the new instruction will be loaded with aER〇220, and It is output via the ear ly signal 丨 93 of FIG. 1 to be transmitted to the instruction translator 138 of FIG. 1 as shown in the figure. The instruction translator 138 will translate the new giant instruction 'and will translate The microinstruction 171 is sent to XIQ 154. In addition, the control logic 102 will generate new information related to the new instruction in X_rel_info 186, as shown in the figure. Because llad [0] 142 is true, so many The worker 31 will select the loading input terminal, and output the new related information provided by X rel inf〇186 through lateO 191 to send to the XIq 154 and multiplexer 172 of FIG. 1 as shown in the figure. Furthermore, since the instruction translator 138 will translate new instructions during clock cycle 2, the FIQ control logic 118 will generate the true eshift signal 164 'in FIG. 1 so that the instructions will be discontinued during clock cycle 3.

1232403

The formula instruction queue 187 is removed. [0 05 7] During clock cycle 3, since the new instruction has been removed from the grid instruction queue 187, v0 134 is false. At the edge of clock cycle 3, the XIQ control logic 156 will load the relevant instruction messages provided by the translation microinstruction 171 & late〇191 into the execution stage temporarily depending on whether xiQ i 54 is empty or not.器 176 or XIQ 154. In addition, the temporary storage device 185 of FIG. 1 will load the eshift signal 164 and output the true value! shift 168. [0058] It can be observed from FIG. 4 that although the new giant instruction is generated during the clock cycle 1, and the related information is not generated until the clock cycle 2, the formatting command queue 187 is helpful. At the same clock cycle, relevant information and translated micro instructions can be sent to the execution stage. [〇 0 5 9] Please refer to FIG. 5, which is an operation timing chart of the formatting instruction queue 1 87 of FIG. 1 according to the present invention. Fig. 5 is similar to Fig. 4 except that in the case of Fig. 5, when the instruction formatter 11 β generates a new formatting giant instruction, X I Q 1 5 4 is full. [0 0 6 0] In the clock cycle! During the period, XIQ-full 95 was true. The instruction formatter 116 generates a new instruction in formatted_instr 197, and makes F_new_instr 152 true, as shown in the case of FIG. 4. Because the formatting instruction queue 187 is empty, the FIQ control logic 118 will generate a true el0ad [0] signal 1 6 2 to load a valid new formatting giant instruction from formatted-instr 197 into Ε0, such as The situation in Figure 4. [0 0 6 1] During the clock cycle 2, v 〇 1 34 will be set; the register 183 will output the true value ii〇ad [〇] 142; the new instruction will be loaded into ER〇220, And output via ear iy〇 signal 193 to send to the command translator

Page 29 1232403 V. Description of the invention (23) 138; X —re 1—info 186 will generate new information related to the new instruction; and the multiplexer 310 will select the loading input and pass ia ^ e〇igi , Output the new relevant information provided by X — r el — info 186 to be transmitted to XIq 154 and multiplexer 172 ′ as shown in the case of FIG. 4. However, since X I Q 1 5 4 is full at the beginning of the clock cycle 2, the F I Q control logic 1 丨 8 will generate a false value of the eshift signal 164, which is different from FIG. 4. After that, the XIq control logic 156 will deassert XIQ_full 195 to indicate that during clock cycle 3, the instruction translator 138 will be ready to translate the new giant instruction.

[0 0 6 2] During clock cycle 3, since the rising edge of clk 2 0 2, the eshif ΐ signal 164 is false, so the new instruction will be kept in ER 0 2 2 0 and sent via early 0 1 93 The instruction translator 138 performs translation. Correspondingly, V0 134 remains true. The instruction translator 138 translates the new giant instruction and sends the translated microinstruction 171 to the XIQ 154. Because llaod [0] 142 is true at the rising edge of clk 202, during the period of clock cycle 2, the relevant information provided by Xjel-info 186 will be included, LR0 32〇. Because during the remainder of clock cycle 3, u〇ad [〇] H2 & lshift

m is false, so the content of LR0 320 (that is, new information related to the instruction) is sent to XIQ 154 via UteO 191, as shown in the figure. After the clock = period 3 starts, the FIQ control logic 118 will generate a true value of eshift = 4, then during the period of clock period 4, the new # 令 will be formatted from the clock cycle [0063] The 4 instruction queue 1 8 7 is moved out, so v 〇 edge 'XIQ control logic 156 will transfer the period, because the new instruction has changed from formatting 134 to false. At the rise of clock cycle 4, translated by micro-instruction 171 and lateO 191

1232403 5. The relevant instruction information provided by the invention description (24) is loaded into XIQ 154. In addition, the temporary storage of Figure 1 will load the eshift signal 164 and output the true value of ^ 168. [0064] It can be observed from FIG. 5 that although a new giant instruction is generated during the clock cycle 1, and the related information is not generated until the clock cycle 2, the formatting command queue 1 8 7 is helpful. In the same clock cycle, the relevant " k said and the translation micro-instruction can be sent to XIQ 1 5 4.

[0 0 6 5] Please refer to FIG. 6, which is an operation timing chart of the formatting instruction queue 1 87 of FIG. 1 according to the present invention. Figure 6 is similar to Figure 5, except that in the case of ^ 6, when the command formatter 116 generates a new formatting giant command, not only XIQ 1 54 is full, but the formatting command queue 87 is not empty. of.

[0066] During the clock cycle 1, XIQ_FU95 is true. The instruction formatter 116 will generate a new instruction in formatted-instr 197, and make F_new_instr 152 true, as shown in the cases of FIGS. 4 and 5. Because EE0 contains a valid instruction, V0 134 is true; however, because EE1 does not contain a valid instruction, the valid bit (VI 134) of the item ee of the formatted instruction queue 丨 87 in Figure 1 is false, as Shown in Figure 6. Therefore, the FIQ control logic 118 will generate a true value of ei0ad [丨] signal 162 to load a valid newly formatted giant instruction from formatted-instr 197 into EE1. The signal eariy〇193 will send the command held in Ε0 (referred to as the old command in Figure 6), and the signal lateO 191 will send information related to the old command held in LE0 (called the old information), as shown in Figure 6 As shown. [0067] During clock cycle 2, VI 134 is set to show that = eei now contains a valid instruction. U4 also remains set. The old instructions are kept in ER0 220, while the old information is kept in LR0 32〇.

1232403 Invention description (25) The register 183 will output the true value of ii〇a (i [l] 142. The new instruction will be loaded into ER1 221, as shown in Figure 6. The new information related to the new instruction is in X — Rel —info 186 is generated, and the multiplexer 311 of FIG. 3 selects the load input terminal, which is sent to the temporary register LR1 321. Since the XIQ 154 is full at the beginning of the clock cycle 2, the FIQ control Logic 118 will generate a pseudo-valued eshift signal 164. After that, XIQ control logic 156 will disable XIQ-full 195 to indicate that during clock cycle 3, the instruction translator 38 will be ready to translate the new giant instruction .

[00 68] During the clock cycle 3, since the eshift signal 164 is false at the rising edge of clk 202, the new instruction will remain in ER1 221. In addition, the old instructions are kept in ER0 22〇 and sent to instruction translator 138 via early 193 for translation. V1 and "134 remain true. The instruction translator 1 38 will translate the old instructions and send the translated micro instructions 171 to XIQ 154. Because in the remainder of clock cycle 3, n〇ad [〇 \ 142 and lshift 168 is false, so the contents of LR〇32〇 (ie,

The old information related to the old instructions) will be sent to XIQ 154 via late〇 191 as shown in Figure 6. Since iiaOd [〇] 14: is true at the rising edge of elk 202, during the clock period 2, the new relevant information provided by X — rel — info 186 will be loaded into LR1 321. After the clock cycle 3 starts, the control logic 118 generates a true eshift signal 164, so that during the clock cycle 4, the new instruction will be moved from EE1 to EE0. "0069] During the period of clock cycle 4, the new instruction has been shifted from eei to I and short 134 is false. At the rising edge of clock cycle 4, XI < ^ control logic 156 translates microinstructions 171 and UteO 191 translated from the old instruction

Page 32 1232403

The relevant instruction information provided is contained in XIQ 154. In addition, the register i85 will load the eshift signal 164 and output the true value of lshift 168. Because the XIQ 154 is ready to receive another microinstruction, esMft 164 remains true. Since the eshift signal 164 is true at the rising edge of clk 202, the new instruction will be moved from ER1 221 to ER〇 220 and delivered to instruction translator 138 via early 193 for translation. v〇 134 remains true. The instruction translator 1 38 translates the new instruction ’and sends the micro instruction 171 translated from the new instruction to the XIQ 154. Because lshift 168 is true during clock cycle 4, the information related to the new instruction held in LR1 321 will be selected at the shift input of multiplexer 310 and transmitted via * Ute〇 signal 191 ,As shown in Figure 6. [0070] During clock cycle 5, because the new instruction has been removed from the formatted instruction queue 187, the FIQ control logic 118 clears v〇 134. At the rising edge of clock cycle 5, the xiq control logic 156 loads the relevant instruction information provided by the microinstruction 171 and Ute〇191 translated from the new instruction into XIQ 1 5 4 〇 [0 0 7 1] Observation shows that although new giant instructions are generated during clock cycle 1, and the related information is not generated until clock cycle 2, the formatted command sequence 1 8 7 is helpful in the same clock cycle. , So that relevant information and translation microinstructions can be sent to XI q 丨 5 4. [0 0 7 2] Although the present invention and its objects, features, and advantages have been described in detail ', other embodiments may also be included within the scope of the present invention. For example, although the illustrated embodiment 'buffers huge instructions to be sent to an instruction translator to translate into micro instructions', the scope of the invention is not limited to such embodiments;

Page 33 1232403 V. Description of the invention (27) Specifically, the present invention can be widely applied to any situation that requires buffering instructions, and the instruction-related information is generated within one clock cycle after the clock cycle that generates the instruction itself. Furthermore, although the foregoing embodiment is implemented in a microprocessor capable of processing variable-length instructions, the present invention is not limited to this, and may be applied to a processor of fixed-length instructions.

[0 0 7] In addition to using hardware to implement the present invention, the present invention may also be implemented in computer-readable codes (such as electricity month a readable program code) contained in a computer-usable (such as readable) medium, Information, etc.). The computer code makes the disclosed function or architecture (or both) feasible. For example, this can be achieved by using common programming languages (such as C, C ++, JAVA, and similar programming languages); GDSII databases; hardware description languages (hdl) including Verilog HDL, VHDL, Altera HDL (AHDL), etc. ; Or other stylized and / or circuit-recording tools available in this area of technology. The computer code can be placed on any known computer-usable (eg, readable) medium, including semiconductor memory, magnetic disks, optical disks (eg, CD-ROM, DVD-ROM, and the like), and can be used as a computer data signal ' Contained in a computer-usable (if readable) transmission medium (such as a carrier wave or any other medium 'including digital, optical, or analogue media)

in. In this regard, computer code can be transmitted over communication networks, including the Internet and internal networks. It should be understood that the present invention can be implemented in computer code (such as part of a Intellectual Property Right (丨 P) core (such as a microprocessor core), or as a system-level design (such as a system-on-a-chip (S0C))) And can be converted into hardware 'as part of integrated circuit manufacturing. Furthermore, the present invention can also be implemented as a combination of hardware and computer code. ~ Of the above is only a preferred embodiment of the present invention,

1232403

Page 1232403

Brief description of the drawings [Simple description of the drawings] [0 0 2 0] FIG. 1 is a block diagram of the microprocessor of the present invention. [0 02 1] FIG. 2 is an earlier version of the normalized instruction 伫 1 of FIG. 1 of the present invention.

[0 022] FIG. 3 is a block diagram of a later string of the formatting instruction queue of FIG. 1 according to the present invention. [0 0 2 3] FIGS. 4, 5 and 6 are operation timing diagrams of the formatting instruction queue of FIG. 1 according to the present invention. Description of drawing number: 100 microprocessor 102 control logic 104 instruction cache memory 106 branch target address cache memory 108 pre-decoding logic 112 instruction byte buffer 114 instruction byte buffer control logic 116 instruction format Adapter 118 Formatting instruction queue control logic 132 Earlier queue 134 Effective bits 138 Instruction translator 142 11 oad [2: 〇] Signal 146 Late queue

1232403 Schematic description 151 152 153 154 155 156 157 161 162 164 165 167 168 169 171 172 175 176 177 177 179 181 182 183 186 I-Phase signal F_new. F-phase ns tr Translation instruction queue (XIQ) X-phase XIQ control logic R-phase control input e 1 〇ad signal eshift signal instruction byte and pre-decode information instruction byte 1 shift signal pre-decode information micro instruction 178, 210, 211, 212, 310, 311, 312: multiple The worker predicts the branch target address during the execution stage. The register corrects the address. The next sequential fetch address. The current fetch address. The current instruction index signal 185, 220, 221, 222, 320, 321, 322: register signal X — rel. —Inf 〇% Page 37 1232403 Brief description of the drawing 1 8 7: Format command queue 1 88: F_va 1 id signal 1 8 9: Valid bit register 1 9 1: 1 ate 0 signal 193: earlyO signal 194: Branch prediction related information 195: XIQ —ful 1 signal 197: Format instruction 198 ·· signal F_instr_info 1 9 9: FIQ full signal 202: clock signal (elk)

Claims (1)

1232403 -A kind of buffering-lined microprocessor instruction and phase device, wherein the buffering device does not obtain the relevant information until at least two = cycles after obtaining the instruction, the device includes: A queue has a first plurality of items, each to store an instruction; 'the project is a second queue, which has a plurality of items corresponding to the first plurality of items, each item is used to store and the First in the first column: relevant information should be ordered; -f A plurality of control signals coupled to the first queue to load shift and hold the instructions in the first queue; and a plurality of registers to receive the control signals and output a delay of one The control signals of the clock cycle are used to load, shift and hold the relevant information of the piano in the second queue. 'μ 2 · As for the device of the scope of patent application, the instructions stored in the first queue include huge instructions, and the first queue sends the giant instructions to an instruction translator, To translate these giant instructions into micro instructions. 8 7 3. If the device of the scope of patent application No. 2, wherein the giant instructions include χ86 giant instructions. 4. The device according to item 1 of the scope of patent application, wherein the instructions are sent to the first queue by an instruction formatter. 5. The device according to item 4 of the patent application, wherein the instructions include variable-length instructions, and the instruction formatter receives a string of unformatted instruction bytes, and the string of unformatted instruction bits The group is formatted into the variable-length instructions. Page 39 1232403 Patent application scope _ 6 · & Chinese patent application scope 1 f Ρ I / In the microprocessor-buckle ,,,,,, "slow position is coupled to an instruction execution stage ^ cache The device of item 6 of the current range of memory and the microprocessor pipeline, wherein the related information includes the portion of the instruction cache memory that is not included in the microprocessor—the instruction is included in the item 6 Item of the device, in which the second symbol series configuration, will: one of the two received the relevant information with the same clock cycle, and then send it to the implementation stage. N of the eighth patent scope The device, one of the complex items " one of the bottom items includes: j 的 本 肉 © 存 器 肖 to store the first one listed after the same clock cycle—the clock Zhoukun The -plural items =-corresponding = corresponding information of the instruction stored in the item; the related information is received inside, and there is an output-"the input end of the J: f cycle and the execution phase, to the The register, m, according to one or more of the delays when Bi delays the control signal in the In the synchronic cycle, the relevant information is selectively sent to the execution stage. The device of the 8th patent application scope, wherein the second row is% li = a translation instruction associated with the relevant information Is sent to the execution; ant time, in the same clock cycle, the relevant information is phased out. 疋 王成 VAN η. If the device of the patent scope item 10 is requested, the translation instruction is applied from 1232403 VI ' The scope of the patent corresponds to the translation of the instruction stored in the first queue of the relevant information. 12. As for the device of the scope of application for the patent, the translation instruction is obtained by receiving the instruction from the first queue. An instruction translator is used to translate. 9 1 3. The device of item 12 of the patent application scope, wherein the instruction translator receives the instruction from the first queue in the same clock cycle. Item of the device, wherein the relevant information is stored in one of the first queue corresponding to the instruction _ eight = 15. If the device of the scope of patent application for item i, the phase; One of the first queue A length of the instruction. : 1 6 · If the device of claim 1 of the patent scope ', wherein the related information includes branch prediction and information related to a corresponding instruction stored in the first queue, where the corresponding instruction is predicted as — Branch instruction. 17. The device according to item 6 of the patent application, wherein the branch prediction information includes a prediction target address of one of the branch instructions. 1 8 · If the device of the scope of patent application No. 16 ', wherein the branch prediction information includes an instruction to show that the branch instruction is at different clock cycles, whether to cross the two output by an instruction cache memory Group instruction byte. For example, at least a part of the device of the patent application No. 16 of the branch prediction information is obtained from information generated by a branch target address cache memory. 2〇 If the device of the scope of patent application No. 丨 9 ′, wherein the branch target address cache memory includes an N-way set-associative cache memory, the branch page 41 1232403 6. Scope of Patent Application The branch prediction information includes an instruction to point out the least recently used path in one of the branch target address cache memory selection sets. 21. The device according to item 19 of the scope of patent application, wherein the branch target address h fetches δ-memory body including an N-way set-associative cache memory, wherein the branch prediction information includes the branch target address cache memory Which of the N paths will be replaced. 22. The device as claimed in claim 19, wherein the branch prediction information includes information of the branch target address cache memory for correcting an incorrect prediction of one of the branch instructions. 2 3 · If the application includes 2 4 · If the application includes 25. If the application includes 2 6 · If the application specifies 27 · If the application is stored in the 2 8 · If the application is stored in the 2 9 The patent scope supports the patent scope table to predict the patent scope to predict the patent scope branch instruction patent scope first queue patent scope first queue order buffer buffer multiple multiplex number temporary storage of the 16th device information. The device of item 16, wherein the branch predicts a linear instruction index of a neighboring branch instruction. The device of item 16, wherein the branch predicts a branch sample of one of the branch instructions. The device of item 16, wherein the branch predicts a branch instruction type of a neighbor. The device of item 1, wherein the related information includes; a displacement field corresponding to the instruction. The device of item 1, wherein the related information includes an immediate stop corresponding to one of the instructions. ’Includes: a type register, each of which is used to store an instruction; a type multiplexer, each of which is used to store and the plurality of which the branch prediction information Page 42 1232403 VI. Information related to the instruction in the corresponding register of the industrial register of the patent application range; Generate a batch of logic, coupled to these multi-purpose registers, to produce the signal of temporary death 22 ' To selectively load the instruction into one of the multiplexed registers; and a message register i for receiving a value of the control cycle within a first clock cycle, and One of the second clocks after the first clock cycle is temporarily crying out! This value is used to selectively load the temporary multiplexers corresponding to the one of the multiplex #I = I Related information in one of these. The instruction buffer of the 30th item, the profit range item 29, wherein the corresponding one of the temporary f multiplexers is also configured to selectively output the relevant information within the second clock cycle. 1. The instruction buffer of item 30 in the patent scope, wherein one of the multiplexers is configured to rotate the instruction in the second clock cycle. μ 32. For example, the instruction buffer of the 31st scope of the patent application, wherein one of the multiplexed registers is output to an instruction translator during the second clock cycle. A microprocessor comprising: an instruction formatter for issuing a branch instruction in a first clock cycle; a round of control logic for performing a first operation after the first clock cycle During the clock cycle, the ! 232403 6. The scope of the patent application makes the buffer 'coupled to the instruction formatter to buffer the branch instruction during the clock cycle, and: Information' If the instruction buffer is in the -4th condition 'and if The instruction buffer during the first clock cycle ^ message: 'then selectively buffer the data during the second clock cycle 34. If the microprocessor of the scope of the patent application No. 33, but also includes. : ΪΪΪ, lightly connect to the instruction buffer, if the instruction is slow in the clock cycle, receive the d from the instruction buffer: d: The instruction buffer receives the information.帛 -In the clock cycle, from the microprocessor in item 34 of the patent application of Rushen, an instruction translator is coupled to the buffer and buffer during the first clock cycle. If the instruction is within the second clock cycle;; = I then the instruction translator order, and if the instruction buffer buffer receives the branch finger empty; then the instruction translator period: do not receive the branch instruction for the buffer . Within the month 'from the instruction 36. If the microprocessor in the 35th scope of the patent application, the J device is empty during the -clock cycle: 哕 If the instruction is slower than the second clock cycle' will be translated from the instruction In the second line stage, a translation micro-finger is received at the odd stage. Page 44 1232403 The instruction buffer is executed in the received micro-instruction sequence during the execution phase; the judgment sequence with the instruction is moved out; if the phase is shifted out within ， Relevant information 3 8 · If the application is dedicated to the second clock cycle if the shift, then the relevant instruction and phase one second clock cycle 6. Application for patent scope order, and if empty, then the Translator 37. A method for buffering information with a pipeline, including: information related to a first clock period after a first clock period; the instruction on the second and the instruction not from the List the relevant information to load whether the symbol was sent to the profit range with the instruction in the second clock cycle along with the instruction to the 37th item. Whether the instruction is not in the period of the Suining period or not, the instruction is in the second time in the second clock. Zhou ^ News in this Suininglie 39 · — species The order buffer includes: a first multiplexer, including a terminal, a load data input terminal with the first clock # 20%, during the period is not „skillful, will be from one of the instructions of the microprocessor "Load an instruction X into an instruction cycle, and whether to remove it from the frame during the clock cycle generation" is in the first column, and if the instruction has been removed from the frame, bypass the queue and The pipeline. The method further includes: moving out, judging that the instruction is shifted down in the rune; and during the pulse cycle, it is moved down in the third clock cycle that is one after the period in the queue. One output terminal, one holding data wheel is connected in a first clock cycle ^ K 1232403 6. Scope of patent application: The control input terminal receives a first-control signal, which is: right = the value of the control input terminal is true, then the first multiplexer selects the warfare input terminal, otherwise it selects the Hold-in data round-in terminal · Part _: The register 'includes an output terminal that is lightly connected to the output terminal of the first device; Fu Beiyu inputs a second register with an input terminal and a round-out Terminal · One input is more than one: device, which includes the material input terminal connected to the input terminal of the second register, and the output terminal of the second register-j-holding the first _ β-loading-shell material Turn in to receive the information related to the command in the control period after the first clock cycle if-= input terminal to connect to the H control signal terminal, otherwise, the loader will select the load The data input will select the holding data input terminal; and the receiving system 2-input terminal to Lr: within the -clock cycle clock cycle; and an output terminal to select the second system signal at 哕m —control signal, by which, if the id period in the first control period is true; Pulse 4 °. If you apply for special information and the relevant information. The tool also includes the command buffer of the item, in which the second one will be replaced by one, and the fourth temporary storage. ” End to receive a fourth register and the second multiplexer: two uses two to store the data of the item located in the second register, the instruction buffer above the item_, the second The multiplexer includes a second control