TW200414035A - Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor - Google Patents

Abstract

An apparatus for killing an instruction after it has already been loaded into an instruction queue of a microprocessor is disclosed. The apparatus includes control logic that detects a condition in which the instruction must not be executed, such as a branch instruction misprediction; however, the control logic determines the condition too late to prevent the instruction from being loaded into the instruction queue. The control logic generates a kill signal indicating the instruction must not be executed. A kill queue receives the kill signal and stores its value. The kill queue maintains its entries in parallel with the instruction queue entries so that when the instruction queue subsequently outputs the instruction, the kill queue also outputs the value of the kill signal associated with the instruction. If the kill signal value output from the kill queue is true, then the microprocessor invalidates the instruction and does not execute it.

Description

200414035 V. Description of the invention (1). TECHNICAL FIELD OF THE INVENTION The present invention relates to an instruction buffer in a microprocessor, and more particularly to instruction deletion after an instruction is loaded into the instruction buffer. This invention is a related application. This application claims the priority of US Patent Application No. 60/440063. This application was filed on January 14, 2003, and its name is used to delete the branch target address used in the previous pipeline stage. APPARATUS AND METHOD FOR KILLING INSTRUCTIONS DETERMINED INVALID AFTER INSTRUCTION FORMATTING IN A MICROPROCESSOR EMPLOYING A BRANCH TARGET ADDRESS CACHE IN AN EARLY PIPELINE STAGE Prior art modern microprocessors were pipeline microprocessors. They can operate on multiple instructions simultaneously in different modules or pipeline stages of a microprocessor. He η nessy and Pa11 ers ο n in their co-author define pipeline technology as "implementation technology of multiple instructions overlapping execution (computer structure: quantification method)", second edition, John L. Hennessy, David A Co-authored by Patterson, Morgan Kauf mann Press, San Francisco, CA, 196. They also provide an excellent image explanation of pipeline technology as follows: A pipeline is like a pipeline. On the pipeline of automobile production, there are Many stages, each stage assembles a component for the car. Each stage runs in parallel with the other stages, but each assembles a different car. Within a computer pipeline, each step completes a part of the instruction. Like a pipeline,

12829twf.ptd Page 9 200414035 V. Description of the Invention (2). Different steps complete different parts of different instructions in parallel at the same time. Each such step is called a pipeline stage, or pipeline segment. All stages are connected together to form a complete pipeline. The instructions enter from one end, pass through each stage in the pipeline, and finally output at the other end, just like cars on the assembly line. The synchronous microprocessor operates on a clock cycle. Generally, in one clock cycle, instructions proceed from the pipeline stage of a microprocessor to the next. On the automobile assembly line, if there are workers at the stage who do not have cars to operate, then the production efficiency of the entire assembly line will be reduced. Similarly, if a microprocessor stage is idled because there are no instructions to operate in a clock cycle (a phenomenon commonly referred to as a pipeline bubble), the microprocessor's computing efficiency will also decrease. A commonly used method to avoid pipeline bubbles is to use instruction buffers between different stages of the pipeline. The common structure is a queue structure. An instruction buffer provides a buffer space when the processing speed of the pipeline stages before and after it is different. For example, when the pipeline execution stage (such as the low-end) requires instructions to operate and there are no instructions in the high-end cache memory of the pipeline, the instruction buffer can play its role. In this case, while the memory is being read, the instruction buffer can provide instructions for the execution phase, thus reducing the impact of missing cached memory instructions. Another possible cause of pipeline bubbles is branch instructions. When the processor receives a branch instruction, it must determine the target address of the branch instruction and obtain the instruction from the target address, not from the next sequential address after the branch instruction. In addition, if this branch instruction is a conditional branch instruction (such as whether to decide whether to execute this branch instruction based on the existence of a certain condition),

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V. Description of the invention (3). In addition to determining the address of the eyepiece, the processor must also determine that this point is executed. Because the pipeline stage that determines the target address and / or decides whether the instruction will be supported or not, the execution and execution of branch instructions can be generated after the pipeline stage that gets the instruction. Instruction buffering with pipeline bubbles can indeed reduce pipeline bubbles. Generally, branch prediction mechanisms are used to advance the box. But whether modern instructions or branch instructions will be executed to further reduce this, address and / or branch Prediction is wrong, no matter what the surprise is. However, this sequence instruction or target address instruction should not be executed ^ 9々 as the next sequential error. ’Otherwise, the incorrect branch instruction prediction will be corrected, which is an example where the instruction of the device must be deleted, that is, the wrong branch instruction is processed microscopically. However, the actual situation may be: ^ official line to execute into the instruction buffer before determining that it must be deleted. ^ Instructions have been written to achieve the instructions written in the instruction memory, and there is an urgent need for an invention. One clock cycle is loaded into the microprocessor instruction queue and one instruction is output at the bottom of the queue at two. It includes: one clock cycle passes the third clock week number after the first clock cycle, which is used to prescribe a delete queue, and is used in conjunction with a delete signal to plant a value of 22f; Delete the signal value, and the next clock i ^ ^ the third clock a validity signal generated in the = clock cycle ^ This value is used for δ brother to indicate whether this instruction needs to be micro-unified u ': Divide 2 columns of Heyi execution. If you delete j

200414035 V. Description of the invention (4) • · ·-. · The delete signal output in the second clock cycle is true, then the validity signal value is false. In another aspect, the invention provides a method for deleting instructions in a microprocessor. It includes: loading instructions into the first queue in the first clock cycle, generating a delete signal in the next clock cycle and loading the value of this delete signal into another queue; in the third clock cycle Output this instruction from the bottom of the first queue and determine whether the signal value in the second queue is true. If this value is true, execute this instruction. In another aspect, the present invention provides a microprocessor. It includes: the first queue is used to receive instructions for instruction buffering; a logic is used in conjunction with the first queue to find that the instruction cannot be executed by the microprocessor, and this logic generates a signal that is true to explain In this case, this signal is generated after the instruction is received by the first queue; the second queue is used in conjunction with logic to load the truth signal and output the signal at the same time as the output instruction in the first queue. The microprocessor responds to this truth signal and invalidates the corresponding instruction. In another aspect, the present invention provides computer data contained in a transmission medium. The computer data f includes computer-readable code, which enables a device to implement instructions for loading a microprocessor in a first clock cycle. The queue deletes the instruction output from the bottom of the queue in the next clock cycle. The code includes: a first piece of code for generating a delete signal and transmitting a signal value generated by a third clock cycle; a second piece of code for generating a delete queue, which is used in conjunction with a delete signal to load a third The erasure signal generated in the clock cycle, and the value of this erasure signal is output in the second clock cycle; the third piece of code is used to generate a validity signal and is used in conjunction with the erasure queue.

12829twf.ptd Page 12 200414035 V. Description of the invention (5) Second: "cycle generation" and used to explain whether the instruction will be registered J ^ th = delete the display output in the first clock cycle " True, this validity signal value will be false. An advantage of the present invention is that it makes it possible to use instructions Ϊ: Ϊ: Ϊ Ϊ in the microprocessor pipeline that requires the instruction delete function in the second pass ^ Ϊ Ϊ Ϊ 仃. Another advantage is that the present invention enables the deletion of a signal sequence to be generated later without the need for additional pipeline stages to store instructions. ^ This makes the above and other objects, features, and advantages of the present invention clearer. The preferred embodiment, combined with the attached drawings, is described in detail and the details are as follows: Mode ^ Yiyuan 1 is a schematic structural diagram of a microprocessor 100 in the present invention. Microprocessor 1 0 0 疋 A pipeline with multiple pipeline stages f shows some of the stages, including an instruction stage (two "51 'graph-an extraction stage (F-stage) 1 5 3, a translation stage (Χ — stage) 155 and a temporary stage (R-Stage) 157. Stage 151 includes a stage to fetch instruction bytes from memory or cache memory. In one example, I-stage 151 includes Multiple stages. F — Stage 153 includes a stage to format an unformatted instruction byte. Ystage 155 includes a macro instruction to R ~ stage 157 includes a cry from temporary storage # # λ 、 史 — Yu Gan from D. 1 7 stored as a slot to load the temporary step slaves of the operands. Other R-stage 157 microprocessing such as address generation, storage, and result write back cry Λ n from the cylinder shell leaves & search for 1 0 0 execution phase is not in Figure i

12829twf.ptd 200414035 V. Description of Invention (6) List. The microprocessor 100 includes an instruction cache memory 104 in the I-stage 151. The instruction cache memory 104 buffers instructions obtained from the system memory used in conjunction with the microprocessor 100. The instruction cache memory 104 receives a currently selected address 181, and selects and outputs an instruction byte 167 with a capacity of one cache line. In one example, the '4 command cache 5 self-memory body 104 is a multi-stage cache memory situation, that is, the instruction cache memory 104 requires multiple clock cycles to correspond to the currently selected bit. Address and output a cache line. " Microprocessor 100 also includes a multiplexer 178 in I-stage 151. The multiplexer 178 provides the currently selected address 181. The multiplexer 178 ^ receives the next target address 179. This address is obtained by adding the current target address 丨 8 i to the instruction cache memory 1 0 4 and outputting the cache line size. The multiplexer 178 will also receive a correction address 177, which explicitly refers to an address for the microprocessor 100 to correct the incorrect branch prediction. The worker 1 7 8 also receives a predicted branch target address 丨 7 5. ° The microprocessor 100 also includes an address cache memory BTAC 1 06 in I-Stage 151 'This cache memory is coupled to 178 »BTAC 106 responds to the current target address 181 and generates-test branch target address 175 〇BTAC i 06 buffer stores the executed branch target address and branch instruction address. In one example, btaci06 includes a 4-way combination cache memory 'and the selected combination contains multiple items for storing the target address and the branch prediction education of the predicted branch instruction. Except the predicted branch target address 丨 7 5, bt AC 丨 〇 6

12829twf.ptd 200414035 V. Description of the invention (7) It also outputs branch prediction related information 1 9 4. In one example, the BTAC information 1 9 4 includes: an offset bit indicating the first byte of the predicted branch instruction of the currently selected address 丨 8 1 selected cache line; an information indicating whether the predicted branch instruction is Cross half of the cache line; one valid bit for each item in the selected item; a message indicating which of the selected combinations is the least recently used road; a message indicating which of the selected roads is the most recent The least used items; and the prediction of whether a branch instruction will be executed. The microprocessor 100 also includes control logic 102. If the current target address 181 matches the valid cache address of an executed branch instruction in BTAC 106, and BTAC 1 0 6 predicts that this branch instruction will be executed, then the control logic 1 02 controls the multiplexer 1 78 to select BTAC destination address 1 75. If an incorrect branch prediction occurs, the control logic 102 controls the multiplexer 17 8 to select the correction address 17 7. Otherwise, the control logic 102 will control the multiplexer 178 to select the next target address 179. Control logic 1 0 2 also accepts BTAC information 1 94 〇 'Microprocessor 10 0 also includes pre-decoding logic 1 in its stage 151 〇 8' This pre-decoding logic 丨 〇8 and instruction cache memory 丨〇4A combined. The pre-decoding logic 1 08 receives the instruction cache memory 1 4 and the instruction line 1 67 of the cache line and the BTAC information 1 94, and generates pre-decoding information 1 6 9 accordingly. In one example, the pre-decoding information 6 9 includes: a bit associated with each instruction byte, which is used to predict whether the byte is a branch instruction predicted to be executed by BTAC 1 06 Operation code; predict multiple bits of the next instruction length based on the predicted instruction length; and each instruction bit

12829twf.ptd Page 15 200414035 V. Description of the invention (8) • * · Department-· A bit related to the tuple. This bit is used to predict whether this byte is the first byte of the instruction; and branch Prediction of instruction output results. The microprocessor 100 also includes an instruction byte buffer 1 12 in its F-Stage 153. This buffer 1 12 is used in combination with the pre-decoding logic 108. The instruction byte buffer 1 1 2 receives pre-decoding information 1 6 9 from the pre-decoding logic 1 08, and receives the instruction byte 1 67 from the instruction cache memory 104. The instruction byte buffer 1 12 provides pre-decoding information to the control logic 102 via a signal 196. In one example, the instruction byte buffer 1 12 can buffer the instruction bytes and related pre-decoding information of the four cache lines. The microprocessor 100 also includes an instruction byte buffer control logic 1 1 4 which is used in conjunction with the instruction byte buffer 1 12. Instruction Byte Buffer Control Logic 1 1 4 Controls the input and output instruction byte buffers and the instruction byte and related pre-decoding information flow. The instruction byte buffer control logic 1 1 4 also receives B T A C information 1 9 4 at the same time. The microprocessor 100 also includes an instruction formatter 1 1 6 in its F-stage 153, which is used in conjunction with the instruction byte buffer 1 1 2. Instruction Formatter} J 6 receives the instruction byte buffer from the instruction byte buffer, and receives the instruction byte and pre-decode information 1 6 5 at the device 1 12 and generates the formatted instruction 1 9 7 from it. That is, the instruction formatter ii 6 consults a string of instruction bytes from the instruction byte buffer 1 1 2 to determine which bytes contain the next instruction and the instruction length, and uses the next instruction as a formatted Command 1 9 7 is output. In the example shown in FIG. 1, the instruction formatter 1 16 includes a combination logic. This logic refers to the instruction byte 165 provided by the instruction byte buffer 112 and outputs the formatted instruction in the same clock cycle. 1 9 7. In one example, the formatted instructions

12829twf.ptd Page 16 200414035 V. Description of the Invention (9) The formatted instructions provided include instructions that fully comply with the X 8 6 structure instruction combination. In one example, the 'formatted instructions' are also called micro-instructions which are converted from giant instructions and executed by the microprocessor's 1000 pipeline execution stage. The formatted command 197 is generated in the F-Stage 153. Each time the command formatter 1 1 6 outputs a formatted command 1 9 7, the command formatter 116 generates a value of F — new — instr 152 to indicate that the formatted command 1 9 7 contains a valid format Following instructions. In addition, the instruction formatter 116 outputs related information of the formatted instruction 197 through a signal F_instr_info 198, and provides this signal to the control logic 102. In one example, the signal F_instr_inf 1 9 8 includes: a prediction information (if the instruction is a branch instruction), the prediction information indicates whether the branch instruction is executed; the prefix of an instruction; the address of the instruction Whether to hit the microprocessor's branch address buffer memory; whether this instruction is a far direct branch instruction; whether this instruction is a far indirect branch instruction •, whether This instruction is a call branch instruction; whether] Jt instruction is a return branch instruction; whether this instruction is a long return branch instruction (far return branch instruction); whether this instruction is An unconditional branch instruction; and whether or not! The ^ instruction is an i conditional branch instruction. In addition, the instruction formatter 1 1 6 outputs the formatted instruction address through the current instruction index c I P signal 1 8 2. This address is equal to the address of the previous instruction plus the length of the previous instruction.

12829twf.ptd Page 17 200414035 V. Description of Invention (ίο) •.... Of microprocessor 100 also includes a formatted instruction queue FIQ 1 8 7 in its X-stage 155 . The formatted instruction queue 1 8 7 receives the formatted instruction 1 9 7 from the instruction formatter 1 1 6. The formatted instruction queue 1 8 7 also outputs the formatted instruction through an early signal (early 0) 193. In addition, the formatted instruction 彳 列 1 8 7 receives information about the formatted instruction obtained by the formatted instruction 197 from the control logic 1 02 through a signal X_r e 1 _ i n f ο 1 8 6. X —re l_info 186 is generated in X-stage 155. The formatted instruction queue 187 also outputs information about the formatted instruction through the e a r 1 y 0 signal 1 9 1 through the 1 a t e 0 signal 1 9 1. The formatted instruction queue 187 and X_rel_info 1 8 6 will be explained in detail below. The microprocessor 1 0 0 also includes the formatted instruction queue FIQ control logic 118 ° FIQ control logic 118 receives a signal F from the instruction formatter 116 new_instr 152 ° FIQ control logic 118 generates a true value signal FIQ — fu 1 1 1 9 9 and when the formatted instruction queue 1 8 7 is full, send this signal to the instruction formatter 1 1 6. The F I Q control logic 1 1 8 also generates a 0 s h i f t ia 16 4 ′, which is used to control the rotation of the formatted instruction Y 1 7 7. The FIQ control logic 118 also generates a plurality of ei0ad signals 162, which are used to control the loading of 187 items from the formatted instruction 197 to the empty formatted instruction queue. In one example, the F I Q control logic 1 1 8 generates an e 1 0 a d signal 16 2 for each item of the formatted instruction 彳 1 8 7. In one example, the formatted instruction queue 1 8 7 includes 12 items, and each item stores a formatted macro instruction. However, in order to make the illustration clear and concise, the formatted instructions in Figs.

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3 items are shown; therefore Fig. 1 shows 3 e 1 o a d signals 16 2 which can be labeled A e 1 o a d [2: 0]. The lower F I Q control logic 1 1 8 also holds a valid bit 1 3 4 for each item of the formatted instruction 彳 1 8 7. The example shown in Figure 1 contains three valid bits, which are labeled F V 2, F V 1, and F V 0, respectively. FV 0 1 3 4 corresponds to the formatted instruction queue 1 8 7 lowest end item; FV 1 1 3 4 corresponds to the style / dagger instruction queue 1 8 7 middle item; and ρ V 2 1 3 4 corresponds to the formatted command queue 1 8 7 highest-end items. The f I Q control logic 1 1 8 also outputs a k number F — v a 1 i d 1 8 8. In one example, this signal is ρ v 〇 1 34. The valid bits 1 3 4 indicate whether the formatted instruction queue 丨 8 7 contains a valid instruction. The F I Q control logic 1 1 8 also receives a XIQ —ful 1 signal 195. The microprocessor 100 also includes an instruction translator 1 3 8 'in its X-Stage 155 for use with the formatted instruction queue 8 8. The instruction translator 1 3 8 receives a formatted instruction from the formatted instruction queue 187 through an early signal 193, and translates the formatted macro instruction into one or more micro instructions 4 7 1. In one example, the microprocessor includes a 1-instruction-set computer (R-sc) core to execute the original or simplified instruction set. In the example shown in FIG. I, the instruction translator 丨 38 includes $ logic to receive the formatted macro instruction through ㈡ ^ 193 and output the translated micro instruction in the same clock cycle. 7 1. That is, regardless of whether the input of the instruction translator 138 contains a valid macro instruction, it will translate its input information at every clock cycle. The processing line 100 also includes a translated version in its X-Stage 155

200414035 V. Description of the invention (12) The instruction queue XIQ 154 is used together with the instruction translator 138. XI Q 154. Buffering Micro-instructions received by instruction translator 138. X I Q 1 5 4 also buffers the relevant information received by the formatted instruction queue 1 8 7 through 1 a t e 0 signal 1 9 1. This information is related to the formatted macro instruction before microinstruction 17.1 translation, and therefore also to microinstruction 17.1. This related information is used by the execution stage of the microprocessor 100 to execute the relevant microinstruction 171. In one example, X I Q 1 5 4 includes 4 items, while in other examples, X I Q 1 5 4 includes 6 or 8 items, respectively. However, for simplicity and clarity, X I Q 1 54 shown in Figure 1 contains only three items. Microprocessor 100 also includes XIQ control logic 156, which is used in conjunction with XIQ 154. The XIQ control logic 156 receives the F_val id signal 188 and generates a XIQ_ful 1 signal 195. The XIQ control logic 156 also generates an X_load signal 164 to control the translated micro-instruction 1 71 and related information to be loaded into X I Q 1 5 4. X I Q control logic 1 56 also generates X-shi ft signal 1 1 1 to control the downward movement of microinstructions in XIQ 154. The XIQ control logic 156 also holds a valid bit 1 4 9 for each input of the XIQ 154. The example shown in FIG. 1 includes three significant bits, which are labeled X V 2, X V 1 and X V 0, respectively. X V 0 1 4 9 corresponds to the effective bits of the low-end items of X I Q 1 5 4; XVI 149 corresponds to the effective bits of the middle-end items of XIQ 154; XV2 149 corresponds to the effective bits of the high-end items of XIQ 154. The XIQ control logic 1 5 6 also outputs an X 1 v a 1 i d signal 1 4 8. In one example, this signal is X V 0 1 4 9. The valid bit 1 4 9 indicates whether the corresponding item in an X I Q 1 5 4 contains a valid translated micro instruction. The microprocessor 100 also includes a 2-input multiplexer 172 in its X-Stagel 55, which is coupled to the XIQ 154. Multiplexer 172 as an option

I2829twf.ptd Page 20 200414035 V. Description of the invention (13) The bypass multiplexer of XIQ 154 is bypassed. The multiplexer 172 receives the output of the XIQ 154 at one input end and the input signal of the xiq 154 at the other end, such as microinstruction 171 and lateO 191. The multiplexer 172 selects an input it accepts under the control of a control signal 16 1 input generated by the XIQ control logic 1 56, and outputs it to the ㈣M register 1 7 in R-stagel57. If the state of the execution stage register 丨 7 6 can receive an instruction, and when the instruction translator 138 outputs a micro instruction 171 乂 "154 is empty, then the pneumatic device 1 2 is under the control of XIQ control logic 1 5 6 XIQ 1 5 4. The microprocessor 1 0 0 also includes a valid bit register R ν 丨 8 9, this register 丨 8 g receives the X-Valid signal 148 from the XIQ control logic 156 and uses this Indicate whether the microinstructions and related information stored in the execution stage register 76 are valid. Formatted instruction queue 1 87 includes: early queue 1 32, = ^ format received via formatted instruction signal 97 The transformed macro is said to be 々; a corresponding late queue 146 is used to store the relevant information received through the “X-rel_lnf0 signal 186. U2 includes 3 projects, which are marked as EE2, EE1⑴: Early ^ 2 2 巧 Qiao Er low-end projects; Ε1 is the early-term Tsai &32; the middle-end item is ^ Ε2 is the early high-end project 132. The first member of Ε〇 output signal earlyO 193. The signal eshift 164 k is used to control the conversion and loading of the early stage 132: class ^ 4 ^ 10 /; 1 2: 0] 162 stage, "6 includes 3 items, each marked as 2 shown in Figure 1 : Late LEO is the low-end project of late queue 146; Lu is ^ '^ E0. End project; LE2 is the high-end project of late queue 146. The output of late 146 is used as the output signal late〇191.

200414035 V. Description of the invention (14) Formatted instruction queue 1 7 ·. Device 185 is a register at the end of the first clock cycle85. Temporarily store the eshift signal 164 and receive the number 168 at the bottom-Q control logic 1 1 8 to output the first clock cycle period. The instruction queue is formatted by a 1 shift letter i 8 7 and also includes the 1 ft signal 1 6 The value of 4. Control logic from FiQ at the end of the first clock cycle. Register 183 signal 1 62, and receive el〇ad [2: 0] 142 at the next 3 rr ### 18 to output the first-time wealth @f 1 through a H〇ad [2: 0] signal value. That is to say, the eloadr2 of the el0ad [2: 0] signal 162 that was received during the temporary crying period, Π 1 ^ 5 and 1 8 3 / do not send the e sh ift signal j 6 4 and el〇ad [2 ″ 0] $ 162 delays one clock cycle output. Answer: In the example, X — rel — inf 〇186 includes: the length of the macro instruction used to translate into pairs of two and two; one for this macro refers to ^ 疋 + JI, a cache line A description of the storage instruction of this macro instruction #: a current position of the 3 instruction; the instruction instruction of this macro instruction ^ λ * miscellaneous, a 丨 macro instruction is predicted to be a branch instruction with various phases i! :: Information, this information is a correction for branch prediction. Tian * cat: In the case of the eighth example, the information related to branch prediction and correction includes: Prediction of the branch history table information whether the i instruction will be executed; whether it will be executed if Li 7 The P knife of the linear instruction index of the branch instruction is used to calculate with the aforementioned sexual instruction or logic, whether the related branch instruction will be executed in the two branch style; in the case of eight * two two, it is used to backtrack the second Branch styles; various flag bits that explain the characteristics of the 11th, such as whether the branch instruction is a conditional branch, a call instruction, a target that returns a heap of worries, 12829twf.ptd page 22 200414035

V. Description of the invention (15) Branch, an indirect branch, and whether the prediction of the branch instruction result is made by the 1 predictor; various information related to the prediction made by the BTAC 1 0 6 such as 1 ^ whether the selected address 181 corresponds to a BTAC Internal address of 106, whether this is valid § W address, whether the branch instruction is predicted to be executed or not executed, is: ^ The most recently used item of the BTAC 106 combination selected by the target address 181, if the execution of the instruction requires BTAC 1 06 To update, which item of the selected group '^ " should be replaced, that is, the destination address output by BTAC 106. In a real second, a part of X_rel_inf〇186 was produced 1 in the previous clock cycle, and the item in this macro instruction was listed by the early Suining 1 2 2 £ e 〇 通 尚 ear 1 y 0 k number 1 9 3 provides the relevant β from the next clock cycle as input. Weixin ~ The microprocessor 1 00 also includes a delete ^ 1 4 5 in its X-stage 1 55, which is coupled to the F I Q control logic 1 1 8. The delete queue 1 4 5 stores a delete signal generated by the control logic 1 0 2 丨 4 1. The control logic 1 〇 2 generates a delete signal 1 4 1 with a value of true to explain the early queue 1 3 2 and the formatted command signal received in the previous curing period. 1 cannot be executed by microprocessor 1 0. The delete queue 4 5 contains the same number of items as the formatted 7 command queue 1 8 7. Fig. 1 shows that three items of the delete queue are labeled κ e 2, K E 1 and K E 0, respectively, and correspond to the 187 items of the command queue after the formalization shown in Fig. 1. KE0 is the bottom entry of the deleted queue, K E 1 is the middle entry of the deleted queue, and κ E 2 is the top entry of the deleted queue. As shown in Figures 4, 5, and 6, the content of KE0 is provided by the output signal k i 1 1 0 1 4 3. Deletion queue 丨 4 5 Receive 丨 oad [2: 〇] signal 丨 4 1 s h i f t 仏 No. 1 6 8 and e s h i f t signal 1 6 4 are used to control deletion of queue 1 4 5

12829twf.ptd Page 23 200414035 V. Description of the invention (16) • · * · · · · Loading and conversion. Deletion queues will be further explained in the following explanation of Figures 4, 5, and 6. The control logic 102 generates a truth signal based on different conditions found from the BTAC information 194, predecode_info 196, F_instr_info 198, and the current instruction index 182. One situation is the detection of a B TA C 106 incorrectly predicting a branch instruction. In one example, B T A C 1 0 6 incorrectly predicts the branch instruction because the predicted instruction length is different from the length confirmed by the instruction formatter 1 16. In one example, BTAC 1 06 incorrectly predicts a branch instruction due to incorrect prediction of a common instruction as a branch instruction. For example, BTAC 1 0 6 predicts an instruction as a branch instruction, and the instruction formatter 1 1 6 confirms its non-branch instruction. . In one example, BTAC 106 is mispredicting a branch instruction due to incorrectly predicting the address of a branch instruction, such as the predicted instruction offset bit output by BTAC 106 and the BTAC 106 used to make this prediction. The sum of the selected address 181 is not equal to the instruction address 1 8 2 generated by the instruction formatter 1 1 6. In one example, when BTAC 106 is making predictions, the mispredicted instructions and subsequent instructions must be deleted; therefore, the control logic 10 generates a delete signal with a value of true for each instruction that needs to be deleted. 1 4 1. The control logic 1 2 generates a delete signal 1 4 1 one clock cycle after the instruction is supplied to the instruction formatter 1 1 6. In addition, the control logic 102 provides information through a void signal 1 4 7 to invalidate the items of b τ A C 1 0 6 which generate a wrong prediction. When the control logic 1 〇 2 invalidates the mispredicted β τ AC 1 0 6 item, the control logic 102 controls the multiplexer 178 to select the correction address 177 so as to reacquire the incorrectly predicted instruction and its subsequent instructions. correct

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Page 24 200414035 i.. Fengmingmaming (17):. *-· · · ··· ** _ · · · • The original wrong prediction. Because the wrongly predicted item in BTAC 106 is invalid at this time, BTAC 1 0 6 will no longer predict the last mispredicted instruction as the executed branch instruction; therefore, it will be regardless of whether this instruction is a branch instruction or not. It will be formatted by the instruction formatter 116, translated by the instruction translator 138, and executed by the execution stage of the microprocessor pipeline 100. Another case in which the control logic 102 generates a true delete signal 丨 41 is that the control logic 102 causes the microprocessor 100 to use a prediction that one of the branch instructions made by btac 106 will be executed. And one target bit is generated. In this case, any subsequent instruction of the branch instruction fetched from the instruction cache memory and transmitted to the instruction byte buffer, 12 must be equal to T. Therefore, the control logic 102 needs to be The deleted instruction S; the value "deletion signal 141. The control logic 102 generates this deletion signal " I at a clock cycle where the instruction is provided to the finger ii. One is a two-boolean -1 ^ 106 to predict the two instructions The first instruction in the. And the support instruction 'control logic 1 02 will delete the second. Figure 2 shows the early queue of column 187 according to the present invention. Formatted instruction selection-temporary storage Device, a νΓνΛ diagram. Early ^^ column. These 3 choices = ΓΛΓ are connected in order to form-仔 Ε0. The temporary storage family includes the items Ε2, Ε1, and the selection at the top of the m-column shown in Figure 1-temporary storage. The device includes a multiplex with 2 inputs of 21 2 and a temporary storage of 2. The incoming state is marked as ER2, which is used to connect

200414035 Ear and Mengming instructions (is) receive the output of multiplexer 212. The multiplexer 212 includes a load data input terminal for receiving the formatted command signal 197 shown in FIG. 1. The multiplexer 212 includes a clever data input terminal for receiving the output of the register ER2 222. The multiplexer 212 receives the elOad [2] signal 162 shown in the figure as a control input. If eload [2] 162 is true, the multiplexer 212 will select the formatted command signal on the input terminal of the load 丨 9 7; otherwise, the multiplexer 2 丨 2 will select the temporary storage on the data input terminal. ER2 2 2 2 output. Temporary ER 2 2 2 2 on a clock cycle (clk) 202; 21 2 output. In the middle of the early queue 132, the register-register includes a 3-input multiplexer 211 and a register 221. This register is labeled ER1 and is used to receive the output of the multiplexer 2 1 1. The multiplexer 2 includes a load data input terminal for receiving the formatted command signal 97. The multiplexer 2 also includes an input terminal, which is used to receive the output of the register E R 1 2 2 1. The multiplex 2 1 1 also includes a conversion data input terminal for receiving the output of the register er2 2 2 2. The multiplexer 211 receives the elOad [1] signal 162 as shown in the figure as a control input. The evening machine 2 1 1 also receives the e s h i f ^ signal 1 β 4 shown in FIG. 1 as the ^ system #. If e 1 〇ad [1] 1 6 2 is true, and the multiplexer 2 1 1 selects negative, the formatted command signal on the lean input terminal 丨 9 7; if eshift signal ^ 64 is true, the multiplexer 211 Select the register ER2 on the input side of the conversion data. Output; otherwise, the multiplexer 2 1 2 selects the output of the temporary storage state ER1 221 on the data input terminal. The register ER1 221 is loaded into the output of the multiplexer 211 at a rising edge of the clock period elk 202. ’Early selection at the bottom of 132-the register includes a 3-input multi-

200414035 V. Description of the invention (19) • · · · *. · ♦. ·.. · · Worker 210 and a register 2 2 0, this register is marked as ER0 and used to receive the multiplexer 210 Output. The multiplexer 21 includes a load data input terminal for receiving the formatted command signal 197. The multiplexer 2 10 also includes a holding data input terminal for receiving the output of the register ER 220. The multiplexer 2 10 also includes a conversion data input terminal for receiving the output of the register E R 221. The multiplexer 210 receives the ei0ad [〇] signal 162 shown in FIG. 1 as a control input. The multiplexer 2 1 0 also receives the e s h i f t signal 1 6 4 shown in FIG. 1 as a control signal. If e 1 0 ad [0] 1 6 2 is true, the multiplexer 2 1 〇 selects the formatted command signal on the load input terminal 丨 9 7; if esh 丨 ft = No. 1 6 4 is true , The multiplexer 2 丨 〇 selects the output of the register ER 1 2 2 1 on the input side of the conversion data; otherwise, the multiplexer 2 丨 2 selects the register ER〇22 on the hold data input end. Output. The register heart 〇 220 at a time pi η week Γ / γ / on the rising edge of 002 carries the output of the multi-body 210. The register ER 0 2 2 0 outputs the result as an early signal 193. ^ Shows a schematic structural diagram of a temporarily-formatted, long-term queue 146 according to the formatted instruction shown in FIG. 1 according to the present invention. Late queuing 146 includes 3 rf heart; multiple organs are connected in sequence to form a ㈣ LE (). Zai Xi workers include the temporary storage of items LE2, LE1, and worker LW column / j6 top, which are not shown in Figure 1. The multiplexer includes a 2-input multi-receiving ^ work register 322. This register is labeled ^ 2, used to receive the rotation of 312. The multiplexer 312 packet is received at the input terminal, and is used to receive the 1-well -γ f < input of a load, and the input of a hold-up signal. The multiplexer 312 also includes input terminals 广 and 广, for receiving the output of the register LR2 322.

Page 27 200414035 V. The invention says (20) The multiplexer 312 receives the lload [2] signal 142 as a control input. If lload [2] 142 is true, multiplexer 312 selects X_ref_info 186 on the input of load data; otherwise, multiplexer 312 selects the output of register LR2 322 on the hold data side. Register! ^ 2 322 is loaded into the output of multiplexer 312 at the rising edge of the illustrated clock cycle elk 202. The register of the middle stage of the late queue 146 includes a 3-input. The register 31 1 and a register 321 are marked as LR1 and are used to receive the output of the multiplexer 311. The multiplexer 311 includes a load data terminal 'for receiving 乂 — 1 ^ _11 ^ 〇186 shown in FIG. Multi-tool 3 11 ^ spoon A holding data input terminal, used to receive the output of the register LR1 321. The multiplexer 311 also includes a conversion data input terminal to write the output of the LR2 322.吝 工 立 必〗 〖Aberdeen for Be Private X /. Xi Gong for 311 receives the U〇ad [l] signal 142 as a control: Ϊί]. / "Industrial / 3U also receives 1SMft signal 168 as the control input. If the value is true, the multi-guard 311 selects the load data to input hrTe; lnf0 I86; if the value of 1shift 168 is true, the output of the second material is more; otherwise The worker 311 selects ten temporary storage on the input data. The output of the register LR1 321. The register lri 321 shows the value in the figure. The rising edge of the clock cycle clk 202 is loaded into the output of the multiplexer 311. A multiplexer at the bottom includes a three-input multi-receiver = 2: 1 register 3 2 0? The dagger register is marked as LR0, which is used for termination, and k is used to connect to this and the network output. Multi The worker 31 〇 includes a load data input ^ X " \ f-ln ^ 186 ° input terminal, which is used to receive the output of the register LR () 32〇.

12829twf.ptd

Page 28 200414035 V. Description of the Invention (21) '· · · · · · ... The multiplexer 310 also includes a conversion data input terminal for receiving the output of the temporary register. LR1 321. The multiplexer 310 receives a lload [0] signal 142 as a control input. The multiplexer 3 1 0 also receives 1 s h i f t signal 1 6 8 as a control input. If the value of 1 1 oad [0] 142 is true, the multiplexer 310 selects X —ref —info 186 on the input of the load data; if the value of lshift 168 is true, the multiplexer 3 1 0 selects LR 1 3 2 1 output; otherwise, the multiplexer 3 1 〇 selects to hold the output of the register LR0 320 on the data input end. The register LR1 320 loads the output value of the multiplexer 310 at the rising edge of the clock period clk 2202 shown in FIG. 2. The multiplexer 3 1 0 outputs the result as the 1 a t e 〇 signal j g 1 in FIG. 1. — FIG. 4 shows a structural diagram of the first example of the deletion queue 415 shown in FIG. 5 according to the present invention. The structure of the deleted queue example in Figure 4 is similar to that of 3, the middle and late queues 1 4.6. Deletion queue includes 3 temporary storage-multiplexing 3. JI solid temporary storage-multiplexers are connected in sequence to form a queue. The three temporary storage multiplexers include the items KE2, KE1 * KE () shown in Figure 1. Delete the temporary multiplexer 412 and the temporary register 422 at the top of the rows 1 4 5 and the output of the temporary multiplexer 412. The multiplexer 412 is used to receive the deletion signal shown in FIG. 1 丨 4 1 is a data input terminal for receiving temporary storage 4 1 2 receives 1 1 〇ad [2] signal 1 4 2 as 142 is true, the multiplexer 412 selects negative 1 4 1; otherwise multiplexer 4 1 2 selects and maintains the output of 4 2 2. The register KR 2 4 2 2 is loaded into the multiplexer 412 at the rising edge of 202. The multiplexer includes a 2-input multi-storage ^ § 4 shows that 3 is KR 2 'for receiving and including a load data input terminal, . The multiplexer 4 1 2 also includes the output of a protector KR2 422. Multiplexer Controls k number. If 1 1 〇 a d [2] contains the delete signal on the data input terminal, the register KR2 on the data input terminal clock cycle c i shown in Figure 2 let the output value. 200414035 V. Description of the invention (22) *-一 -----: -— Delete the temporary storage of the queue 1 4 5 + paragraphs-multi-work cry, health device 411 and a temporary storage device 421, including one 3 input more. Receive the output of multiplexer 411. The multiplexer 411 includes two terminals, which are used for termination and used to receive deletion signals. Multiplexer 4 ... ^ lean input The input is used to receive the register KR1 42 \ and return an H; it includes a conversion data inclined to Λ Liushan Tian 10 1 ′ and Xi Gong is selected for 41 1. Multiplex cry 41, 1, pile ^〗 ^ "'Used to receive the input signal 142 of the register KR 2 4 2 2 as the control input. Multiplex 14 = ί; = No. 1⑼ as the control wheel ... Fruit 11 — [1] If the value of lshlft 168 is the output signal of the delete signal of the direct load multi-duplexer; otherwise, the multiplexer must be selected to keep the output of 421; 4 into 11 and select T 4. • Register KR1 421 is shown in Figure 2--"R1 Chuan's rising edge manned multi-monitor 411 = the median period of the clock cycle Chuan delete queue 1 4 5 bottom of the temporary storage-multiplex cry a work Register 4 1 0 and a temporary register 4 2 0, this temporary storage; f ::: input? The output of the multiplexer 41 is received. The multiplexer 41 is terminated with: =? And used to receive the delete signal 141. Multi-material input secondary input terminal, used to receive the return from the register KR〇 42〇. Xi Ge ^ 22 2 Including a conversion of the assets to the mountain, Xi Gong returned for 410. The multiplexer writes 41'0, the receiver 41 which receives the register 01421, and also receives two h + 20 = [] signals 14 2 as control inputs. Multiplex Mouth urges U to receive 1 s h 1 f t signal 1 β η argon 142 value is straight, multiplex control input. If Uoadm is "1; if lshift lfi8 the acre load data is input to the delete signal on the input terminal.

200414035 i. Manmin's explanation (23) =: save, 〇42〇 Load the output value of multiplexer 410 with the rising edge of the clock cycle shown in Figure 2. The multiplexer 4 «is output as the kill0 signal in Fig. 1; ... Fruit Fig. 5 shows a diagram according to the invention! Schematic diagram of the deleted example shown in. Deleting the queue M includes three choices i :: = wideband? This is connected to form a queue. These three choices are stored in items IV, KE2, KE1, and KE0. Temporarily delete the selection at the top of queue 145-the register includes one, register 5 ″ 2 and one register 5 2 2 and the register is marked as the output of Xi Gongyi 5 1 2. The multiplexer 5 j 2 includes a load signal 141 shown in FIG. The multiplexer 512 also includes: receiving picture with 5! 2! Shown 11〇ad [2] signal 14 xi = device

The value of Hoacim 142 is true, and the multiplexer 512 selects the delete signal 141; otherwise, the multiplexer 512 selects the load protection material 4 1 input, and the output of the f 2 device KR2 5 2 2 is selected. The register KR2 5 22 is loaded with the output values of the two multiplexers 512 at t = = t. At this time, the pulse period is marked as elk. Delete the middle selection of queue 145. The register includes _ 3 multiplexer channels. Output. Multiplexer 511 includes a receiver 1 4 1 for receiving a delete signal. Multiplex 5 n and 4 k input terminals, human terminal, used to receive the output of the register KR1 521, a two-wheeled wheel-a conversion data input, used to receive the register KR2 21, 1 return and output include

200414035 V. Description of the invention. (24) • * · * .. * β-multiplexer 5 11 receives the Uoad [i] signal 142 shown in FIG. 1 as a control signal. The multiplexer 511 also receives a 1 shift signal 168 shown in FIG. 1 as a control input. If the value of lload [l] 142 is true, the multiplexer 511 selects the delete signal 141 on the input of the load data; if the value of the 1 shift signal 168 is true, the multiplexer 511 selects the output of the KR2 522; otherwise, the multiplexer Hi select ^ to maintain the output of the register KR1 521 on the data input. The temporarily stored gKRi 52 '丨 is loaded into the output value of the multiplexer 51 1 at the rising edge of the clock cycle elk 2 0 2. . Delete the selection at the bottom of column 145-the register includes a 2-input multiplexer 510, a register 520 labeled KR0, which is used to receive the output of the multiplexer 51, and a 2-input multiplexer 509 . The multiplexer 509 includes a load data input terminal for receiving a delete signal. The multiplexer 509 also includes a lean input terminal for receiving the output of the register KR0 520. The multiplexer 509 receives the 11oad [0] signal 142 shown in FIG. 1 as a control signal. If the value of 11 〇ad [0] 142 is true, the multiplexer 509 selects the delete signal 141 on the input side of the load data; otherwise, the multiplexer 509 selects the temporary register KR0 on the data input side. 5 2 〇 output. The multiplexer 5110 includes a lean input terminal for receiving the output of the multiplexer 509. This output is "= 143. The multiplexer 510 also includes the output of a conversion data input device 511. The multiplexer 51 is received as a control input. If the eshift signal m is the output of the real working test r 1 η, $ 由 枓 知 工 5 5 11; otherwise, multiplying kp nq = household holding data The output of the multiplexer 509 on the input side. The output value is temporarily stored. The rising edge of cik 202 is loaded into the multiplexer 51.

200414035 V. Description of the invention (25)... '· · · • *. * * · · · · · · · Figure 6 shows three examples of deleting the queue 4 4 5 shown in Figure 1 according to the present invention. Schematic. Deletion of queue 1 4 5 in the figure is similar to deletion of queue 1 1 4 5 in FIG. 5 and corresponding components are also marked with similar numbers. The deletion queue shown in FIG. 6 differs from the value shown in FIG. 5 in the following points. The input KE 0 of the delete column 1 4 5 in FIG. 6 also includes four logic gates. One inverter 6 and two two-input AND gates 6 0 4 and 6 0 6 and one two-input OR Gate 6 〇8. The inverter 602 receives the 11 oad [0] signal 142 and supplies its output to an AND gate 604. The AND gate 604 receives the output of the register KR 0 522 and uses it as the second input. And gate 6 0 6 receives 1 l0ad [0] signal 142 as one of its inputs, and the same day Shou receives delete number 1 4 1 as its other input. The outputs of the two AND gates 604 and 6_06 are used as the inputs of the OR gate 608. The result of the OR gate 6 08 is output as the k i 1 1 0 signal 1 4 3 of the delete queue 145 shown in FIG. 1, instead of the output of the multiplexer 509 in the delete queue 145 shown in FIG. FIG. 7 shows a schematic diagram of the logic for generating the F-valid signal 188 shown in FIG. This logic includes an inverter 7 1 2 and a 2-input AND gate 7 丨 4. The inverter 7 丨 2 receives the k 1 1 1 0 signal 1 4 3 shown in FIG. 1 and supplies its output to the AND gate 7 丨 4 as one of its inputs. The other input of the AND gate 7 1 4 is the valid bit FV 134 of the formatted instruction queue 187 shown in FIG. 1. Therefore, the valid bits FV〇 U4 are limited by the ^ u〇 signal, so that the XIQ control logic 156 can know that the instruction provided to the instruction translator 38 through the early signal 193 is an invalid instruction, such as a deleted instruction. FIG. 8 shows a flowchart of the operation principle of the microprocessor 100 instruction deletion device shown in FIG. 1 according to the present invention. The process starts at block 802.

12829twf.ptd Page 33 200414035 V. Description of the invention (26) • * · · · · · · · · · · · ····, In block 802, the instruction formatter shown in Figure 1 1 1 6 'Set the instruction bit

An instruction in the group buffer 1 1 2 is formatted, and the formatted instruction is loaded into the early queue 1 3 2 by the F I Q control logic 1 1 8. In particular, the F I Q control logic 1 8 loads the formatted instructions into the invalid items at the lowest end of the early queue 1 2 2. In one example, block 802 occurs during the first clock cycle and is labeled c 1 0 c k 1 in FIG. 8. The flow advances to block 804. In block 804, the control logic 1 02 shown in FIG. 1 generates a true value on the delete signal 1 4 1 shown in FIG. 1 to explain that the early queue 1 is loaded in the previous clock cycle. 3 The 2 instruction must be deleted. In one example, block 804 occurs at the next clock cycle of clock cycle 1 and is labeled c 1 0 c k 2 in FIG. 8. The flow advances to 806. In block 806, the delete queue loads the value of the delete signal 1 4 1 generated in clock 2. This value is loaded into the invalid item at the lowest end of the delete queue. The flow advances to the decision function block 808. In the judgment function block 808, the judgment condition is to load the formatted instruction queue 1 187 in the block 802, for example, whether the instruction to be deleted is located in the format. After the instruction 伫Column 1 of the bottom 87 items. If this instruction is in the lowest end item of the formatted instruction queue 1 8 7, the flow advances to the decision function block 8 1 2; if not, the flow advances to block 8 1 8. In the judgment function block 8 1 2, the judgment condition is whether the value of the deletion signal 1 4 1 is not true. If true, the flow advances to block 81 4; otherwise, the flow advances to block 8 1 6. In block 814, a value of true will be generated as shown in Figure 1.

12829twf.ptd Page 34 200414035 V. Description of the invention (27) •-. ·:. · · · · · · · Ki 1 1 0 signal 1 43 to generate a FIQ valid bit FV0 1 34 The F-va 1 id signal 1 8 8 shown in FIG. 1 with a value of false is used to implement the deletion of the instruction. The process ends at block 8 1 4. 3 In block 816, a killO signal 143 shown in FIG. 1 with a value of false will be generated; therefore, if FV0 134 is true, then F_valid 188 is also true. The smuggling ends at block 8 1 6. In one example, all from block 804 to block 8 1 6 occur in the second clock cycle. In block 8 1 18, the formatted command queue 1 8 7 and delete queue 丨 4 5 move one item down. The flow advances to the decision function block 8 2 2. In the judgment function block 8 2 2, the judgment condition is that the formatted instructions loaded in the block 8 02 are listed as 1 8 7 instructions, for example, whether the instruction to be deleted 'is located in the formatted instruction. Queue the lowest end items of 1 8 7. If so, the flow advances to decision function block 8 2 4; otherwise, the flow returns to block 8 1 8. In the judgment function block 8 2 4, the judgment condition is whether the lowest end item of the deletion queue is true. If yes, the flow advances to block 8 2 6; otherwise, the flow advances to block 8 2 8. At block 826, a kill (Mf number 143 'shown in FIG. 1 with a value of true will be generated by limiting the FIQ valid bit fv〇134 to generate a false F_val id signal shown in FIG. 1 1 88, and use this to implement the instruction deletion. The process ends at block 8 2 6. At block 8 2 8, a false k 丨 丨 丨 〇 signal 4 4 will be generated; therefore, if FVO 134 If true, then F — Valid 188 is also true. The process ends at block 8 2 8. In one example, each from block 8 1 8 to block 8 2 8

12829twf.ptd Page 35 200414035 V. Description of the invention (28). The loops all occur at the next _ clock cycle next to clock 2.... Clock 3 'or the next adjacent clock In the cycle, the division instruction is transferred to the lowest end item of the formatted instruction symbol 187. FIG. 9 is a timing diagram illustrating the operation of the instruction deletion device shown in FIG. Figure 9 shows five clock cycles. Each clock cycle is represented by the true value of the graph in the inverse series level. Figure 9 shows the following when each instruction-formatter 116 generates a new formatted macro instruction. The state of XIQ 1 5 4 in Tian Tu 1 is dissatisfied. For example, χ 丨 Q i 5 4 can be changed from The instruction interpreter 1 3 8 receives the macro instruction; the formatted instruction queue 丨 8 7 is empty. In addition, in the example of FIG. 9, when the instruction translator 138 translates the formatted macro instruction of early 3 193 and generates a new micro instruction 71, the X worker 0 is empty. Therefore, the XIQ control logic 156 uses χ—to η signal 148 to raise the value of the valid signal 188 instead of storing F_valid 188 as a valid bit ^ 149 as shown in FIG. G. -As shown in the figure, in the first clock cycle 1, the instruction formatter 丨 i 6 produces a value of true, shown in Figure 1 F — new_instr signal 152, for the month, after formatting in 1. Instruction signal 1 9 7 contains a valid new formatted macro instruction. Because the formatted command queue 1 8 7 is empty, the FIQ control logic 118 in FIG. 1 generates a true el0ad [〇] signal 162, which is a valid new format of the command signal 197 formatted with ^ f. The transformed macro & 7, enters the transformed empty command line 1 8 7 and the lowest empty item EE 0. As shown in the figure, in the same instance, the signals 1 4 1 and k 1 1 0 are deleted. The signal 143 ’Invalid 188, X-valid 148 and the valid bit RV 189 are both

P.36 200414035 V. Description of Invention (29) False. · * In the second clock cycle 2, the valid bit FV〇34 of the item EE0 of the formatted instruction queue 1 8 7 in FIG. 1 is set to indicate whether EE () contains a valid instruction. At the rising edge of the clock cycle 2, a register 183 in FIG. 1 loads eload [0] 162 and outputs a value of true i0ad [0] 142. As shown in the figure, because el0ad [〇] ι62 is true, the new instruction is loaded into ER0 220 and outputted in the eariy signal 193 in FIG. 1 as the input of the instruction translator 1 38 in FIG. 1. The instruction translator 丨 3 8 translates this new macro instruction ′ and provides the resulting micro instruction 1 7 1 to X I Q 1 5 4. In addition, as shown in the figure, the control logic 102 generates new information about the new instruction on X-rel-info 186. Because ll〇ad [0] 142 is true, as shown in the figure, the multiplexer 41 〇 selects the load data input terminal and outputs the relevant information contained in X_rel_infol86 to 1 ate 0 1 9 1 as XIQ 1 5 4 and the input of the multiplexer 1 7 2 shown in FIG. 1. Further, because the instruction translator 138 has translated this new instruction in the second clock cycle, the FIQ control logic 11 8 generates a true value on the eshift signal 1 6 4 in the figure, so that the instruction can be in the third clock Cycle out of formatted instruction queue 1 8 7. Also in the second clock cycle 2, the control logic 1 finds a situation where a new instruction generated in the first clock cycle must be deleted, and therefore a graph with a value of true is generated in the second half of the second clock cycle The deletion signal 141 is shown at 1. Because in the second half of the clock 2 llad [0] 142 and the delete signal are both true, according to FIGS. 4 to 6, the killO signal 143 is also true. Further, since the ki 1 10 signal is 143 bits true, according to FIG. 7, F_val id 188 is a mother. Finally, as shown in the figure, because F_valid 188 is false and XIQ 154 is empty,

12829twf.ptd Page 37 200414035 V. Description of the invention (30) X_val id 148 is false at the end of the second clock cycle. In the third clock cycle 3, FV0 134 is false because the new instruction has \ next instruction queue 187. At the third time, the formatting edge is transferred, because XIQ154 is empty, and the XIq control logic 丨 "the rise of the second period 1 7 1 and 1 ate 0 1 9 1 provides information about the instruction, the microinstruction unit 176. In addition, In FIG. 1, the register 185 loads the eshif line stage to temporarily store a truth value 1 shi ft 168. Further, at the second clock y " 1 and turns out a false X —val id I48 is loaded into RV m, this signal In the end value of 'is false. Therefore, the microinstruction 1 7 1 generated in the second clock cycle and & entered in the second clock cycler 1 7 6 is marked as invalid, and the temporary storage as in the 仃 stage will be It is executed by the execution stage of the microprocessor 100 pipeline. Similarly, it can not be seen from Figure 9, although the new macro instruction has been generated and loaded into the formatted instruction on the first day. Column 丨 8 7 In the pulse period, 1 4 1 is not generated until the second clock period. The instruction deletion in FIG. 1 enables the macro instruction to be deleted. For example, the flag is invalid, & The instructions that have been deleted will be executed. This execution step is illustrated in Fig. 10, according to the instruction deletion shown in Fig. I of the present invention. Timing diagram of the management. Except when the instruction formatter 丨 i 6 generates a macro instruction after x is set, X qi 54 is full, and the figure S and the phase S in FIG. 9 are formatted as the example in FIG. 10 The XI qi 54 is the valid bit of the full X 丨 q 1 54 _, similar. Because 149 is displayed, the value of RV 189 and x — valid H8 is not $ 1 v2 in the clock cycle 1, XIQ_fuU 195 is true. As shown in Fig. 9, the instruction formatter 116 produces a new instruction on formatted instr 197—F—new—instr 152 is true. Because formatting—a "instruction"

200414035 V. Description of the invention (31). ··· .... · · · · · Column 1 8 7 is empty, as shown in Figure 9, FIQ control logic. Series 1 1 8 yields a value of true e 1 〇ad [0] signal 16 2 to load a valid new formatted macro instruction from the formatted instruction signal 197 to EE 0. The divide-by-J signal 141, killO signal 143, and F_valid 188 shown in FIG. 1 are all false, as shown in FIG. However, because X I Q 1 5 4 is full, the valid bit XV2 149 is true, that is, input 2 of XIQ 154 is valid. In clock cycle 2, as shown in Figure 9, FV 0 1 3 4 is set to indicate whether EE0 contains a valid instruction; register 183 outputs a value of true lload [0] 142; the new instruction is loaded Into ER0 220, and is output as earlyO signal 193 as input to instruction translator 138; new information related to new instructions is generated as χ — rel — inf〇186; multiplexer 310 selects the load data input terminal, The new related information provided by X-re 1 _ inf 〇 1 8 6 is output as lateO 191 as the input of XIQ 154 and multiplexer 172. However, since 乂 Q 1 5 4 is full at the beginning of the second clock cycle, different from the case shown in FIG. 9, the F I Q control logic 1 1 8 generates an e s h i f t signal 1 6 4 which is false. X I Q control logic 1 5 6 subsequently cancels X I Q — f u 1 1 1 9 5 ′ to indicate that the instruction translator 1 8 is ready to translate a new macro instruction in the third clock cycle. Similarly, in clock cycle 2, control logic 1 finds a situation where a new instruction generated in the first clock cycle must be deleted, and therefore a true delete is generated half a week after the first clock cycle Signal 1 4 1. Because iiad [0] 142 and the delete signal are both true in the second half of clock 2, according to Figs. 4 to 6, the killo signal 143 is also true. Further, since the kiu0 signal 143 is true, it can be known from FIG. 7 that F_valid 188 is false. because

12829twf.ptd Page 39 200414035 V. Description of the invention (32) • · · · · XIQ 154 is shifted downwards, so that XIq 154 is no longer full at the second clock cycle. 'XV2 149 turns false' means xiq 154 The instructions for the top item, that is, the item whose validity is explicitly indicated by XV 2 1 4 9 are no longer valid. In clock cycle 3 ', because the signal 164 is false at the rising edge of clock cycle cik 2 0 2, the new instruction is held in ER 〇 2 2 0 and provided by ear 1 y 0 1 9 3 Translate the instruction translator 丨 38. Equivalently, FV 0 1 3 4 remains true. The instruction translator 丨 38 translates the new macro instruction and provides the translated microinstruction 171 to xiq 154. Because lload [〇] 142 The rising edge of c 1 k 2 0 2 is true in the clock cycle, and the relevant information provided by X-rel — 186 in the second clock cycle is loaded into lr〇320. Because at other times in the clock cycle 丨1〇ad [〇] 142 & lshi ft 1 68 is false, 2: 'LR 0 3 2 0 within $, that is, information related to the instruction *, which is provided to XIQ 154 in response to ^ teO 191 After the third steam, the control logic 118 generates a value of true esMft letter J 4 on =, so that the command at the fourth time ㈣ keep Γί in the weekly data, ^ ^ 1 4 5 Enter ΚΕ 0 to delete 俨Jealousy 丨 4 丨 born and loaded and deleted queue Η 11〇 signal 14 ^ receive 供 被 is held in cycle 3, and remains false throughout clock cycle 3 through 1 8 8, F — The instruction 193 of va 1 1 d is an invalid instruction. This step is false ^ ^ supply instruction translator pulse cycle 2 control logic 10 2 produces ^ is / and 'is because the time represents the instruction generated in the clock cycle i The deletion signal "i to 9 7 must be broken and deleted. X v 2 1 4 9 Following 12829twf.ptd Page 40 200414035 V. Description of the invention (33) " ----: The narrative / step 'control logic assigns a false value to the delete signal within the clock cycle 3 1 4 1 (Also known as the undelete signal 丨 4 1). In clock cycle 4, because the new instruction is transferred out of the formatted instruction column 1 8 7. ‘F V 0 1 3 4 turns false. At the rising edge of clock cycle 4, graph i == register 185 loads eshift signal 164 and outputs a [, value through lshift 168. In addition, “X 丨 q control logic” 5 6 loads the translated micro-instructions 丨 7 1 and the instruction-related information provided through 1 a 11 e 0 1 9 1 to X I Q 1 5 4. but,

Because F — vai id 188 is false at the end of period 3 of the b-pulse Monday, a false value is loaded into XV2 149 to indicate that the translated microinstruction ππ loaded into XIQ 154 is invalid. Therefore, ^ is generated by instruction translator 1 3 8 at clock cycle 3 and loaded into XIQ from "々171 is marked invalid, and as expected, when its 1 Q 1 5 4 output, it will not be In the two examples of the execution phase of the processor's 100 pipeline, because XIQ 154 receives the input of the microinstruction 171 and is known as "f is invalid, it may be overwritten by the next microinstruction. H ΐ, i, 0. It can be seen that although the new macro instruction is ηΛλΛ ^ in the first clock cycle and is loaded into the formatted instruction queue 1 8 7, it is deleted-to the second clock Cycles will only happen. The instruction deletion Λ Shizhuo macro instruction in FIG. 1 can be deleted, that is, it is marked as invalid, and the deleted instruction will not be executed in the ordering stage. Shield throw, ^ is a huge picture illustrating the operation of the instruction deletion device shown in FIG. 1 according to the present invention. Except when the instruction formatter 116 generates a new formatting command, XIQ 154 is full and the formatted command queue 187 is not ^ ΐΞ 1 1 is similar to Figure 丨 0. The value of the delete signal 1 4 1 shown in Figure 1 must be loaded into the delete queue and this new value in the formatted command queue 187

200414035 V. Description of the invention (34) The macro "orders the items corresponding to the loaded items, and transfers downwards corresponding to the formatted command line 1 8 7 to ensure that the formatted command line 1 8 7 When a new macro instruction is provided, the value of the corresponding correct deletion signal is also provided by the deletion column. Relevant specific details will be explained below. Therefore, the value of the register 〇1 in queue 145 (labeled 42 in FIG. 4; [, 521 in FIGS. 5 and 6, and hereinafter referred to as ^ 421) is also shown in FIG. 11 . -XIQ_full 195 is true during clock cycle 1. As shown in Figs. 9 and 10, the 'instruction formatter 116 generates a new instruction on fmatted_instr 97, and F_new_instr 152 is true. Because EE0 contains a valid instruction 'FV0 134 is true; however, as shown in the figure, because Ει does not contain a valid instruction, the formatted instruction queue shown in Figure 1 shows the valid bit ρ of item EE 1 of 8 7 v 1 1 3 4 is false. Therefore, the f IQ control logic 1 1 8 generates a true e 1 0 ad [1] signal 1 6 2, thereby validating a new formatted macro instruction of the formatted instruction signal 1 9 7 Load EE 1. The signal ear 1 y 0 1 9 3 provides the instruction saved in e E 0, this instruction is marked as old instr in Figure 1 1; the signal lateO 191 provides information about the old instruction saved in LEO ', this information is marked as ο 1 dinf 〇 as shown. As shown in FIG. 10, the deletion signal 丨 4 1 丨 丨 丨 signal 丨 4 3 in FIG. 1 are both false and the valid bit XV2 149 is true. However, since FV0 134 is true and delete signal 141 is false, F_valid 188 is true. KR1 421 is false 0 In clock cycle 2, F V 1 1 3 4 is set to indicate whether E E 1 contains a valid instruction, and F V 0 also remains set. Old instruction save

12829twf.ptd Page 42 200414035 V. Description of the invention (35) ER 0 2 2 0, and the relevant information of the old instruction is stored in LR 0 3 2 0. The register 183 outputs a value of true lload [l] 142. The new instruction is loaded into ER1 2 2 1 as shown. The new information related to the new command is generated as X — rel — info 186, and the multiplexer 311 in FIG. 3 will select the load data input terminal, and this input is also provided to the register L R 1 3 2 1. Because X I Q 1 5 4 is full at the beginning of the second clock cycle, the F I Q control logic 1 1 8 generates an e s h i f t signal 1 6 4 with a false value. The X I Q control logic 1 5 6 then assigns a false value to X I Q — f u 1 1 1 9 5 to indicate that the instruction translator 3 8 will be ready to translate a new macro instruction in the third clock cycle. Also in the clock cycle 2, the control logic 1 02 finds that a new instruction generated in the first clock cycle must be deleted, and therefore generates a true delete signal in the second half of the second clock cycle 丨4 1. κ R 1 4 2 1 remains false. According to FIG. 4 to FIG. 6 ′, because the instructions in the formatted instruction list E E 0 in this example need not be deleted in this example, the k i 1 1 0 signal 1 4 3 is false. Further, since the k i 1 1 0 signal 1 4 3 is false and f v 0 1 3 4 is true, it can be seen from FIG. 7 that F_valid 188 is false. Because XIq 154 is shifted downward, Xj Q 1 5 4 is no longer full at the second clock cycle, and χ v 2 1 4 9 is false. This means that the instruction of the top item of X I Q 1 5 4, that is, the item whose validity is specified by χ v 2 1 4 9, is no longer valid. In the daily pulse period 3, because the e s h 丨 f t signal 丨 6 4 is false at the rising edge of the clock period c i k 2 0 2 ’The new instruction is kept in ER i 2 2 丨 and the old instruction

It is kept at E R 0 2 2 0, and the general talk 1 Π 1 Π O 1 overearlyO 193 is provided to instruction translation = 8 / ^ 转 /// 八 川 物 0134 remains true. Instruction translator 138 Reposts # 售 的 大 集 心 令 ’and provides the translated microinstructions 17ι to xiq

12829twf.ptd

Page 43 200414035 V. Description of the Invention (36) 154. Because in the clock cycle 3 he LRO 32〇 \, U〇ad [〇] 142

The old information about the command will pass the U of ': =, that is, old 154. Because lload [〇] 14 19 is provided to XIQ, the rising edge of fclk 2 0 2 is true in the second clock cycle, and the information is carried in LR1 321. After the new correlation series U8 provided by Ί21 / η〇I86 started to produce a straight mouth with two values, the FIQ control logic is also in the day guard cycle 3, because the clock Η1 1 Θ does not. But 疋 'according to Fig. 4 to Fig. 6' kii 丨 Enter a y, the control logic 102 assigns a false value to the delete signal at clock cycle 3, so jm4 'Because the new instruction is transferred from positive to delete, / LTi ΐ Γ On the rising edge of clock cycle 4, the xiq control logic 156 will carry the microinstruction 171 translated from the private sale order and the instruction information through ia to XIQ 154. In addition, the register i85 is loaded,

= And output via lshift 168—truth. Because XIQ 154 complains that it can accept another microinstruction, esMft is straight. Because the eshift signal 164 at the rising edge elk 2 0 2 in the clock cycle is straight / so it is transferred to ER 0 2 2 0 and provided to ‘7 translators 1 3 8 through eary 0, 193 for translation. F V 0 1 3 4 remains true. The instruction translator 1 3 8 translates the new instruction and provides the obtained microinstruction 丨 7 1 to χ 丨 q °

200414035 V. Description of Invention (37) 154. Because lshift 168 is true in clock cycle 4, the new instruction related information kept at LR 1 3 2 1 is selected as the switching data input terminal of multiplexer 3 1 0 and is provided externally through the lateO signal 191 ,as the picture shows. Also in the clock cycle 4, the value of the delete signal 1 4 1 generated in the clock cycle 2 and stored in the delete queue 1 4 5, that is, the delete bit, is transferred from KR1 421 to FIG. 4 KR0 4 2 0 (or KR0 520 in Figures 5 and 6). Therefore, it can be known from FIG. 4 to FIG. 6 that it leads to the generation of a kill0 signal 1 4 3 with a true value. According to FIG. 7, F _ v a 1 i d 1 8 8 is false accordingly. In clock cycle 5, because the new instruction is transferred out of the formatted instruction queue 1 8 7, the F I Q control logic 1 1 8 clears F V 0 1 3 4. At the rising edge of the clock cycle 5, the X I Q control logic 1 5 6 loads the micro instruction 1 71 and the information about the new instruction provided by 1 a t e 0 1 9 1 into the XIQ 154. However, because F_val id 188 is false at the end of clock cycle 4, a false value is loaded into XV2 149 to indicate that the translated microinstructions loaded into XIQ U4 are invalid. Therefore, the microinstruction 1 7 1 generated by the instruction translator, 1 3 8 and loaded into XI q 1 5 4 at clock cycle 3 is marked as beneficial, ° and as expected, when it is removed from XIQ i When 54 is output, no: executed by the execution stage of the 1001 pipeline. In one example: Because 7 154 items used to receive microinstructions 171 are marked as invalid, it is combined with the next microinstruction coverage. Figure 11 shows that although the new macro instruction has been generated in the first clock cycle and is loaded into the formatted instruction queue i 8 7, the delete letter is up to the second clock cycle. Just produced. The instruction deletion device in FIG. 1 enables the macro instruction to be deleted, that is, marks it as invalid, and so on

12829twf.ptd

200414035 V. Description of the Invention (38) The deleted instruction will not be executed during the execution phase. Although the present invention and its objects, features, and advantages have been explained in detail in this document, it may include other examples. For example, although the case where various instructions must be deleted has been mentioned in the text, the present invention can be applied to instruction deletion in other cases. In addition, although the article only describes an example of a microprocessor that translates a macro instruction into a micro instruction, a microprocessor uses a reduced instruction set computer (RI SC) to decode the RI SC instruction instead of translating the macro instruction into Examples of microinstructions still do not depart from the scope of contemplated embodiments of the invention. In addition to implementing the present invention in hardware, it can also be implemented in a computer-usable (eg, readable) medium through computer-readable code (eg, computer-readable code, information, etc.). Such computer code may cause the function of this invention to be implemented, imitated, or both. For example, this function can be implemented with a general-purpose programming language (such as C, C ++, JAVA, and other similar languages); it can also use the GDSII database and hardware description language (HDL), including Verilog HDL, VHDL, Altera HDL (AHDL ), Etc., or other programs and / or circuits (such as schematic) capture tools and other industry memory implementation tools. Computer code can be stored on any computer-usable (eg, readable) media, including peninsula memory, magnetic disks, CD-ROMs, CD-ROMs, DVD-ROMs, and the like, or placed on a computer as computer data (eg (Readable) communication media (such as carrier waves or other media including digital, optical, or analog media). As a result, computer code can be transmitted across communication networks, including the Internet and corporate intranets. As part of the intellectual property, the invention may be embodied in a core of a computer code, such as a microprocessor core, or a system

12829twf.ptd Page 46 200414035 V. Description of the invention (39) level design, such as in the single-chip microcomputer system (S0C), and transferred to the hard body as part of the integrated circuit product. At the same time, the present invention can also be implemented by a combination of hardware and computer code. Finally, those skilled in the art can use the disclosed technical content to make minor changes or modifications to equivalent embodiments without departing from the scope of the technical solution of the present invention. However, those who do not depart from the technical solution of the present invention Any simple corrections, equivalent changes, and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

12829twf.ptd Page 47 200414035 Brief Description of Drawings Figure 1 is a schematic structural diagram of a microprocessor according to the present invention. FIG. 2 is a schematic diagram illustrating the structure of a first queue of the instruction queue formatted as shown in FIG. 1 according to the present invention. FIG. 3 is a schematic diagram illustrating the structure of a second queue of the instruction queue formatted as shown in FIG. 1 according to the present invention. FIG. 4 is a schematic structural view illustrating a first example of a deletion queue shown in FIG. 1 according to the present invention. Fig. 5 is a structural diagram illustrating a second example of the deletion queue shown in Fig. 1 according to the present invention. Fig. 6 is a schematic structural view illustrating a third example of the deletion queue shown in Fig. 1 according to the present invention. FIG. 7 is a schematic structural diagram of F I Q control logic for generating the F_va 1 i d signal shown in FIG. 1 according to the present invention. Fig. 8 is a flowchart illustrating the operation principle of the microprocessor instruction deletion device shown in Fig. 1 according to the present invention. Fig. 9 is a timing chart illustrating the operation principle of the instruction deletion device shown in Fig. 1 according to the present invention. Fig. 10 is a timing chart illustrating the operation principle of the instruction deletion device shown in Fig. 1 according to the present invention. Fig. 11 is a timing chart illustrating the operation principle of the instruction deletion device shown in Fig. 1 according to the present invention. Explanation of the graphic symbols1 0 0: Microprocessor 1 0 2: Control logic

12829twf.ptd Page 48 200414035 Brief description of the diagram 1 0 4: Instruction cache 1 0 6: Branch target address cache 1 0 8: Pre-decoding logic 1 1 1: X_shi ft signal 1 1 2 : Instruction byte buffer 1 1 4: Instruction byte buffer control logic 1 1 6: Instruction formatter 1 1 8: FIQ control logic 1 3 2: Early queue 1 3 4: Valid bit 1 3 8: Instruction translator 1 4 1: delete signal 142: 1 load signal 1 4 6: late queue 148: X_valid signal 1 4 9: valid bit 1 5 1: phase I · 152: F_new_instr signal 1 5 3: F phase 1 5 4: Translated instruction queue 1 5 5: X stage 1 5 6: XIQ control logic 157: R stage 1 6 1: Control signal

12829twf.ptd Page 49 200414035 Schematic description 162 e 1 〇ad signal 164 es hi ft signal 164 1 〇ad signal 167 instruction byte 169 196: pre-decode information 171 micro instruction 172 178: multiplexer 175 prediction Branch target address 176 during execution stage register 177 correction address 179 next a mark address 181 currently selected address 182 current instruction index 183, 185: register 186: X — re 1_in f 〇 signal 187: Formatted instruction queue 188: F_va 1 id signal 189 • Valid bit register 191: Late signal 193 • Early signal 1 9 4: Branch prediction related information 1 95: XIQ_ful 1 signal 1 9 7: Formatted command 198: F_instr_info signal

12829twf.ptd Page 50 200414035 Brief description of the diagram 199: FIQ_ful1 signal 2 0 2 ··· Clock signal 210, 211, 212, 310, 311, 312, 410, 411, 412, 509, 510, 511, 512: Multi Workers 220, 221, 222, 320, 321, 322, 420, 421, 422, 520, 521, 5 2 2: Registers 60 2, 7 1 2: Inverters 604, 606, 714: and gates 6 0 8: OR gate

12829twf.ptd Page 51

Claims (1)

200414035 VI. Patent application scope 1. An instruction deletion device, in which an instruction is loaded into an instruction queue of a microprocessor at a first clock cycle, and the instruction is executed from a second clock cycle thereafter The output of the bottom line of the instruction queue. The instruction deletion device includes: a deletion signal for transmitting a value generated in a third clock cycle after the first clock cycle; and a deletion queue coupled to the deletion signal. For loading the value of the deletion signal generated in the third clock cycle and outputting the value in the second clock cycle; and a validity signal coupled to the deletion queue at the second time A pulse period is generated to indicate whether the instruction will be executed by the microprocessor. If the value of the delete signal output by the aforementioned delete queue in the second clock period is true, the validity signal value is false. 2. The instruction deletion device according to item 1 of the scope of the patent application, wherein the third clock cycle and the second clock cycle are the same clock cycle. 3. The instruction deletion device according to item 1 of the scope of patent application, wherein the third clock cycle is a clock cycle before the second clock cycle. 4. The instruction deletion device according to item 1 of the scope of the patent application, further comprising: a loading signal coupled to the deletion queue for indicating whether the instruction is already in the first clock cycle in the second clock cycle Loaded into the bottom item of the aforementioned instruction queue. 12829twf.ptd Page 52 200414035 VI. Patent application scope 5. According to the instruction deletion device described in item 4 of the patent application scope, if the loading signal is true, the third clock cycle and the second clock cycle For the same clock cycle. 6. According to the instruction deletion device described in item 4 of the scope of the patent application, if the loading signal is false ', the second clock cycle is after the third clock cycle. 7. The device for deleting an instruction according to item 4 of the scope of the patent application, further comprising: a logic coupled to the deletion queue for using the loading signal and the deletion queue in the second clock cycle. The value of the aforementioned deletion signal is output to generate the aforementioned validity signal. 8. The device for deleting an instruction according to item 1 of the scope of the patent application, wherein the deletion queue includes: a plurality of items for storing the values of the plurality of deletion signals generated in the corresponding plurality of clock cycles. 9. According to the instruction deletion device described in item 8 of the scope of the patent application, wherein the plurality of deletions described above, each of the queued items includes a load data input terminal 'this load lean input terminal is connected to the corresponding project to Receive the aforementioned deletion signal. 10. The instruction deletion device according to item 8 of the scope of the patent application, wherein each of the plurality of deletion queue items includes a holding data input terminal, and the holding data input terminal is coupled to the corresponding item to receive The current value of this corresponding item. 1 1 According to the instruction deletion device described in item 8 of the scope of patent application, 12829twf.ptd Page 53 200414035 VI. Scope of patent application Where each of the aforementioned plurality of deletion queue items a includes a transfer data input terminal 5 This transfer data ¥ m input terminal is coupled to the corresponding item to receive a One of a plurality of values of a deletion signal transmitted from an item above the corresponding item among the plurality of deletion queue items. 12. According to the instruction deletion device described in Item 8 of the patent scope, wherein the instruction queue includes a plurality of items for storing a plurality of instructions, and the plurality of deletion queue items are used to store the plurality of instructions. The value of the deletion signal corresponding to the plurality of instructions in the column a. According to the instruction deletion device described in item 1 of the patent scope, the instruction includes a variable-length instruction. 14 Λ According to the instruction deletion device described in item 13 of the patent application, the variable length instruction mentioned above includes an X 8 6 structure instruction. > 15 According to the instruction deletion device described in item 13 of the patent application, the instruction is provided by an instruction formatter to the instruction queue in the first clock cycle. 5 The foregoing instruction formatter determines the length of the instruction. 16 According to the request The instruction deletion device according to item 1 of the patent scope, wherein the foregoing instruction is first, and the second clock cycle is outputted to the instruction translator by the bottom end item 9 of the foregoing instruction queue to be translated into one or more microinstructions and processed by the micro. The processor executes selectively according to the aforementioned validity signal. 17 A method for deleting instructions in a microprocessor, including: • loading an instruction in a first queue at a _ first clock cycle, and generating a second clock cycle after the aforementioned first clock cycle A deletion signal 9 loads the values of the deletion signal in the aforementioned clock cycle 12829twf.ptd Page 54 200414035 VI. The scope of patent application is in a second queue; in a third clock cycle, it is judged whether the aforementioned value in the second queue is true, and the instruction is commanded in the aforementioned third clock cycle Output by the bottom item of the aforementioned first queue; and if the aforementioned value is true, execute the aforementioned instruction. 18. The method for deleting instructions in a microprocessor according to item 17 of the scope of the patent application, wherein the third clock cycle and the second clock cycle are the same clock cycle. 19. The method for deleting instructions in a microprocessor according to item 17 of the scope of the patent application, wherein the third clock cycle is the next clock cycle of the second clock cycle. 20. The method for deleting instructions in a microprocessor according to item 17 of the scope of the patent application, further comprising: formatting the aforementioned instructions before loading the aforementioned instructions into the aforementioned first column. 2 1. The method for deleting an instruction in a microprocessor according to item 17 of the scope of the patent application, further comprising: after loading the foregoing instruction in the first queue, determining whether the instruction is in the foregoing Shift down in a queue; and if the instruction has been shifted down in the first queue, after the value of the delete signal is loaded into the second queue, the value of the delete signal is transferred in the second queue Move down within the column. 2 2. The method for deleting instructions in a microprocessor according to item 17 of the scope of patent application, further comprising: 12829twf.ptd Page 55 200414035 6. Scope of patent application Before loading the aforementioned instruction into the aforementioned first column, predict that the aforementioned instruction is a branch instruction; find an incorrect prediction of the instruction for the aforementioned branch; and respond to the findings In the wrong prediction, during the second clock cycle, the operation for generating the deletion signal is performed. 2 3. The method for deleting instructions in a microprocessor according to item 22 of the scope of patent application, wherein a branch address cache memory of the microprocessor performs the foregoing instruction to predict the branch instruction. 24. The method for deleting instructions in a microprocessor according to item 22 of the scope of the patent application, wherein the misprediction of the branch instruction includes a misprediction of the length of the branch instruction. 25. The method for deleting instructions in a microprocessor according to item 22 of the scope of the patent application, wherein the misprediction of the branch instruction includes a misprediction of the address of the branch instruction. 26. The method for deleting instructions in a microprocessor according to item 22 of the scope of the patent application, wherein the misprediction of the branch instruction includes a misprediction that judges a non-branch instruction as a branch instruction. 27. The method for deleting instructions in a microprocessor according to item 17 of the scope of the patent application, further comprising: predicting based on a branch instruction to cause this microprocessor to branch, and the instruction is one of the branch instructions. The next instruction; and after branching the microprocessor, performing the operation of generating the deletion signal in the second clock cycle. 2 8. Delete in the microprocessor according to item 17 of the scope of patent application 12829twf.ptd Page 56 200414035 VI. Patent application method of dividing instructions, wherein the foregoing instruction is the next instruction of a branch instruction that is predicted to proceed, and the method further includes: in response to finding that the foregoing branch instruction is predicted to proceed, in The second clock cycle performs the operation of generating the deletion signal. 29. A microprocessor, comprising: a first queue for receiving an instruction and buffering; a logic coupled to the first queue for discovering a instruction that cannot be executed by the microprocessor A situation in which the foregoing logic generates a true value on a signal to explain the foregoing situation, wherein the signal having the true value is generated after the instruction is received by the first queue; and a second queue is coupled to the logic Is used to load the signal with a true value and then output the true value at the same time as the first queue output the instruction, wherein the microprocessor responds to the signal with a true value and invalidates the instruction without executing it. 30. The microprocessor according to item 29 of the scope of patent application, wherein the second queue includes: a plurality of storage units, which are used to store the aforementioned signals generated by the aforementioned logic in corresponding multiple clock cycles Multiple values. 31. The microprocessor according to item 30 of the scope of the patent application, wherein the first queue includes a plurality of storage units for storing a plurality of instructions, and the plurality of storage units for the second queue includes A plurality of signal values corresponding to the plurality of instructions stored in the plurality of storage units in the first queue are stored. 3 2. A computer data signal contained in a transmission medium, including: 12829twf.ptd Page 57 200414035 VI. Patent Application Scope A computer-readable code for providing a device to delete the queue of microprocessor instructions loaded in the first clock cycle and the instructions in the second clock cycle The instruction output by the bottom item of the queue, and the second clock cycle is after the aforementioned first clock cycle, the aforementioned computer code includes: a first code for providing a delete signal for passing a A value generated in the third clock period after the first clock period; a second code for providing a delete queue, coupled to the delete signal, for loading the third clock period generated The value of the deletion signal and outputs the value of the deletion signal in the second clock cycle; and a third code for providing a validity signal coupled to the deletion queue, the validity signal is The second clock cycle is generated to indicate whether the foregoing instruction will be executed by the microprocessor. If the value of the deletion signal output by the deletion queue in the second clock cycle is true, then the previous The validity of the signal is false. 12829twf.ptd Page 58