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Application filed by United Microelectronics CorpfiledCriticalUnited Microelectronics Corp
Priority to TW83104987ApriorityCriticalpatent/TW245821B/en
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Publication of TW245821BpublicationCriticalpatent/TW245821B/en
A process for erasing device isolation stress of IC includes the following steps: 1. forming one pad oxide on one Si substrate; 2. forming one Si3N4 layer on the pad oxide, and through etching forming opening, exposing region to be formed as field oxide; 3. through the opening implanting the first ion into the Si substrate; 4. oxidizing the Si substrate in the opening to form one field oxide by which the first ion forms one channel stop layer; 5. through the opening implanting the second ion into the field oxide; 6. thermal treating the field oxide for making the second ion form via hole in the field oxide and lower its stress; 7. removing the Si3N4 layer and the pad oxide, finishing the device isolation.
TW83104987A1994-05-311994-05-31Process for erasing device isolation stress of IC
TW245821B
(en)