TW212250B - - Google Patents

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Publication number
TW212250B
TW212250B TW081104161A TW81104161A TW212250B TW 212250 B TW212250 B TW 212250B TW 081104161 A TW081104161 A TW 081104161A TW 81104161 A TW81104161 A TW 81104161A TW 212250 B TW212250 B TW 212250B
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Taiwan
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semiconductor device
thin film
film
leads
patent application
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TW081104161A
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English (en)
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

21325U A6 _B6_ 五、發明説明（1) 發明之領域 本發明係關於半導體裝置，尤指一種使用可撓性薄膜 供為封裝材料之封裝。 發明之背景 一 人們對於更電路度板密度之需要，终於産生具有低輪 廓之小型半導體裝置。人們慣常由平面觀點考慮電路板 空間條件，薄封裝之動機則為次要論點。不過，隨著電 子業界考慮薄封裝，以針對與種種産品如記億卡、靈巧 卡、仿真卡等有關之密度問題，封裝厚度便為一性關鍵 性因素。 先前技藝封裝包括習知之封装，諸如National Semicondutor's TapePak™,帶自動接合（Tape Automated Bonding,簡稱 TAB),雙列直插引線（Dual I η - 1 i n e P i η ,簡稱D I P )封裝，及小型輪廓封裝（S in a 1 1 Outline Packages,簡稱 SOPs) e TAB 封裝使用一種液 體塑膠包封半導體晶片。習知之先前技藝封裝用金屬線 接合將晶片連接至引線框架。TapePak™ 沿封裝之四面 均有連接。 發明之槪逑 '' 經濟部中央標準局貝工消費合作社印製 本發明為一種半導體封裝，其中傜將半導體装置夾於 二薄層塑膠薄膜之間。薄膜使該裝置對環境氣密密封， 使該裝置具有機械強度，提供低輪廓，並為一種低重量 裝置。與標準之封裝技術比較，該封裝為成本低廉。 81. 5. 20.000(H) (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度遑用中國國家標準(CNS)甲4規格(210X297公釐) 212250 A6 B6 五、發明説明（2) 種 一 有 為具 可或 置具 裝模 體體 導導 半半 之 上 朝 片 晶 成 凸 之 點 觸 電 或體 ’積 下 朝 片 晶 路 可 形一 構合 配 力 . 應 圖 之 附 上 合 面 配 接 ， 交 明 線 說 n 弓 歹 1 下 部 之 凸 例 使 施 以 實 , 佳 線 較 引 項 置 一 偏 之 用 。明 使少發 環最本 承為由 支減 將 慮 C 考的 色目 特多 穎諸 新其 種及 •I ΙΛ 1" 之步 釋進 閫術 所技 圍之 範表 利 '代 專所明 請明說 申發要 附本簡 後白之 及明圖 以會附 圖 面 剖 視圖 側視 之上 裝之 封裝 之封 明之 發 1 本圖 為為 1 2 圖圖 圖 視 。 側圖 之視 裝倒 封之 之裝 上封 朝之 側環 點承 觸支明 具及說 模線之 體引例 導置施 半偏實 以有佳 一 一 較 為為之 3 4 明 圖圖發 本 多體可 有導膜 上半薄 10。料 具點材 模觸此 體部 ， 導凸蓋 半一覆 。每以 置至予 裝箸膜 體附薄 導11料 半線材 裝引一 封一以 膜 。a 5 ο 薄 1 1 1 點面 示觸背 1 部之 圖凸具 痼模 為 如 例 為 此 冊 註 有 具 ill 種1 之 造 製 所 材底 片之 之具 度模 厚體 吋導 05半 ο . 0 為脂 可樹 膜物 薄化 此硫 。撐 料苯 材聚 性為 撓料 可材 膜之 薄性 之般 標一 商 〇 (請先閱讀背面之注意事項再填寫本頁) 裝- 訂- 經濟部中央標準局貝工消費合作社印製 間選 之任 線可 引線 與引 蓋 。 覆合 在接 。波 蓋音 覆超 以成 予作 膜位 薄部 膠之 塑示 由所 也 B 11及 線 A 引頭 及箭 面在 引 例 施 實1 在 0 圍 周 膜-C 薄成 部製 底所 於架 叠框 摺線 > 弓 示之 所把 中鍍 1 由 函為 如線 本紙張尺度逍用中B國家標毕(CNS)甲4規格(210x297公*) 81. 5. 20,000(H) 經濟部中央標準局貝工消费合作社印製 五、發明説明（3) 画2為圖1之裝置之上視圖，示引線在積體電路裝置 上之一般配置。引線11予以繞裝置10設置，並且伸出裝 置之側面。除了提供外部電接觸至積體電路之引線11a 之尾端外，塑膠薄膜覆蓋該裝置及引線》引線數及引線 之排列並非關鍵性因素，而是可依裝置構形繞半導體裝 置排列。 封裝為輕質，在一實施例約為Q.Q3吋厚度。此種薄膜 封裝裝置可起機械式及電作用，並且在大多數情況，提 供較之標準環氧樹脂模製裝置更乾淨及更好之密封裝置。 該封裝之工序流程包括將晶片以接頭帶接合至一引線 框架或諸引線，將該裝置及諸引線置於二片薄膜之間， 並以超音波將薄膜密封於引線周圍之步驟。薄膜在諸引 線間自相密封並密封至引線，以形成一種氣密密封。薄 膜之密封可在使一連缜帶引線框架上之多値裝置分開前 予以完成。在密封後，裝置可予以標示符號，並在測試 前分開為痼別之裝置。 圖3示薄膜封裝之第二實施例。半導體裝或積體電路 2 0上有多痼觸點21。諸引線22予以接合至觸點，·然後並 向下傾斜至半導體裝置之平面。其後，將上薄膜23及下· 薄膜24密封於該裝置周圍，以及密封至諸引線22。 圖4示薄膜封裝之S —實施例。半導體裝置3Q予以安 裝為以觸點側面朝上。諸引線予以連接至觸點，然後並 向下彎曲，以位於半導體裝置之平面。一絶線材料之支 -5 - A 6 B6 (請先閲讀背面之注意事項再填寫本頁) 裝. 訂- 線‘ 本紙張尺度逍用中國《家楳毕（CNS)甲4規格(210X297公龙) 81. 5. 20,000(H)
Si挪ο A6 B6 五、發明説明（4 ) 環 合 線 承 接 引ai支 在32及 裝線 3 安弓點 3 於觸 環高至 承伸加 半 在 點 觸 至 面 上 份將 體gp並 一 ΛΜ 之 導U ， 延 於 並4¾置 3 5 ’ 膜 3 $ Μ膜 冑㈣® - 膠 2塱Η® f 一一 平 第 置 裝 3 用 端可 末也 線環 引承 與支 1X 3 ο 點少 觸最 輕至 減減 33其 環使 承並 支 ， 。力 面壓 下或 o J 3 力 覃應 裝之 體處 導合 半接 位 或 伸 延 置 裝 該 繞 全 完 可 〇 環域 該區 〇之 置點 裝觸 之 \ 合線 接引 線在 屬好 金恰 於於 (請先閲讀背面之注意事項再填寫本頁) 裝< 訂_ 線· 經濟部中央標準局貝工消費合作社印製 本紙張尺度逍用中B國家標準(CNS)甲4規格(210x297公*) 81. 5. 20,000(fl)

Claims (1)

  1. A B c D 212250 六、申請專利範si 1. 一種薄膜半導體裝置封裝，包含： 一半導體裝置； (請先閱讀背面之注意事項再填寫本頁) ‘多條引線有一端附著至半導體裝置及一第二端延伸 離開該半導體裝置； - 一第一薄膜在半導體模具及引線之一側面；以及 一第二薄膜在與上述第一薄膜相反之半導體模具及 引線之側面； 其中上述第一及第二薄膜予以在上述諸引線間彼此 接合，並予接合至上述諸引線'以形成一供上述半導 體裝置之密封式薄膜封裝，而上述諸第二端自該薄膜 封裝伸出。 2. 根據申請專利範圍第1項之薄膜封裝，其中上述第一 及第二薄膜像予彼此超音波接合及接合至上述多條引 線。 3. 根據申請專利範圍第3項之薄膜封裝，其中上述第二 引線端自接合之薄膜伸出，並且摺回於薄膜封裝之一 部份。 4. 根據申請專利範圔第1項之薄膜封裝，包括一在薄膜 封裝内之金臑環，此金鼷環將薄膜支承於引線端附著， 至半導體裝置之部位。 短.濟部中央標準局R工消費合作杜印製 5. 根據申謓專利範圍第1項之薄膜封装，其中薄膜係一 種聚苯撐硫化物樹脂。 6. 根據申諳專利範圍第1項之薄膜封裝，其中引線像用 -7 - 本紙证尺度適】丨】家#準（CNS)»p43Lji格(210x297公 1?) + 81. 1. 5.000(H) 7 7 7 7 A B c D 六、申請專利範SI 一接頭片接合連接至半導體裝置。 7. 根據申請*專利範圍第1項之薄膜封裝，其中薄膜係在 諸裝置引線與一連缠引線框架帶分開前施加至半導體 裝置並將其密封。 - 8. —種薄膜半導體裝置封裝，包含： 一半導體裝置； 多條引線有一端附箸至半導體裝置及一第二端延伸 離開該半導體裝置； 一第一薄膜在半導體模具及引線之一側面；以及 一第二薄膜在與上述第一薄膜相反之半導體模具及 引線之倒面；以及 一金颶環在薄膜封装内將該薄膜支承在引線末端附 箸至半導體裝置之部位； 其中上述第一及第二薄膜予以在上述諸引線間彼此 接合，並予接合至上述諸引線，以形成一供上述半導 體裝置之密封式薄膜封裝，而上述諸第二端自該薄膜 封裝伸出。 9. 根據申請專利範圍第8項之薄膜封裝，其中上毬第一 及第二薄膜僳予彼此超音波接合及接合至上述多條引· 線。 經濟部中央標準局Η工消費合作社印製 (請先閑讀背面之注意事項再填寫本頁) 10. 根據申請專利範圍第8項之薄膜封裝，其中上述第 二引線端自接合之薄膜伸出，並且摺回於薄膜封裝之 —部份。 "8 - 本紙張尺度適丨丨]中《«家標芈（CNS)<P4规格(210x297公"ΪΠ ' 81. 1. 5.000(H) 212^^ AT B7 C7 D7 六、申請專利苑® 11. 根據申請專利範圍第8項之薄膜封裝，其中薄膜傷 一種聚苯撐硫化物樹脂。 12. 根據申請專利範圍第8項之薄膜封装 用一接頭片接合連接至半導體装置。 13. 根據申請專利範圍第8項之薄膜封裝 在諸裝置引線與一連缠引線框架帶分開 體裝置並將其密封。 ，其中引線傜 ，其中薄膜傜 前施加至半導 14. 一種製造薄膜封裝半導體裝置之方法 將一引線框架上之諸引線以接頭片接 包含下列步驟 合相互連接至 一 TAB接合凸起之半導體晶片； 施加薄膜材料至半導體裝置及引線之相對表面；以 及 超音波密封薄膜材料，以包封半導體裝置及諸引線 之一部份。 15. 根據申請專利範圍第14項之方法，包 内密封半導體裝置及諸引線之一部份以 環安裝於諸引線一部份之步驟。 16. 根據申諳專利範圍第14項之方法，其 使諸值別裝置分開前，施加至一連缠帶 多锢半導體裝置。 括在薄膜封装 前，將一支承 中薄膜傜予在 引線框架上之 ............................( ......................R...............................訂·.........................级 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局Η工消費合作社印製 本紙張尺度適川中B «家標毕（CNS) <P4規格(210x297公S) 81. 1. 5.000(H)
TW081104161A 1991-03-04 1992-05-28 TW212250B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/664,170 US5130783A (en) 1991-03-04 1991-03-04 Flexible film semiconductor package

Publications (1)

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TW212250B true TW212250B (zh) 1993-09-01

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Country Status (6)

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US (1) US5130783A (zh)
EP (1) EP0502710B1 (zh)
JP (1) JPH0567692A (zh)
KR (1) KR100263723B1 (zh)
DE (1) DE69212185T2 (zh)
TW (1) TW212250B (zh)

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JP3151219B2 (ja) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド 取り外し自在のリード支持体を備えた半導体接続構成体およびその製造方法
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JPH0567692A (ja) 1993-03-19
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US5130783A (en) 1992-07-14
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