TW202414796A - 用於替換金屬閘極接合堆疊式場效電晶體的多重臨限電壓解決方案 - Google Patents

用於替換金屬閘極接合堆疊式場效電晶體的多重臨限電壓解決方案 Download PDF

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TW202414796A
TW202414796A TW112117856A TW112117856A TW202414796A TW 202414796 A TW202414796 A TW 202414796A TW 112117856 A TW112117856 A TW 112117856A TW 112117856 A TW112117856 A TW 112117856A TW 202414796 A TW202414796 A TW 202414796A
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forming
gate
layer
dipole element
contacts
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TW112117856A
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鮑如強
德超 郭
俊利 王
吳恒
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美商萬國商業機器公司
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Abstract

本發明提供一種半導體裝置，其包括：一基板；一第一電晶體之集合，其定位於該基板之一上部表面上，該第一電晶體之集合中之各者包含一第一閘極及一第一介電質；一絕緣層，其定位於該第一電晶體之集合之一上部表面上；及一第二電晶體之集合，其定位於該第一電晶體之集合上方且其中該第一電晶體之集合位於該絕緣層之一上部表面上，該第二電晶體之集合中之各者具有一第二閘極及一第二介電質；其中該等第一介電質中之各者連接至一對應第一閘極中之各者的一側壁；且其中該等第二介電質中之各者連接至該絕緣層。

Description

用於替換金屬閘極接合堆疊式場效電晶體的多重臨限電壓解決方案
本文所描述之例示性實施例大體上係關於半導體裝置及其製造方法，且更具體言之，係關於多重臨限電壓用於堆疊式電晶體裝置之裝置及方法。
半導體封裝通常採用各種積體電路(IC)裝置，通常為諸如安裝於矽晶體基板或晶圓材料上之電晶體的電路元件。在製造併入電晶體之半導體封裝中，製造製程包括沈積材料以形成膜、遮蔽及圖案化、材料蝕刻及移除、及摻雜處理。在微程度上進行此等製造製程中，電晶體已在一個平面中產生，其中佈線/金屬化物形成於主動裝置平面上方，且因此已表徵為二維(2D)電路或2D製造。縮放努力已極大地增加2D電路中每單位面積電晶體之數目，但縮放努力在縮放進入單數字奈米半導體裝置製造節點時及在2D面積大小增大時遇到較大挑戰。為了補償至奈米級程度之按比例縮小且限制2D面積增大，已提出電晶體堆疊於彼此頂部上之三維(3D)半導體電路。
電晶體之堆疊係基於預期適用於未來邏輯技術之新裝置架構。然而，當考慮用於此新裝置架構之特定組態時，特定言之關於使用多重臨限電壓之閘極堆疊、替換金屬閘極及電晶體及其他裝置不確定性大量存在。在此類組態中，應考慮若干變數，即電晶體或裝置涉及材料降級、在單一裝置中提供多重電壓之能力及共用結構中之閘極之能力時，考慮電晶體或裝置之熱態樣的變數。
在一個例示性態樣中，一種半導體裝置，其包含：一基板；一第一電晶體之集合，其定位於該基板之一上部表面上，該第一電晶體之集合中之各者包含一第一閘極及一第一介電質；一絕緣層，其定位於該第一電晶體之集合之一上部表面上；及一第二電晶體之集合，其定位於該第一電晶體之集合上方且其中該第一電晶體之集合位於該絕緣層之一上部表面上，該第二電晶體之集合中之各者具有一第二閘極及一第二介電質。該等第一介電質中之各者連接至一對應第一閘極中之各者的一側壁。該等第二介電質中之各者連接至該絕緣層。
該第一電晶體之集合中之該等電晶體中之至少一者可包含一偶極元件，且該第一電晶體之集合中之該等電晶體中之至少一者可包含一非偶極元件。該第二電晶體之集合中之至少一個電晶體可以一堆疊式組態定位於該第一電晶體之集合中之至少一個電晶體上方且可界定一多重臨限電壓配置。該半導體裝置可進一步包含該第一電晶體之集合中之該等電晶體中之至少一者與該第二電晶體之集合中之該等電晶體中之至少一者之間的一自對準閘極連接。該半導體裝置可進一步包含該第二電晶體之集合之一上部表面上之一後段製程層。該半導體裝置可進一步包含該基板之一下部表面上之一背側配電網。
在另一例示性態樣中，一種用於形成一半導體裝置之方法，其包含：在一基板上形成矽結構層以形成一第一通道及一第二通道；處理該第一通道以形成一偶極元件及該第二通道以形成一非偶極元件；在該第一通道及該第二通道周圍沈積一第一高k介電層且在該第一高k介電層上沈積一第一層間介電質；在該偶極元件周圍及該非偶極元件周圍形成一底部虛設閘極；將一絕緣層接合至該底部虛設閘極及該絕緣層上之一矽層；在該偶極元件上方之該矽層中形成一第一電晶體元件，及在該非偶極元件上方之該矽層中形成一第二電晶體元件；在該第一電晶體元件及該第二電晶體元件周圍沈積一第二高k介電層且在該第二高k介電層上沈積一第二層間介電質；在該第一電晶體元件及該第二電晶體元件周圍形成一上部虛設閘極；移除該第一虛設閘極以形成一第一空隙；用一第一金屬填充該第一空隙以形成一第一替換閘極；移除該第二虛設閘極以形成一第二空隙；用一第二金屬填充該第二空隙以形成一第二替換閘極；形成至該第一替換閘極之一第一觸點之集合及形成至該第二替換閘極之一第二觸點之集合；在該第二觸點之集合上形成一後段製程層；及在該第一觸點之集合上形成一背側配電網。
在一基板上形成矽結構層以形成一第一通道及一第二通道可包含沈積Si及SiGe之交替層及移除該SiGe。形成該第一電晶體元件及該第二電晶體元件可包含在該矽層中形成鰭片式FET裝置。形成該第一電晶體元件及該第二電晶體元件中之一者可包含形成一第二偶極元件。移除該第一虛設閘極可包含自該第二層間介電質形成至該第一虛設閘極之開口及在該等開口之一或多個側壁上沈積間隔物。該方法可進一步包含經由該形成的開口拉動該第一虛設閘極之材料。用該第一金屬填充該第一空隙以形成該第一替換閘極可包含將該第一金屬連接至該絕緣層。該方法可進一步包含使該第一替換閘極與該第二替換閘極自對準。該方法可進一步包含進行一化學機械研磨以用該第二層間介電質平坦化該等觸點。
在另一例示性態樣中，一種用於形成一半導體裝置之方法，其包含：在一基板上形成一第一電晶體結構及一第二電晶體結構；將該第一電晶體結構圖案化為一偶極元件及將該第二電晶體結構組態為一非偶極元件；在該偶極元件及該非偶極元件上方形成一第一虛設閘極；在該第一虛設閘極上沈積一絕緣層；在該偶極元件上方形成一第三電晶體結構及在該非偶極元件上方形成一第四電晶體結構；在該第三電晶體結構及該第四電晶體結構上方形成一第二虛設閘極；用一第一替換閘極替換該第一虛設閘極；用一第二替換閘極替換該第二虛設閘極以在至少該第一電晶體結構與該第三電晶體結構之間形成一多重臨限電壓形式；在該第二替換閘極上方沈積一MOL層間介電層；自該MOL層間介電層形成至該第一替換閘極及該第二替換閘極中之一或多者之一第一觸點之集合；自該基板形成至該第一替換閘極之一第二觸點之集合；在該第一觸點之集合上形成後段製程層；及在該第二觸點之集合上形成一背側配電網。
形成一第三電晶體結構及形成該第四電晶體結構可包含形成一偶極元件及一非偶極元件。該方法可進一步包含在該第一虛設閘極周圍形成一第一高k介電層及一第一層間介電質，及在該第二虛設閘極周圍形成一第二高k介電層及一第二層間介電質。該方法可進一步包含在該後段製程層上形成一載體晶圓。
在另一例示性態樣中，一種用於形成一半導體裝置之方法，其包含：在一基板上形成一第一電晶體結構及一第二電晶體結構；圖案化該第一電晶體結構以形成一偶極元件及將該第二電晶體結構組態為一非偶極元件；在該偶極元件及該非偶極元件上方形成一第一虛設閘極；在該第一虛設閘極上沈積一絕緣層；在該偶極元件上方形成一第三電晶體結構及在該非偶極元件上方形成一第四電晶體結構；在該第三電晶體結構及該第四電晶體結構上方形成一第二虛設閘極；用一第一替換閘極替換該第一虛設閘極；用一第二替換閘極替換該第二虛設閘極以在至少該第一電晶體結構與該第三電晶體結構之間形成一多重臨限電壓形式；在該第二替換閘極上方沈積一MOL層間介電層；形成至該第一替換閘極及該第二替換閘極中之一或多者之一第一觸點之集合；形成至該第一替換閘極之一第二觸點之集合；在該第一觸點之集合上形成後段製程層；及在該第二觸點之集合上形成一背側配電網。
該第一觸點之集合可自該MOL層間介電層形成至該第一替換或該第二替換閘極中之一或多者，且該第二觸點之集合可自該基板形成至該第一替換閘極。該第一觸點之集合及該第二觸點之集合兩者可形成通過該MOL層間介電層。該第一替換閘極及該第二替換閘極可自對準。
在另一例示性態樣中，一種方法，其包含：在一基板上形成包含一偶極元件之一第一FET；在一基板上形成包含一非偶極元件之一第二FET；在該偶極元件周圍及該非偶極元件周圍沈積一底部虛設閘極及一第一介電層；將一絕緣層接合至該底部虛設閘極及該絕緣層上之一矽層；在該偶極元件上方之該矽層中形成一第三FET，及在該非偶極元件上方之該矽層中形成一第四FET；在該第三FET及該第四FET周圍沈積一上部虛設閘極及一第二介電層；用一第一金屬閘極替換該第一虛設閘極；用一第二金屬閘極替換該第二虛設閘極；形成至該第一金屬閘極之一第一觸點之集合及形成至該第二金屬閘極之一第二觸點之集合；在該第二觸點之集合上形成一後段製程層；及在該第一觸點之集合上形成一背側配電網。該第一介電層連接至該第一金屬閘極之一側壁。該第二介電層連接至該絕緣層。
該第一金屬閘極及該第二金屬閘極可自對準。
上文所描述之結構及方法的優點通常涉及熱預算態樣。特定言之，閘極堆疊之降級由於整個半導體封裝之3D態樣而最小化。此外，半導體封裝具有在單式結構中提供多重臨限電壓(例如，金屬閘極圖案化及偶極圖案化)之能力，因此增加整體效率。此外，本文所描述之實施例說明在單個結構中提供共用閘極及獨立閘極兩者之能力。
字組「例示性」在本文中用於意謂「充當實例、例子或說明」。不必將本文中描述為「例示性」之任何實施例理解為比其他具實施例較佳或優於其他實施例。描述於此具體實施方式中之所有實施例係經設置以使熟習此項技術者能夠製造或使用本發明之例示性實施例，且不限制受申請專利範圍限定之本發明之範疇。
本文所描述之例示性實施例提供多重臨限電壓(多重Vt)半導體封裝，其中至少一個場效電晶體(FET)定位於第二FET上方，使得兩個FET由隔離絕緣層分離。如本文所使用，FET之臨界電壓(Vt)為產生FET之源極與汲極之間的傳導路徑所需之最小閘極電壓。在此類封裝中，頂部閘極介電質可連接至隔離絕緣層，但底部閘極介電質可僅在底部閘極之側壁上連接。底部FET中之一者含有偶極元件，而底部FET中之另一者含有非偶極元件。自對準CT切口定位於頂部FET與底部FET之間。自對準閘極連接形成於頂部FET與底部FET之間。
現參考圖式，展示使用前側填充技術製造多重Vt半導體封裝或裝置之例示性方法。如圖1A、圖1B及圖1C中所展示，其中堆疊FET之多重Vt半導體裝置通常以100展示且下文稱為「半導體裝置100」。如所展示，半導體裝置100包括頂部層505中之兩個鰭片式FET裝置，兩個鰭片式FET裝置中之各者「堆疊」於底部層200中之具有非偶極元件之對應FET及具有偶極元件之FET上方，頂部層505及底部層200由接合氧化物層500耦接。底部層200連接至背側配電網(BSPDN)。頂部層505連接至後段製程層1800 (BEOL 1800)。載體晶圓1810安置於BEOL 1800上。
圖2A至圖18C繪示製造半導體裝置100之一個例示性方法。如圖2A中所展示，底部層之FET之俯視圖以200 (底部層200)展示。FET包括隨後各自形成非偶極元件及偶極元件兩者之第一結構205及第二結構210，非偶極元件及偶極元件鄰近地定位且在X方向上延伸。支撐結構215垂直於第一結構205及第二結構210定位且在Y方向上延伸。
圖2B、圖2C及圖2D說明根據如所揭示之例示性實施例之在製造底部層200之初始步驟且展示分別沿著線X、線Y1及線Y2截取之橫截面視圖。如所展示，支撐結構215包含其上形成內埋氧化物(BOX)層225之基板220 (例如，矽)。矽鍺(SiGe)及矽(Si)之交替層沈積於BOX層225上。在底部NS圖案化及蝕刻之後，第一結構205及第二結構210自BOX層225之上部表面延伸，個別層之集合包含SiGe及Si之交替層。
如圖3A中所展示，第一結構205之第一層之集合界定將隨後定義為具有非偶極元件之FET的通道，且第二結構210之第二層之集合界定將隨後定義為具有偶極元件之FET的通道。形成非偶極元件之第一層之集合可為或與對應於不具有偶極層之第一Vt相關聯，且形成偶極元件之第二層之集合可為或與對應於偶極層之第二Vt相關聯。
如圖3B、圖3C及圖3D中所展示(沿著如圖3A中所展示之X1、Y1及X2維度)，間隔物310形成於第一結構205及第二結構210周圍。移除SiGe，由此在Si之間及周圍留下開口315以為經沈積虛設閘極做準備。高k介電材料經磊晶沈積於BOX層225上(在320處展示)。層間介電質325 (ILD 325) (例如，二氧化矽)沈積於層320上。接著對第二結構210之矽進行偶極圖案化及處理以形成偶極元件。
如圖4A、圖4B及圖4C中所展示，底部虛設閘極400形成於在第一結構205之第一層之集合及第二結構210之第二層之集合(形成偶極元件之第二層之集合)周圍之開口315中。底部虛設閘極400之材料可為多晶矽。
如圖5A、圖5B及圖5C中所展示，接合氧化物層500沈積至底部虛設閘極400之頂部表面、間隔物310之上部邊緣及ILD 325上以為用於接合頂部層505中之一或多個頂部裝置之通道做準備。Si層510沈積至接合氧化物層500上。
如圖6A、圖6B及圖6C中所展示，頂部層505中之通道為經圖案化且形成至Si層510中以用於鰭片式FET裝置600之鰭片。
如圖7A、圖7B及圖7C中所展示，頂部層505經圖案化且高k介電材料經磊晶沈積於接合氧化物層500上以形成區710。上部層間介電質720 (上部ILD 720)沈積於上部區710上。接著可視情況進行偶極圖案化及處理以在頂部層505中形成偶極元件。可沈積多晶矽以在頂部層505中形成上部虛設閘極730。
如圖8A、圖8B及圖8C中所展示，ILD層810可沈積至上部ILD 720之上部表面上。開口接著可形成於上部ILD 720及頂部層505之剩餘部分中以打開底部虛設閘極400，由此暴露底部層200之多晶矽材料。內部間隔物800可沈積於開口之側壁上。內部間隔物800之材料可為TiN。
如圖9中所展示，自底部層200拉動多晶矽。
如圖10中所展示，自開口之側壁剝離內部間隔物800。多晶矽拉動及剝離內部間隔物800引起整個半導體裝置100中之空隙，其中頂部層505中之FET堆疊於底部層200中之FET上方。
如圖11中所展示，金屬填充物沈積至空隙中作為閘極材料1100。金屬填充物可為任何適合的金屬或合金。藉此，閘極材料1100連接至絕緣層(接合氧化物層500)。
如圖12中所展示，在堆疊式FET之間產生第一閘極切口1200。移除金屬填充物及ILD層810之上部層。
如圖13中所展示，第一閘極切口1200填充有適合的金屬以形成填充物1300。頂部閘極與底部閘極對準。
如圖14中所展示，第二閘極切口在頂部層505中產生且填充有適合的金屬以提供底部電晶體閘極拾取1400。
如圖15A及圖15B中所展示，移除頂部層505中之上部虛設閘極730之多晶矽，由此在鰭片式FET裝置600周圍留下空隙。
如圖16A及圖16B中所展示，在移除頂部層505中之上部虛設閘極730之多晶矽上後形成之空隙填充有頂部閘極材料1600，由此形成多重Vt裝置。
如圖17A、圖17B及圖17C中所展示，額外介電質沈積於層720上以形成中段製程(MOL) ILD層1750，且第一觸點CA1及CA2通過MOL ILD層1750形成至區710之材料，且第二觸點CB2亦通過MOL ILD層1750及整個頂部層505形成至接合氧化物層500 (隔離絕緣層)。另外，第三觸點CA2亦通過頂部層505形成至層320。介電質頂蓋1700可沈積於第三觸點CA2上。接著可進行化學機械研磨(CMP)以平坦化觸點與MOL ILD層1750。
如圖18A、圖18B及圖18C中所展示，後段製程(BEOL)層1800沈積於頂部層505上，且載體晶圓1810接合至BEOL層1800。接著翻轉該結構，且將背側配電網1900 (BSPDN 1900)沈積於基板220之底部表面上以產生如圖1中所展示之半導體裝置100。
在另一例示性實施例中，製造方法可相應地調整以產生如圖19A、圖19B及圖19C中所展示之半導體裝置2000。在半導體裝置2000中，鰭片式FET裝置600用具有根據如上文所描述之方法製造之非偶極裝置及/或偶極元件之額外FET 2010替換。
在另一例示性實施例中，一種方法在移除頂部層505中之上部虛設閘極730之多晶矽後經由形成空間為相同的。該空間填充有頂部閘極材料1600，由此形成多重Vt裝置，如以上圖16A、圖16B及圖16C中所展示。然而，如圖20A、圖20B及圖20C中所展示，觸點形式可產生與先前實施例相比不同的觸點配置。特定言之，第一觸點CA1及CA2通過MOL ILD層1750形成至區710之材料，第二觸點CB2及CB3亦通過MOL ILD層1750及整個頂部層505形成至底部閘極215，且第三觸點CA2亦通過頂部層505形成至層320。第四觸點CB1接著通過MOL ILD層1750形成且至頂部閘極材料1600。介電質頂蓋1700可沈積於第三觸點CA2上。接著對上部表面進行CMP以平坦化觸點與MOL ILD層1750。
接著，如圖21A、圖21B及圖21C中所展示，類似於圖18A、圖18B及圖18C，後段製程(BEOL)層1800沈積於頂部層505上，且載體晶圓1810接合至BEOL層1800。接著翻轉該結構，且將背側配電網1900 (BSPDN 1900)沈積於基板220之底部表面上以產生如圖22A、圖22B及圖22C中所展示之半導體裝置2200。
製造半導體裝置之一個例示性方法以圖23中之2300展示。在區塊2305處，FET之底部通道形成於基板上之BOX層上。如上文所指示，基板可為矽。底部通道可為Si及SiGe之交替層。在區塊2310處，底部虛設閘極形成於底部通道之結構周圍。在區塊2315處，移除底部虛設閘極之材料，且沈積IL及高k介電質層。可進行圖案化以在底部通道之結構上形成偶極元件，如2320處所展示，且任何底部電晶體觸點可如2325處所指示形成。如在區塊2330處所指示，頂部通道結構可在底部通道上方接合。如區塊2335處所指示，頂部虛設閘極可形成於頂部通道結構周圍，接著移除底部虛設閘極且形成IL及高k介電質層，如區塊2340處所指示。可進行間隔物沈積，諸如TiN/相對聚沈積及平坦化，如區塊2345處所指示。可形成CT切口以拉動底部虛設閘極之材料，如區塊2350處所展示，接著在2355處填充所得空隙以形成底部替換金屬閘極(RMG)。如區塊2360處所指示，移除頂部虛設閘極，且頂部RMG形成有多重Vt圖案化。形成觸點，如在區塊2365中。結構接著可經翻轉，且BSPDN可形成於表面上，如區塊2370處所指示。
上述例示性實施例展現各種高值屬性。舉例而言，最頂部電晶體或裝置之熱預算使得閘極堆疊降級由於整個半導體封裝之3D態樣而最小化。此提供優於先前技術之優點，原因在於解決堆疊式FET中之閘極堆疊熱預算之問題。此外，半導體封裝具有在單式結構中提供多重臨限電壓(例如，金屬閘極圖案化及偶極圖案化)之能力，因此增加整體效率。此外，本文所描述之實施例說明在單個結構中提供共用閘極及獨立閘極兩者之能力。
在一個態樣中，一種半導體裝置，其包含：一基板；一第一電晶體之集合，其定位於該基板之一上部表面上，該第一電晶體之集合中之各者包含一第一閘極及一第一介電質；一絕緣層，其定位於該第一電晶體之集合之一上部表面上；及一第二電晶體之集合，其定位於該第一電晶體之集合上方且其中該第一電晶體之集合位於該絕緣層之一上部表面上，該第二電晶體之集合中之各者具有一第二閘極及一第二介電質。該等第一介電質中之各者連接至一對應第一閘極中之各者的一側壁。該等第二介電質中之各者連接至該絕緣層。
該第一電晶體之集合中之該等電晶體中之至少一者可包含一偶極元件，且該第一電晶體之集合中之該等電晶體中之至少一者可包含一非偶極元件。該第二電晶體之集合中之至少一個電晶體可以一堆疊式組態定位於該第一電晶體之集合中之至少一個電晶體上方且可界定一多重臨限電壓配置。該半導體裝置可進一步包含該第一電晶體之集合中之該等電晶體中之至少一者與該第二電晶體之集合中之該等電晶體中之至少一者之間的一自對準閘極連接。該半導體裝置可進一步包含該第二電晶體之集合之一上部表面上之一後段製程層。該半導體裝置可進一步包含該基板之一下部表面上之一背側配電網。
在另一態樣中，一種用於形成一半導體裝置之方法，其包含：在一基板上形成矽結構層以形成一第一通道及一第二通道；處理該第一通道以形成一偶極元件及該第二通道以形成一非偶極元件；在該第一通道及該第二通道周圍沈積一第一高k介電層且在該第一高k介電層上沈積一第一層間介電質；在該偶極元件周圍及該非偶極元件周圍形成一底部虛設閘極；將一絕緣層接合至該底部虛設閘極及該絕緣層上之一矽層；在該偶極元件上方之該矽層中形成一第一電晶體元件，及在該非偶極元件上方之該矽層中形成一第二電晶體元件；在該第一電晶體元件及該第二電晶體元件周圍沈積一第二高k介電層且在該第二高k介電層上沈積一第二層間介電質；在該第一電晶體元件及該第二電晶體元件周圍形成一上部虛設閘極；移除該第一虛設閘極以形成一第一空隙；用一第一金屬填充該第一空隙以形成一第一替換閘極；移除該第二虛設閘極以形成一第二空隙；用一第二金屬填充該第二空隙以形成一第二替換閘極；形成至該第一替換閘極之一第一觸點之集合及形成至該第二替換閘極之一第二觸點之集合；在該第二觸點之集合上形成一後段製程層；及在該第一觸點之集合上形成一背側配電網。
在一基板上形成矽結構層以形成一第一通道及一第二通道可包含沈積Si及SiGe之交替層及移除該SiGe。形成該第一電晶體元件及該第二電晶體元件可包含在該矽層中形成鰭片式FET裝置。形成該第一電晶體元件及該第二電晶體元件中之一者可包含形成一第二偶極元件。移除該第一虛設閘極可包含自該第二層間介電質形成至該第一虛設閘極之開口及在該等開口之一或多個側壁上沈積間隔物。該方法可進一步包含經由該形成的開口拉動該第一虛設閘極之材料。用該第一金屬填充該第一空隙以形成該第一替換閘極可包含將該第一金屬連接至該絕緣層。該方法可進一步包含使該第一替換閘極與該第二替換閘極自對準。該方法可進一步包含進行一化學機械研磨以用該第二層間介電質平坦化該等觸點。
在另一態樣中，一種用於形成一半導體裝置之方法，其包含：在一基板上形成一第一電晶體結構及一第二電晶體結構；將該第一電晶體結構圖案化為一偶極元件及將該第二電晶體結構組態為一非偶極元件；在該偶極元件及該非偶極元件上方形成一第一虛設閘極；在該第一虛設閘極上沈積一絕緣層；在該偶極元件上方形成一第三電晶體結構及在該非偶極元件上方形成一第四電晶體結構；在該第三電晶體結構及該第四電晶體結構上方形成一第二虛設閘極；用一第一替換閘極替換該第一虛設閘極；用一第二替換閘極替換該第二虛設閘極以在至少該第一電晶體結構與該第三電晶體結構之間形成一多重臨限電壓形式；在該第二替換閘極上方沈積一MOL層間介電層；自該MOL層間介電層形成至該第一替換閘極及該第二替換閘極中之一或多者之一第一觸點之集合；自該基板形成至該第一替換閘極之一第二觸點之集合；在該第一觸點之集合上形成後段製程層；及在該第二觸點之集合上形成一背側配電網。
形成一第三電晶體結構及形成該第四電晶體結構可包含形成一偶極元件及一非偶極元件。該方法可進一步包含在該第一虛設閘極周圍形成一第一高k介電層及一第一層間介電質，及在該第二虛設閘極周圍形成一第二高k介電層及一第二層間介電質。該方法可進一步包含在該後段製程層上形成一載體晶圓。
在另一態樣中，一種用於形成一半導體裝置之方法，其包含：在一基板上形成一第一電晶體結構及一第二電晶體結構；圖案化該第一電晶體結構以形成一偶極元件及將該第二電晶體結構組態為一非偶極元件；在該偶極元件及該非偶極元件上方形成一第一虛設閘極；在該第一虛設閘極上沈積一絕緣層；在該偶極元件上方形成一第三電晶體結構及在該非偶極元件上方形成一第四電晶體結構；在該第三電晶體結構及該第四電晶體結構上方形成一第二虛設閘極；用一第一替換閘極替換該第一虛設閘極；用一第二替換閘極替換該第二虛設閘極以在至少該第一電晶體結構與該第三電晶體結構之間形成一多重臨限電壓形式；在該第二替換閘極上方沈積一MOL層間介電層；形成至該第一替換閘極及該第二替換閘極中之一或多者之一第一觸點之集合；形成至該第一替換閘極之一第二觸點之集合；在該第一觸點之集合上形成後段製程層；及在該第二觸點之集合上形成一背側配電網。
該第一觸點之集合可自該MOL層間介電層形成至該第一替換或該第二替換閘極中之一或多者，且該第二觸點之集合可自該基板形成至該第一替換閘極。該第一觸點之集合及該第二觸點之集合兩者可形成通過該MOL層間介電層。該第一替換閘極及該第二替換閘極可自對準。
在另一態樣中，一種方法，其包含：在一基板上形成包含一偶極元件之一第一FET；在一基板上形成包含一非偶極元件之一第二FET；在該偶極元件周圍及該非偶極元件周圍沈積一底部虛設閘極及一第一介電層；將一絕緣層接合至該底部虛設閘極及該絕緣層上之一矽層；在該偶極元件上方之該矽層中形成一第三FET，及在該非偶極元件上方之該矽層中形成一第四FET；在該第三FET及該第四FET周圍沈積一上部虛設閘極及一第二介電層；用一第一金屬閘極替換該第一虛設閘極；用一第二金屬閘極替換該第二虛設閘極；形成至該第一金屬閘極之一第一觸點之集合及形成至該第二金屬閘極之一第二觸點之集合；在該第二觸點之集合上形成一後段製程層；及在該第一觸點之集合上形成一背側配電網。該第一介電層連接至該第一金屬閘極之一側壁。該第二介電層連接至該絕緣層。
該第一金屬閘極及該第二金屬閘極可自對準。
在前述描述中，闡述諸如特定結構、組件、材料、尺寸、處理步驟及技術之許多特定細節，以便提供對本文揭示之例示性實施例之徹底理解。然而，一般熟習此項技術者將認識到，本文中所揭示之例示性實施例可在無需此等具體細節之情況下實踐。此外，可已忽略或尚未以順序描述熟知結構或處理步驟之細節以避免混淆所呈現之實施例。亦應理解，當諸如層、區或基板之元件稱作「在」另一元件「上」或「上方」時，其可直接在另一元件上或亦可存在介入元件。相比之下，當元件稱為「直接位於」另一元件「上」時，不存在介入元件。亦應理解，當元件稱為「在」另一元件「之下」或「下方」時，該元件可直接在另一元件之下或下方，或可存在介入元件。相比之下，當元件稱為「直接在」另一元件「之下」或「直接在」另一元件「下方」時，不存在介入元件。
已出於說明及描述之目的呈現本發明之描述，但該描述並不意欲為詳盡的或限於所揭示之形式。在不脫離本發明之範疇的情況下，一般熟習此項技術者將容易瞭解許多修改及變化。選擇並描述實施例以便最佳地解釋本發明之原理及實務應用，且使其他一般熟習此項技術者能夠關於具有適合於所預期之特定用途的各種修改之各種實施例來理解本發明。
100:半導體裝置 200:底部層 205:第一結構 210:第二結構 215:支撐結構 220:基板 225:內埋氧化物層 310:間隔物 315:開口 320:層 325:層間介電質 400:底部虛設閘極 500:接合氧化物層 505:頂部層 510:Si層 600:鰭片式FET裝置 710:區 720:上部層間介電質 730:上部虛設閘極 800:內部間隔物 810:ILD層 1100:閘極材料 1200:第一閘極切口 1300:填充物 1400:底部電晶體閘極拾取 1600:頂部閘極材料 1700:介電質頂蓋 1750:中段製程ILD層 1800:後段製程層 1810:載體晶圓 1900:背側配電網 2000:半導體裝置 2010:額外FET 2200:半導體裝置 2300:方法 2305:區塊 2310:區塊 2315:區塊 2320:區塊 2325:區塊 2330:區塊 2335:區塊 2340:區塊 2345:區塊 2350:區塊 2355:區塊 2360:區塊 2365:區塊 2370:區塊 CA1:第一觸點 CA2:第三觸點 CB1:第四觸點 CB2:第二觸點 CB3:第二觸點 X:線 Y1:線 Y2:線
例示性實施例之前述及其他態樣在結合隨附圖式讀取時在以下具體實施方式中更顯而易見，其中：
圖1A、圖1B及圖1C為其中堆疊FET之多重Vt半導體裝置的示意性側視圖；
圖2A為半導體裝置之底部層之元件的示意性俯視圖；
圖2B、圖2C及圖2D為圖2A之底部層的示意性側視圖；
圖3A為展示非偶極及偶極元件之圖2A之底部層的示意性俯視圖；
圖3B、圖3C及圖3D為圖3A之底部層的示意性側視圖；
圖4A、圖4B及圖4C為展示虛設閘極及ILD之圖3A之底部層的示意性側視圖；
圖5A、圖5B及圖5C為展示接合氧化物層及其上形成頂部層之矽層之底部層的示意性側視圖；
圖6A、圖6B及圖6C為其中形成有鰭片之矽層的示意性側視圖；
圖7A、圖7B及圖7C為展示頂部層中之ILD及高k介電層之鰭片的示意性側視圖；
圖8A、圖8B及圖8C為展示至底部層之開口及開口中之間隔物之頂部層的示意性側視圖；
圖9為具有拉動的虛設閘極之底部層的示意性側視圖；
圖10為自開口剝離至底部層之間隔物的示意性側視圖；
圖11為沈積於頂部及底部層中之金屬的示意性側視圖；
圖12為至頂部及底部層之經沈積金屬中之閘極切口的示意性側視圖；
圖13為填充有金屬之閘極切口的示意性側視圖；
圖14為至頂部層中以形成底部電晶體閘極拾取之額外閘極切口的示意性側視圖；
圖15A及圖15B為自頂部層拉動之虛設閘極的示意性側視圖；
圖16A及圖16B為沈積至自頂部層拉動以形成多重Vt裝置之虛設閘極之空間中之金屬的示意性側視圖；
圖17A、圖17B及圖17C為形成於多重Vt裝置中之觸點的示意性側視圖；
圖18A、圖18B及圖18C為在BEOL處理及載體晶圓接合之後多重Vt裝置的示意性側視圖；
圖19A、圖19B及圖19C為頂部及底部層兩者中之具有非偶極及/或偶極元件之多重Vt半導體裝置的示意性側視圖；
圖20A、圖20B及圖20C為具有通過頂部層至介電層之觸點之多重Vt半導體裝置的示意性側視圖；
圖21A、圖21B及圖21C為在BEOL處理及載體晶圓接合之後圖20A、圖20B及圖20C之多重Vt半導體裝置的示意性側視圖；
圖22A、圖22B及圖22C為在BEOL處理及載體晶圓接合之後多重Vt裝置的示意性側視圖；及
圖23為形成其中堆疊FET之多重Vt半導體裝置之一個例示性方法的流程圖。
100:半導體裝置
200:底部層
500:接合氧化物層
505:頂部層
1800:後段製程層
1810:載體晶圓
1900:背側配電網
CA1:第一觸點

Claims (25)

  1. 一種半導體裝置，其包含： 一基板； 一第一電晶體之集合，其定位於該基板之一上部表面上，該第一電晶體之集合中之各者包含一第一閘極及一第一介電質； 一絕緣層，其定位於該第一電晶體之集合之一上部表面上；及 一第二電晶體之集合，其定位於該第一電晶體之集合上方且其中該第一電晶體之集合位於該絕緣層之一上部表面上，該第二電晶體之集合中之各者具有一第二閘極及一第二介電質； 其中該等第一介電質中之各者連接至一對應第一閘極中之各者的一側壁；且 其中該等第二介電質中之各者連接至該絕緣層。
  2. 如請求項1之半導體裝置，其中該第一電晶體之集合中之該等電晶體中之至少一者包含一偶極元件且該第一電晶體之集合中之該等電晶體中之至少一者包含一非偶極元件。
  3. 如請求項1之半導體裝置，其中該第二電晶體之集合中之至少一個電晶體以一堆疊式組態定位於該第一電晶體之集合中之至少一個電晶體上方且界定一多重臨限電壓配置。
  4. 如請求項1之半導體裝置，其進一步包含該第一電晶體之集合中之該等電晶體中之至少一者與該第二電晶體之集合中之該等電晶體中之至少一者之間的一自對準閘極連接。
  5. 如請求項1之半導體裝置，其進一步包含該第二電晶體之集合之一上部表面上的一後段製程層。
  6. 如請求項1之半導體裝置，其進一步包含該基板之一下部表面上之一背側配電網。
  7. 一種用於形成一半導體裝置之方法，該方法包含： 在一基板上形成矽結構層以形成一第一通道及一第二通道； 處理該第一通道以形成一偶極元件及該第二通道以形成一非偶極元件； 在該第一通道及該第二通道周圍沈積一第一高k介電層且在該第一高k介電層上沈積一第一層間介電質； 在該偶極元件周圍及該非偶極元件周圍形成一底部虛設閘極； 將一絕緣層接合至該底部虛設閘極及該絕緣層上之一矽層； 在該偶極元件上方之該矽層中形成一第一電晶體元件，及在該非偶極元件上方之該矽層中形成一第二電晶體元件； 在該第一電晶體元件及該第二電晶體元件周圍沈積一第二高k介電層且在該第二高k介電層上沈積一第二層間介電質； 在該第一電晶體元件及該第二電晶體元件周圍形成一上部虛設閘極； 移除該第一虛設閘極以形成一第一空隙； 用一第一金屬填充該第一空隙以形成一第一替換閘極； 移除該第二虛設閘極以形成一第二空隙； 用一第二金屬填充該第二空隙以形成一第二替換閘極； 形成至該第一替換閘極之一第一觸點之集合及形成至該第二替換閘極之一第二觸點之集合； 在該第二觸點之集合上形成一後段製程層；及 在該第一觸點之集合上形成一背側配電網。
  8. 如請求項7之方法，其中在一基板上形成矽結構層以形成一第一通道及一第二通道包含沈積Si及SiGe之交替層及移除該SiGe。
  9. 如請求項7之方法，其中形成該第一電晶體元件及該第二電晶體元件包含在該矽層中形成鰭片式FET裝置。
  10. 如請求項7之方法，其中形成該第一電晶體元件及該第二電晶體元件中之一者包含形成一第二偶極元件。
  11. 如請求項7之方法，其中移除該第一虛設閘極包含自該第二層間介電質形成至該第一虛設閘極之開口及在該等開口之一或多個側壁上沈積間隔物。
  12. 如請求項11之方法，其進一步包含經由該等形成的開口拉動該第一虛設閘極之材料。
  13. 如請求項7之方法，其中用該第一金屬填充該第一空隙以形成該第一替換閘極包含將該第一金屬連接至該絕緣層。
  14. 如請求項7之方法，其進一步包含使該第一替換閘極與該第二替換閘極自對準。
  15. 如請求項7之方法，其進一步包含進行一化學機械研磨以用該第二層間介電質平坦化該等觸點。
  16. 一種用於形成一半導體裝置之方法，該方法包含： 在一基板上形成一第一電晶體結構及一第二電晶體結構； 將該第一電晶體結構圖案化為一偶極元件及將該第二電晶體結構組態為一非偶極元件； 在該偶極元件及該非偶極元件上方形成一第一虛設閘極； 在該第一虛設閘極上沈積一絕緣層； 在該偶極元件上方形成一第三電晶體結構及在該非偶極元件上方形成一第四電晶體結構； 在該第三電晶體結構及該第四電晶體結構上方形成一第二虛設閘極； 用一第一替換閘極替換該第一虛設閘極； 用一第二替換閘極替換該第二虛設閘極以在至少該第一電晶體結構與該第三電晶體結構之間形成一多重臨限電壓形式； 在該第二替換閘極上方沈積一MOL層間介電層； 自該MOL層間介電層形成至該第一替換閘極及該第二替換閘極中之一或多者之一第一觸點之集合； 自該基板形成至該第一替換閘極之一第二觸點之集合； 在該第一觸點之集合上形成後段製程層；及 在該第二觸點之集合上形成一背側配電網。
  17. 如請求項16之方法，其中形成一第三電晶體結構及形成該第四電晶體結構包含形成一偶極元件及一非偶極元件。
  18. 如請求項16之方法，其進一步包含在該第一虛設閘極周圍形成一第一高k介電層及一第一層間介電質，及在該第二虛設閘極周圍形成一第二高k介電層及一第二層間介電質。
  19. 如請求項16之方法，其進一步包含在該後段製程層上形成一載體晶圓。
  20. 一種用於形成一半導體裝置之方法，該方法包含： 在一基板上形成一第一電晶體結構及一第二電晶體結構； 圖案化該第一電晶體結構以形成一偶極元件及將該第二電晶體結構組態為一非偶極元件； 在該偶極元件及該非偶極元件上方形成一第一虛設閘極； 在該第一虛設閘極上沈積一絕緣層； 在該偶極元件上方形成一第三電晶體結構及在該非偶極元件上方形成一第四電晶體結構； 在該第三電晶體結構及該第四電晶體結構上方形成一第二虛設閘極； 用一第一替換閘極替換該第一虛設閘極； 用一第二替換閘極替換該第二虛設閘極以在至少該第一電晶體結構與該第三電晶體結構之間形成一多重臨限電壓形式； 在該第二替換閘極上方沈積一MOL層間介電層； 形成至該第一替換閘極及該第二替換閘極中之一或多者之一第一觸點之集合； 形成至該第一替換閘極之一第二觸點之集合； 在該第一觸點之集合上形成後段製程層；及 在該第二觸點之集合上形成一背側配電網。
  21. 如請求項20之方法，其中該第一觸點之集合自該MOL層間介電層形成至該第一替換或該第二替換閘極中之一或多者，且其中該第二觸點之集合自該基板形成至該第一替換閘極。
  22. 如請求項20之方法，其中該第一觸點之集合及該第二觸點之集合兩者形成通過該MOL層間介電層。
  23. 如請求項20之方法，其中該第一替換閘極及該第二替換閘極自對準。
  24. 一種方法，其包含： 在一基板上形成包含一偶極元件之一第一FET； 在一基板上形成包含一非偶極元件之一第二FET； 在該偶極元件周圍及該非偶極元件周圍沈積一底部虛設閘極及一第一介電層； 將一絕緣層接合至該底部虛設閘極及該絕緣層上之一矽層； 在該偶極元件上方之該矽層中形成一第三FET，及在該非偶極元件上方之該矽層中形成一第四FET； 在該第三FET及該第四FET周圍沈積一上部虛設閘極及一第二介電層； 用一第一金屬閘極替換該第一虛設閘極； 用一第二金屬閘極替換該第二虛設閘極； 形成至該第一金屬閘極之一第一觸點之集合及形成至該第二金屬閘極之一第二觸點之集合； 在該第二觸點之集合上形成一後段製程層；及 在該第一觸點之集合上形成一背側配電網； 其中該第一介電層連接至該第一金屬閘極之一側壁；且 其中該第二介電層連接至該絕緣層。
  25. 如請求項24之方法，其中該第一金屬閘極及該第二金屬閘極自對準。
TW112117856A 2022-09-15 2023-05-15 用於替換金屬閘極接合堆疊式場效電晶體的多重臨限電壓解決方案 TW202414796A (zh)

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