TW202341470A - 用於奈米帶架構的半導體結構 - Google Patents

用於奈米帶架構的半導體結構 Download PDF

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TW202341470A
TW202341470A TW111143388A TW111143388A TW202341470A TW 202341470 A TW202341470 A TW 202341470A TW 111143388 A TW111143388 A TW 111143388A TW 111143388 A TW111143388 A TW 111143388A TW 202341470 A TW202341470 A TW 202341470A
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fin
dielectric
gate structure
semiconductor device
layer
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TW111143388A
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李奧納 古勒
塔何 甘尼
查理斯 沃蘭斯
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美商英特爾股份有限公司
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Abstract

本文公開的實施例包括半導體裝置和形成此裝置的方法。在一實施例中，半導體裝置包括具有第一端和第二端的鰭。在一實施例中，第一介電質覆蓋鰭的第一端，以及第二介電質覆蓋鰭的第二端。在一實施例中，閘極結構在鰭的第一端上方，其中該閘極結構在鰭的頂表面和第一介電質的頂表面上。

Description

用於奈米帶架構的半導體結構
本公開的實施例係在半導體結構和處理的領域，特別是在鰭結構的末端具有介電質填充物的奈米帶結構。
在過去的幾十年裡，積體電路中功能特徵的縮放一直是半導體工業不斷發展的推動力。縮到越來越小的特徵使得能夠在半導體晶片的有限面積上增加特徵單元的密度。例如，縮小電晶體尺寸能夠在晶片上結合更多數量的記憶體或邏輯裝置，有助於製造具有更高容量的產品。然而，追求更大的容量並非沒有問題。最佳化每個裝置之性能的必要性變得越來越重要。
傳統和當前已知製程的可變性可能會限制將它們進一步擴展到10奈米節點或次10奈米節點範圍的可能性。因此，未來技術節點所需的功能元件的製造可能需要引入新方法或將新技術整合到當前製程中或取代當前製程。
在積體電路裝置的製造中，隨著裝置尺寸不斷縮小，諸如三閘極電晶體和全環繞式閘極(gate-all-around，GAA)電晶體的多閘極電晶體已經變得更加普遍。三閘極電晶體和GAA電晶體通常在塊材矽(bulk silicon)基板或絕緣體上矽(silicon-on-insulator)基板上製造。在某些情況下，塊材矽基板是首選，因為它們成本較低並且與現有的高產量塊材矽基板基礎架構相容。
然而，縮放多閘極電晶體並非沒有後果。隨著微電子電路的這些基本構建塊的尺寸減小以及在給定區域中製造的基礎構建塊的絕對數量增加，對用於製造這些構建塊的半導體製程的限制變得極大。
及
本文描述的實施例包括在鰭結構的端部處具有介電質填充物的奈米帶結構。在下面的描述中，闡述了許多具體細節，諸如具體的整合及材料體系，以便提供對本公開之實施例的透徹理解。對於本領域之技術人士來說顯而易見的是，可以在沒有這些具體細節的情況下實施本公開的實施例。在其他情況下，沒有詳細地描述眾所周知的特徵，諸如積體電路設計布局，以免不必要的模糊本公開的實施例。此外，應當理解的是圖中所示的各種實施例是說明性表示，不一定按照比例繪製。
在以下描述中也可能使用某些術語，僅用於參考目的，因此不旨在限制。舉例來說，諸如“上(upper)”、“下(lower)”、“上方(above)”、“下方(below)”、“底部(bottom)”和“頂部(top)”的術語是指圖式中所參考的方向。諸如“前面(front)”、“後面(back)”、“背面(rear)”和“側面(side)”等術語描述了元件部分在一致但任意參考框架內的方向及/或位置，其可以透過參考描述正在討論的元件的文本和相關聯的圖式而清楚地了解。此類術語可以包括上面特別提及的詞、其衍生詞和類似意思的詞。
為了提供上下文，圖1A-1D示出用於製造奈米帶或奈米線電晶體結構的一些處理操作。如圖1A的平面圖圖示所示，半導體裝置100包括複數個鰭110，其被設置在基板上。鰭110可以由交替材料層製成。例如，通道材料與犧牲層交替。然後將交替材料層圖案化成鰭，如圖1A中所示。鰭110的長度(圖1A中從上到下的方向)大於其寬度(圖1A中從左到右的方向)。在一些情況下，複數個鰭110已經被圖案化。也就是說，在過程流程的這一點上，存在穿過鰭110的切口112。隔離層105可以設置在基板上方和鰭110的表面上方。隔離層105可以是淺溝槽隔離(shallow trench isolation，STI)層等。例如，隔離層105可以包括矽和氧(例如，SiO 2)等。
現在參考圖1B，示出了將間隔層120設置在鰭110的側壁和頂表面上方之後的鰭110的平面圖圖示。間隔層120可以是絕緣材料。例如，間隔層120可以是對隔離層105有選擇性蝕刻的材料。在一些情況下，用以形成間隔層120的沉積過程是共形沉積過程。因此，鰭面對切口112的表面也將生長間隔層120。如圖1B中所示，間隔層120的端面121長入鰭110之間的切口112中。如以下將更詳細描述的，間隔層120的這種額外生長導致半導體裝置100中的潛在缺陷。例如，隨後沉積的閘極結構可能會向下延伸到鰭110面對切口112的表面。
現在參考圖1C，示出了在間隔層120周圍設置介電層130之後的半導體裝置100的平面圖圖示。介電層130可以是對間隔層120有選擇性蝕刻的任何合適的介電質材料。例如，介電層130可以是氧化物、氮化物、碳化物等。如所示，介電層130包括填充鰭110之間的切口112的介電材料的部分131。由於表面121的結構，部分131可以具有曲面。另外，應當理解的是，間隔層120將介電層130與鰭110隔開。也就是說，鰭110的任何部分都沒有直接接觸介電層130。
現在參考圖1D，示出了在去除間隔層120並且跨鰭110設置閘極結構140之後的半導體裝置100的平面圖圖示。如所示，間隔層120的去除導致圍繞鰭110之周邊的隔離層105暴露。由於間隔層120延伸到切口112中，隔離層105的部分106延伸超過鰭110的端部。因此，在鰭110的端部和在鰭110之間的介電層130的部分131之間存在間隙。這允許閘極結構向下延伸到鰭110的表面。
例如，圖2是半導體裝置200的橫截面圖示，如圖1D中沿線2-2所見。如所示，設置一對鰭210 A和210 B。該對鰭210 A和210 B可以各自包含基底基板211和複數個交替層212和213。層212可以是通道層。也就是說，半導體通道最終將由層212製成。層213可以是犧牲層。也就是說，層213最終將從結構中去除。隔離層205可以在層212和213下方將鰭210 A和210 B的兩端分開。在層212和213的層次，鰭210 A和210 B可以被圍繞鰭210 A和210 B的介電層的部分231分開。然而，由於部分231不直接接觸鰭210 A和210 B的端面，因此閘極結構240的部分243可能向下延伸至鰭210 A和210 B的端面。閘極結構240可以包括遮罩層241和在下面的多晶矽層242。部分243是多晶矽層242的一部分。
因此，本文公開的實施例包括使介電層能夠與鰭的端部直接接觸的過程流程。因此，沒有間隙可以沉積閘極結構的多晶矽。相反的，閘極結構被設置在鰭和介電層之間的界面上方。為了提供這樣的結構，直到間隔層沉積在鰭上之後才切割鰭。在沉積間隔層之後，穿過間隔件和鰭二者形成鰭中的切口。這暴露了鰭的端面，使得介電層可以直接接觸鰭的端部。另外，間隔件的剩餘部分保留，以便將介電質與將端部連接在一起的鰭的邊緣間隔開。圖3A-3E中提供了此種過程流程的範例。
現在參考圖3A，根據實施例示出了半導體裝置300的橫截面圖示。在一實施例中，半導體裝置300可以被製造於基板之上(基板在隔離層305下方)。下面的基板可以是半導體基板，諸如晶圓或其他矽片或另一種半導體材料。合適的半導體基板包括但不限於單晶矽、多晶矽和絕緣體上矽(silicon on insulator，SOI)，以及由其他半導體材料形成的類似基板，諸如包含鍺、碳或III-V族材料的基板。
在一實施例中，隔離層305可以設置在鰭310之間。圖3A中的鰭310也顯示為被隔離層305的材料覆蓋。然而，應當理解的是，鰭310從隔離層305向上延伸(即，出頁面)。隔離層305可以包括任何合適的電絕緣材料，例如但不限於包含矽和氧(例如，SiO 2)的材料。在一些實施例中，隔離層305可以被認為是淺溝槽隔離(STI)特徵。
在一實施例中，鰭310可以是適合形成奈米帶或奈米線裝置的半導體鰭。例如，鰭310可以包括交替的第一層和第二層。第一層可以是用於形成半導體通道的半導體材料，而第二層可以是對第一層有選擇性蝕刻的材料。鰭310可以由已知方法形成，諸如在下面的基板上形成交替的第一層和第二層，然後蝕刻該些層以形成鰭狀結構(例如，使用遮罩和電漿蝕刻過程)。
在一實施例中，第二層的犧牲材料可以是相對於第一層的材料可以被選擇性蝕刻的任何材料。用於第一層和第二層的材料可以包括例如但不限於矽、鍺、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP的材料。在一具體實施例中，第一層是矽，而第二層是SiGe。在另一具體實施例中，第一層是鍺，而第二層是SiGe。
現在參考圖3B，根據實施例示出了半導體結構300的平面圖圖示。如圖3B中所示，間隔件320設置在鰭310上方並圍繞鰭310。在圖3B中以虛線示出鰭310，以便說明它們存在於間隔件320下方。在一實施例中，間隔件320可以包括對隔離層305有選擇性蝕刻的材料。在一實施例中，間隔件320以共形沉積過程形成。
現在參考圖3C，根據實施例示出了半導體結構300的平面圖圖示。如圖3C中所示，切割一或多個鰭310以在鰭310之間設置切口312。在一實施例中，鰭310中的一些可能被切割不止一次，以便沿著鰭310的長度設置多個切口312。如圖3C中所標記的，切口312將鰭區分成第一鰭310 A和第二鰭310 B。在一實施例中，用於圖案化鰭310的圖案化過程也導致間隔件320被圖案化有匹配的切口。因此，鰭310的端面與間隔件320的端面實質上共平面。例如，第一鰭310 A的端面315與間隔件320的端面321實質上共平面。
現在參考圖3D，根據實施例示出了半導體結構300的平面圖圖示。如圖3C中所示，介電層330設置在間隔件320周圍。在一實施例中，介電層330包括對間隔件320有選擇性蝕刻的材料。例如，介電層可以包含氮化物、氧化物、碳化物等。在一實施例中，介電層330直接接觸被切割的鰭310的端面315。同樣地，介電層330接觸被切割的間隔件320的端面321。為了便於參考，介電層330在切口之間的部分可被稱為區域331。區域331可以透過介電層330的區域333耦合在一起。區域333可以沿著鰭310的長度延伸。然而，與區域331相比，區域333可以不直接接觸鰭310的部分。
現在參考圖3E，根據實施例示出了半導體結構300的平面圖圖示。如圖3E中所示，去除間隔件320並且形成閘極結構340。在一實施例中，可以使用對介電層330上的間隔件材料具有選擇性的蝕刻過程去除間隔件320。因此，去除間隔件320而實質上不改變介電層330的結構。間隔件320的去除導致隔離層305沿鰭310的長度的暴露。也就是說，鰭310保持與介電層330的區域333間隔開。如所示，一些閘極結構340可以越過鰭310的端部。然而，與圖1A-1D和圖2中所示的範例相比，閘極結構340不會向下延伸接觸鰭310的端面。
鰭310 A和310 B的端部之間的界面和介電層330在鰭310 A和310 B之間的部分331沿圖3E中的線A-A以橫截面圖顯示於圖4A中。現在參考圖4A，根據實施例示出了半導體結構400的橫截面圖示。第一鰭410 A和第二鰭410 B包括在基底411上的第一層412和第二層413。第一層412和第二層413可以實質上類似於上面更詳細說明的第一層和第二層。例如，第一層412可以是通道材料，而第二層413可以是犧牲層。在一實施例中，可以在鰭410 A和410 B的頂部上設置介電蓋(dielectric cap)414。
在一實施例中，鰭410 A可以透過隔離層405和介電層430的部分431與鰭410 B分開。如所示，介電層430的部分431可以與鰭410 A和410 B的端部直接接觸。此外，介電層430的部分431的頂表面與鰭410 A和410 B的頂表面可以是彼此實質上共平面的。但是，應當理解的是，在一些實施例中，介電層430的部分431與鰭410 A和410 B可以具有實質上不共平面的頂表面。如本文中所使用的，實質上共平面可以指彼此共平面約5nm內的兩個表面。應當理解的是，製造公差可能導致在圖式中看起來共平面的特徵實際上是非共平面的。
在一實施例中，可以在鰭410的頂表面和介電層430的部分431上方設置閘極結構440。閘極結構440可以包括多晶矽442和在多晶矽442上方的遮罩層441。與上面圖2中所示的實施例相比，多晶矽442不接觸鰭410 A和410 B的側壁。相反的，對於一些閘極結構，多晶矽442的底表面可以接觸鰭410的頂表面和介電層430的部分431的頂表面二者。
在圖示的實施例中，示出了製造階段。然而，應當理解的是，為了完成電晶體裝置的製造，可以繼續附加處理。例如，可以蝕刻鰭410在閘極結構440外部的部分並且用源極和汲極區域替換。在形成源極和汲極區域之後，可以用金屬閘極結構替換閘極結構，其過程通常被稱為替換金屬閘極過程。在這樣的實施例中，介電層圍繞閘極結構440，並且去除閘極結構440。此時可以去除犧牲的第二層413，並且以閘極堆疊替換。閘極堆疊可以包括閘極介電質和在閘極介電質上方的金屬。該金屬可以包含直接位於閘極介電質上方的功函數金屬和填充金屬。
閘極介電質可以是，例如，任何合適的氧化物，諸如二氧化矽或高k閘極介電材料。高k閘極介電質材料的範例包括，例如，氧化鉿、氧化矽鉿、氧化鑭、氧化鋁鑭、氧化鋯、氧化矽鋯、氧化鉭、氧化鈦、鋇鍶鈦氧化物、氧化鋇鈦、氧化鍶鈦、氧化釔、氧化鋁、鉛鈧鉭氧化物和鈮酸鉛鋅。在一些實施例中，當使用高k材料時，可以對閘極介電層執行退火過程以提高其品質。
當功函數金屬將用作N型功函數金屬時，功函數金屬較佳具有介於約3.9 eV和約4.2 eV之間的功函數。可用於形成功函數金屬的N型材料包括但不限於鉿、鋯、鈦、鉭、鋁和包括這些元素的金屬碳化物，即，碳化鈦、碳化鋯、碳化鉭、碳化鉿和碳化鋁。功函數金屬將用作P型功函數金屬時，功函數金屬較佳具有介於約4.9 eV和約5.2 eV之間的功函數。可用於形成功函數金屬的P型材料包括但不限於釕、鈀、鉑、鈷、鎳和導電金屬氧化物，例如，氧化釕。
雖然鰭410 A和410 B的結構和閘極結構440可以在附加製造期間改變，但應當理解的是，介電層430的部分431持續在半導體結構400中。例如，因為部分431與閘極結構440下方的鰭的部分相鄰，因此在部分431和第二層413之間的接觸可以用部分431和與閘極介電質或替換金屬閘極堆疊的另一部分之間的接觸替代。在一些實施例中，第一層412可以保持與部分431接觸。
現在參考圖4B，根據實施例示出了半導體結構400的橫截面圖示。圖4B中的橫截面類似於圖3E中線B-B所示的橫截面。如所示，多晶矽層442能夠環繞鰭410的三個邊(即，鰭410的頂表面和側壁面)。這是因為在介電層430和鰭410之間有間隙G。間隙G是在從結構中去除間隔層445時形成的。在一些情況下，多晶矽可以被稱為具有圍繞鰭410的U形。多晶矽的底部部分可以與隔離層405介接。
現在參考圖5A-5E，根據額外的實施例示出了描繪用於形成半導體結構500的過程的一系列透視圖圖示。特別是，圖5A-5E中所示的實施例更清楚地說明了切割後鰭的結構以及鰭和間隔件的表面。
現在參考圖5A，根據實施例示出了半導體結構500的透視圖圖示。在一實施例中，半導體結構500可以包括基板501，諸如半導體基板等。鰭510可以從基板501向上延伸。例如，子鰭511被設置與隔離層505相鄰，並且交替的第一層512和第二層513可以在隔離層505上方延伸。如所示，薄層的隔離材料也可以覆蓋鰭510的表面。
如所示，可以在基板501的表面上設置複數個實質上平行的鰭510。在圖示的實施例中，鰭510的寬度可以是不均勻的。例如，中間的兩個鰭510的寬度大於朝向圖5A邊緣的鰭510的寬度。然而，應當理解的是，鰭的寬度在一些實施例中可以實質上相等。類似地，鰭510之間的間隔可以是實質上均勻的。在其他實施例中，所有鰭510之間的間隔可以是不均勻的。
現在參考圖5B，根據實施例示出了在形成間隔件520之後的半導體結構500的透視圖圖示。在一實施例中，間隔件520可以共形地沉積在鰭510的表面上。因此，間隔件520可以環繞鰭510的側壁和頂表面。如所示，間隔件520覆蓋隔離層505緊鄰鰭510的邊緣的部分。
現在參考圖5C，根據實施例示出了在穿過間隔件520和鰭510形成切口561之後的半導體結構500的透視圖圖示。如所示，切口導致鰭510的端面與間隔件520的端面實質上共平面。也就是說，間隔件520僅沿著被切割的鰭510的長度保留，而非鰭510的端部。
現在參考圖5D，根據實施例示出了在沉積介電層530之後的半導體結構500的透視圖圖示。如所示，可以靠著鰭510和間隔件520的暴露面設置部分531。此外，部分533可以在間隔件520的邊緣之間沿著鰭510的長度延伸。
現在參考圖5E，根據實施例示出了在去除間隔件並且形成閘極結構540之後的半導體結構500的透視圖圖示。間隔件520的去除導致在鰭510和介電層530之間形成間隙G。間隙G允許閘極結構540環繞鰭510的側壁。然而，由於鰭510的端面處沒有間隙，因此透過介電層530避免閘極結構540與鰭510的端面接觸。
在一實施例中，閘極結構540包括多晶矽層542，其在遮罩層541下方。應當理解的是，可以實施附加處理以形成源極/汲極區域，並且形成替換金屬閘極。用於形成源極/汲極區域和替換金屬閘極結構的處理及所得到的結構與上面更詳細說明的相似，此處將不再重覆。
圖6示出根據本公開實施例之一種實施方式的計算裝置600。計算裝置600容納板子602。板子602可以包括多個元件，包括但不限於處理器604和至少一個通訊晶片606。處理器604物理和電氣耦合到板子602。在一些實施方式中，至少一個通訊晶片606也物理和電氣耦合到板子602。在其他實施方式中，通訊晶片606是處理器604的一部分。
取決於其應用，計算裝置600可以包括其他元件，這些元件可能或可能不物理和電氣耦合到板子602。這些其他元件包括但不限於揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編解碼器、視頻編解碼器、功率放大器、全球定位系統(GPS)裝置、指南針、加速度計、陀螺儀、揚聲器、相機和大容量儲存裝置(諸如硬碟驅動器、光碟(CD)、數位光碟(DVD)等)。
通訊晶片606實現無線通訊，用於將資料傳送至及自計算裝置600。術語“無線”及其衍生物可用於描述電路、裝置、系統、方法、技術、通訊通道等，其可透過非固體媒體使用經調變的電磁輻射來傳輸資料。該術語並不暗示相關聯的裝置不包含任何電線，儘管在一些實施例中它們可能不包含任何電線。通訊晶片606可以實現多種無線標準或協定中的任一種，包括但不限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生物，以及任何其他被指定為3G、4G、5G或更高版本的無線協定。計算裝置600可以包括複數個通訊晶片606。例如，第一通訊晶片606可專用於諸如Wi-Fi及藍牙等較短範圍無線通訊，以及第二通訊晶片606可專用於諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他等較長範圍無線通訊。
計算裝置600的處理器604包括封裝在處理器604內的積體電路晶粒。在一實施例中，處理器的積體電路晶粒可以包括具有緊鄰半導體鰭之一端的介電層的電晶體裝置，如本文中所述。術語“處理器”可以指處理來自暫存器及/或記憶體的電子資料以將該電子資料轉換成可以儲存在暫存器及/或記憶體的其他電子資料的任何裝置或裝置的一部分。
通訊晶片606也包括封裝在通訊晶片606內的積體電路晶粒。在一實施例中，通訊晶片的積體電路晶粒可以包括具有緊鄰半導體鰭之一端的介電層的電晶體裝置，如本文中所述。
在其他實施方式中，安置在計算裝置600內的另一元件可以包括具有緊鄰半導體鰭之一端的介電層的電晶體裝置，如本文中所述。
在各種實施方式中，計算裝置600可以是膝上型電腦、輕省型筆電、筆記型電腦、超級筆電、智慧型手機、平板電腦、個人數位助理(PDA)、超級行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機頂盒、娛樂控制單元、數位相機、可攜式音樂播放器或數位攝錄影機。在其他實施方式中，計算裝置600可以是處理資料的任何其他電子裝置。
圖7示出包括本公開之一或多個實施例的中介層700。中介層700是用於將第一基板702橋接到第二基板704的中間基板。第一基板702可以是，例如，積體電路晶粒。第二基板704可以是，例如，記憶體模組、電腦主機板或另一積體電路晶粒。在一實施例中，根據本文所述的實施例，第一基板702和第二基板704中的一個可以包括具有緊鄰半導體鰭之一端的介電層的電晶體裝置。通常，中介層700的目的是將連接擴展到更寬的間距或將連接重新路由到不同的連接。例如，中介層700可以將積體電路晶粒耦合到球柵陣列(ball grid array，BGA)706，其隨後可以被耦合到第二基板704。在一些實施例中，第一和第二基板702/704附接到中介層700的相對側。在其他實施例中，第一和第二基板702/704附接到中介層700的同一側。並且在其他實施例中，三個或更多個基板透過中介層700互連。
中介層700可以由環氧樹脂、玻璃纖維增強環氧樹脂、陶瓷材料或諸如聚醯亞胺的聚合物材料形成。在其他實施方式中，中介層700可以由替代的剛性或柔性材料形成，其可以包括與上述用於半導體基板的相同材料，諸如矽、鍺和其他III-V族和IV族材料。
中介層700可以包括金屬互連708和通孔710，其包括但不限於矽穿孔(through-silicon via，TSV) 712。中介層700可以進一步包括嵌入式裝置714，其包括被動和主動裝置二者。此類裝置包括但不限於電容器、解耦電容器、電阻器、電感器、保險絲、二極體、變壓器、感測器和靜電放電(ESD)裝置。諸如射頻(RF)裝置、功率放大器、電源管理裝置、天線、陣列、感測器和MEMS裝置等更複雜的裝置也可以形成在中介層700上。根據本公開的實施例，本文公開的裝置或過程可用於製造中介層700。
因此，本公開之實施例可以包括具有緊鄰半導體鰭之一端的介電層的電晶體裝置。
以上對本公開的實施例的圖示實施方式的描述，包括在摘要中描述的內容，並非旨在窮舉或將本公開限制為所揭露的精確形式。儘管本文出於說明性目的描述了本公開的具體實施方式和範例，但是在本公開的範圍內可以進行各種等效修改，如相關領域的技術人士將理解到的那樣。
可以根據以上詳細的說明對本公開進行這些修改。所附申請專利範圍中使用的術語不應被解釋將本公開限制為說明書和申請專利範圍中揭露的具體實施方式。相反的，本公開的範圍將完全由所附申請專利範圍確定，該申請專利範圍應根據既定的申請專利範圍解釋的原則來解釋。
範例1：一種半導體裝置，包括：具有第一端和第二端的鰭；覆蓋該鰭之該第一端的第一介電質；覆蓋該鰭之該第二端的第二介電質；在該鰭之該第一端上方的閘極結構，其中該閘極結構在該鰭的頂表面和該第一介電質的頂表面上。
範例2：根據範例1的半導體裝置，其中該鰭包括：複數個半導體通道在垂直堆疊中。
範例3：根據範例1或範例2的半導體裝置，其中該鰭的該頂表面與該第一介電質的該頂表面實質上共平面。
範例4：根據範例1至3的半導體裝置，還包括：具有第三端和第四端的第二鰭，其中該第二鰭的該第三端面向該鰭的該第二端，並且其中該第二介電質覆蓋該第二鰭的該第三端。
範例5：根據範例4的半導體裝置，還包括：在該第二鰭上方的第二閘極結構，其中該第二閘極結構在該第二鰭和該第二介電質上。
範例6：根據範例1至5的半導體裝置，其中該第一介電質和該第二介電質透過沿該鰭的長度設置的第三介電質相連接。
範例7：根據範例6的半導體裝置，其中該第三介電質與該鰭之將該鰭的該第一端連接到該鰭的該第二端的邊緣間隔開。
範例8：根據範例7的半導體裝置，其中該閘極結構在該鰭和該第三介電質之間。
範例9：根據範例1至8的半導體裝置，其中該第一介電質具有接觸該鰭的該第一端的實質上平面的表面。
範例10：根據範例1至9的半導體裝置，其中該閘極結構是金屬閘極結構。
範例11：根據範例1至10的半導體裝置，其中該閘極結構的一面偏離該鰭的該第一端。
範例12：根據範例1至11的半導體裝置，其中該閘極結構圍繞該鰭的側壁和該鰭的該頂表面。
範例13：根據範例12的半導體裝置，其中該閘極結構形成圍繞該鰭的U形。
範例14：一種形成半導體裝置的方法，包括：在基板上設置鰭，其中該鰭包括一對側壁和頂表面，其中該鰭包括複數個半導體通道；在該鰭的該些側壁和該頂表面上方形成間隔件；蝕刻穿過該間隔件和該鰭以形成將該鰭分成第一鰭和第二鰭的間隙；在該間隙中沉積介電層，其中該介電層直接接觸該複數個半導體通道；去除該間隔件；以及在該第一鰭的一端上方形成第一閘極結構以及在該第二鰭的一端上方形成第二閘極結構。
範例15：根據範例14的方法，其中該第一閘極結構落在該第一鰭和該介電層上。
範例16：根據範例14或範例15的方法，其中該第二閘極結構落在該第二鰭和該介電層上。
範例17：根據範例14至16的方法，其中該第一閘極結構和該第二閘極結構以替換金屬閘極過程形成。
範例18：根據範例14至17的方法，其中該複數個半導體通道是奈米帶或奈米線通道。
範例19：根據範例18的方法，其中該複數個半導體通道與犧牲層交替，以及其中該些犧牲層最終被去除並以閘極介電質和閘極金屬替換。
範例20：根據範例19的方法，其中該閘極金屬包含功函數金屬和填充金屬。
範例21：根據範例14至20的方法，其中在蝕刻穿過該間隔件和該鰭以形成分開該鰭的該間隙之後，該第一鰭的端面與該間隔件的第一面實質上共平面，以及其中該第二鰭的端面與該間隔件的第二表面實質上共平面。
範例22：根據範例14至21的方法，其中該介電層環繞該第一鰭和該第二鰭的周邊。
範例23：根據範例22的方法，其中該第一鰭的長度邊緣與介電層間隔開。
範例24：一種電子系統，包括：板子；耦合到該板子的封裝基板；以及耦合到該封裝基板的晶粒，其中該晶粒包括半導體裝置，其包括：具有第一端和第二端的鰭；覆蓋該鰭之該第一端的第一介電質；覆蓋該鰭之該第二端的第二介電質；在該鰭之該第一端上方的閘極結構，其中該閘極結構在該鰭的頂表面和該第一介電質的頂表面上。
範例25：根據範例24的電子系統，其中該第一介電質和該第二介電質透過圍繞該鰭的長度延伸的第三介電質相連接，並且其中該第三介電質與該鰭之將該鰭的該第一端連接到該鰭的該第二端的邊緣間隔開。
100:半導體裝置 105:隔離層 106:隔離層的部分 110:鰭 112:切口 120:間隔層 121:端面 130:介電層 131:介電材料的部分 140:閘極結構 200:半導體裝置 205:隔離層 210A:鰭 210B:鰭 211:基底基板 212:交替層 213:交替層 231:介電層的部分 240:閘極結構 241:遮罩層 242:多晶矽層 243:閘極結構的部分 300:半導體裝置 305:隔離層 310:鰭 310A:鰭 310B:鰭 312:切口 315:端面 320:間隔件 321:端面 330:介電層 331:區域 333:區域 340:閘極結構 400:半導體結構 405:隔離層 410:鰭 410A:鰭 410B:鰭 411:基底 412:第一層 413:第二層 414:介電蓋 430:介電層 431:介電層的部分 440:閘極結構 441:遮罩層 442:多晶矽 445:間隔層 500:半導體結構 501:基板 505:隔離層 510:鰭 511:子鰭 512:第一層 513:第二層 520:間隔件 530:介電層 531:部分 533:部分 540:閘極結構 541:遮罩層 542:多晶矽層 561:切口 600:計算裝置 602:板子 604:處理器 606:通訊晶片 700:中介層 702:第一基板 704:第二基板 706:球柵陣列(BGA) 708:金屬互連 710:通孔 712:矽穿孔(TSV) 714:嵌入式裝置
[圖1A]是根據實施例之基板上的鰭的平面圖圖示。
[圖1B]是根據實施例之在鰭的上方形成有間隔層的鰭的平面圖圖示。
[圖1C]是根據實施例之在間隔層周圍設置介電層之後的鰭的平面圖圖示。
[圖1D]是根據實施例之在去除間隔件並且在鰭的上方設置閘極結構之後的鰭的平面圖圖示。
[圖2]是根據實施例之圖1D中的結構的橫截面圖示，其示出了閘極結構向下延伸到鰭的側邊的部分。
[圖3A]是根據實施例之基板上的鰭的平面圖圖示。
[圖3B]是根據實施例之在鰭的上方形成間隔層之後的鰭的平面圖圖示。
[圖3C]是根據實施例之在進行多次切割以分離一或多個鰭之後的鰭的平面圖圖示。
[圖3D]是根據實施例之在鰭和間隔件周圍設置介電層之後的鰭的平面圖圖示。
[圖3E]是根據實施例之在去除間隔件並且在鰭的上方設置閘極結構之後的鰭的平面圖圖示。
[圖4A]是根據實施例之圖3E中鰭沿線A-A的橫截面圖示。
[圖4B]是根據實施例之圖3E中一個鰭沿線B-B的橫截面圖示。
[圖5A]是根據實施例之基板上的鰭的透視圖圖示。
[圖5B]是根據實施例之在鰭的上方設置間隔件之後的鰭的透視圖圖示。
[圖5C]是根據實施例之在鰭和間隔件在某些位置凹陷之後的鰭的透視圖圖示。
[圖5D]是根據實施例之在間隔件周圍設置介電層之後的鰭的透視圖圖示。
[圖5E]是根據實施例之在去除間隔件並且在鰭的上方形成閘極結構之後的鰭的透視圖圖示。
[圖6]示出根據本公開實施例之一種實施方式的計算裝置。
[圖7]是實現本公開之一或多個實施例的中介層。
200:半導體裝置
205:隔離層
210A:鰭
210B:鰭
211:基底基板
212:交替層
213:交替層
231:介電層的部分
240:閘極結構
241:遮罩層
242:多晶矽層
243:閘極結構的部分

Claims (25)

  1. 一種半導體裝置，包括： 具有第一端和第二端的鰭； 覆蓋該鰭之該第一端的第一介電質； 覆蓋該鰭之該第二端的第二介電質； 在該鰭之該第一端上方的閘極結構，其中該閘極結構在該鰭的頂表面和該第一介電質的頂表面上。
  2. 如請求項1的半導體裝置，其中該鰭包括： 在垂直堆疊中的複數個半導體通道。
  3. 如請求項1或2的半導體裝置，其中該鰭的該頂表面與該第一介電質的該頂表面實質上共平面。
  4. 如請求項1或2的半導體裝置，還包括： 具有第三端和第四端的第二鰭，其中該第二鰭的該第三端面向該鰭的該第二端，並且其中該第二介電質覆蓋該第二鰭的該第三端。
  5. 如請求項4的半導體裝置，還包括： 在該第二鰭上方的第二閘極結構，其中該第二閘極結構在該第二鰭和該第二介電質上。
  6. 如請求項1或2的半導體裝置，其中該第一介電質和該第二介電質透過沿該鰭的長度設置的第三介電質相連接。
  7. 如請求項6的半導體裝置，其中該第三介電質與該鰭之將該鰭的該第一端連接到該鰭的該第二端的邊緣間隔開。
  8. 如請求項7的半導體裝置，其中該閘極結構在該鰭和該第三介電質之間。
  9. 如請求項1或2的半導體裝置，其中該第一介電質具有接觸該鰭的該第一端的實質上平面的表面。
  10. 如請求項1或2的半導體裝置，其中該閘極結構是金屬閘極結構。
  11. 如請求項1或2的半導體裝置，其中該閘極結構的一面偏離該鰭的該第一端。
  12. 如請求項1或2的半導體裝置，其中該閘極結構圍繞該鰭的側壁和該鰭的該頂表面。
  13. 如請求項12的半導體裝置，其中該閘極結構形成圍繞該鰭的U形。
  14. 一種形成半導體裝置的方法，包括： 在基板上設置鰭，其中該鰭包括一對側壁和頂表面，其中該鰭包括複數個半導體通道； 在該鰭的該些側壁和該頂表面上方形成間隔件； 蝕刻穿過該間隔件和該鰭以形成將該鰭分成第一鰭和第二鰭的間隙； 在該間隙中沉積介電層，其中該介電層直接接觸該複數個半導體通道； 去除該間隔件；以及 在該第一鰭的一端上方形成第一閘極結構以及在該第二鰭的一端上方形成第二閘極結構。
  15. 如請求項14的方法，其中該第一閘極結構落在該第一鰭和該介電層上。
  16. 如請求項14或15的方法，其中該第二閘極結構落在該第二鰭和該介電層上。
  17. 如請求項14或15的方法，其中該第一閘極結構和該第二閘極結構以替換金屬閘極過程形成。
  18. 如請求項14或15的方法，其中該複數個半導體通道是奈米帶或奈米線通道。
  19. 如請求項18的方法，其中該複數個半導體通道與犧牲層交替，以及其中該些犧牲層最終被去除並以閘極介電質和閘極金屬替換。
  20. 如請求項19的方法，其中該閘極金屬包含功函數金屬和填充金屬。
  21. 如請求項14或15的方法，其中在蝕刻穿過該間隔件和該鰭以形成分開該鰭的該間隙之後，該第一鰭的端面與該間隔件的第一面實質上共平面，以及其中該第二鰭的端面與該間隔件的第二表面實質上共平面。
  22. 如請求項14或15的方法，其中該介電層環繞該第一鰭和該第二鰭的周邊。
  23. 如請求項22的方法，其中該第一鰭的長度邊緣與介電層間隔開。
  24. 一種電子系統，包括： 板子； 耦合到該板子的封裝基板；以及 耦合到該封裝基板的晶粒，其中該晶粒包括半導體裝置，其包括： 具有第一端和第二端的鰭； 覆蓋該鰭之該第一端的第一介電質； 覆蓋該鰭之該第二端的第二介電質； 在該鰭之該第一端上方的閘極結構，其中該閘極結構在該鰭的頂表面和該第一介電質的頂表面上。
  25. 如請求項24的電子系統，其中該第一介電質和該第二介電質透過圍繞該鰭的長度延伸的第三介電質相連接，並且其中該第三介電質與該鰭之將該鰭的該第一端連接到該鰭的該第二端的邊緣間隔開。
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