TW202333376A - 功率半導體元件 - Google Patents

功率半導體元件 Download PDF

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TW202333376A
TW202333376A TW111104777A TW111104777A TW202333376A TW 202333376 A TW202333376 A TW 202333376A TW 111104777 A TW111104777 A TW 111104777A TW 111104777 A TW111104777 A TW 111104777A TW 202333376 A TW202333376 A TW 202333376A
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epitaxial layer
power semiconductor
semiconductor device
doped
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TWI806414B (zh
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陳中怡
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鴻海精密工業股份有限公司
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Abstract

功率半導體元件包含第一電極、基底、第一磊晶層、第二磊晶層、閘極電極以及第二電極。基底位在第一電極上，基底具有主動區以及圍繞主動區的終端區。第一磊晶層位於基底上，其中第一磊晶層具有第一導電類型，第一磊晶層包含第一摻雜區以及第二摻雜區。第一摻雜區具有第一導電類型且位在終端區以及主動區中。第二摻雜區具有第二導電類型且位在終端區中。第二磊晶層位於第一磊晶層上。閘極電極位於第二磊晶層上且位在主動區中。第二電極位於第二磊晶層上且位在主動區中。

Description

功率半導體元件
本揭露是有關於一種功率半導體元件。
功率半導體元件之性取決於崩潰電壓(Breakdown voltage)及導通電阻(RDSon)特性。磊晶層的摻雜濃度及厚度以及終端區之設計影響了崩潰電壓大小。然而，提高耐壓的方法大多會降低導通電阻，因此難以兼顧高崩潰電壓及低導通電阻的需求。
在目前常見的終端區設計方式之一為浮接場環(floating field ring，FFR)，然而此設計需要足夠大的終端區面積，不利於功率半導體元件之微型化。其他常見的終端區設計方式為於溝槽內填充多晶矽或氧化物以降低電場集中現象，然而此設計容易使終端區邊緣電應力集中而導致可靠度下降的問題。
有鑑於此，如何提供一種可解決上述問題之功率半導體元件仍是目前業界亟需研究的方向之一。
本揭露之一技術態樣為一種功率半導體元件。
在一實施例中，功率半導體元件包含第一電極、基底、第一磊晶層、第二磊晶層、閘極電極以及第二電極。基底位在第一電極上，基底具有主動區以及圍繞主動區的終端區。第一磊晶層位於基底上，其中第一磊晶層具有第一導電類型，第一磊晶層包含第一摻雜區以及第二摻雜區。第一摻雜區具有第一導電類型且位在終端區以及主動區中。第二摻雜區具有第二導電類型且位在終端區中。第二磊晶層位於第一磊晶層上。閘極電極位於第二磊晶層上且位在主動區中。第二電極位於第二磊晶層上且位在主動區中。
在一實施例中，第一摻雜區的摻雜濃度在5x10 17cm -3至1x10 19cm -3的範圍中。
在一實施例中，第二摻雜區的摻雜濃度在5x10 16cm -3至2x10 18cm -3的範圍中。
在一實施例中，第一摻雜區包含第一區與第二區，其中第一區位在第二區與第二摻雜區之間，且第一區的摻雜濃度大於第二區的摻雜濃度。
在一實施例中，第一磊晶層的數量為複數，且第一磊晶層的第一摻雜區的寬度隨著與第二磊晶層的距離增加而增加。
在一實施例中，第一磊晶層的數量為複數，且第一磊晶層的第一摻雜區的寬度隨著與第二磊晶層的距離增加而縮減。
在一實施例中，第一磊晶層的數量為複數，且第一磊晶層具有不同厚度。
在一實施例中，第二摻雜區中之一者的寬度與第二摻雜區中之另一者的寬度相異。
在一實施例中，第二摻雜區中之一者的深度與第二摻雜區中之另一者的深度相異。
在一實施例中，第二摻雜區中相鄰兩者間具有一間距，且第二摻雜區之間的間距中之一者與間距中的另一者相異。
在上述實施例中，藉由設置第二摻雜區於終端區中，可使第一磊晶層、第二磊晶層以及終端區的邊緣的電場下降，並提升可靠度。藉由設置第一摻雜區於主動區以及終端區中，使得第一摻雜區所在區域的電阻下降，並使功率半導體元件整體的導通電阻下降。藉由這樣的設計，可縮減功率半導體元件的終端區的面積及整體體積。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。且為了清楚起見，圖式中之層和區域的厚度可能被誇大，並且在圖式的描述中相同的元件符號表示相同的元件。
第1A圖為根據本揭露一實施例之功率半導體元件100的上視圖。第1B圖為沿著第1A圖中線段1B-1B的剖面圖。功率半導體元件100包含第一電極110、基底120、第一磊晶層130、第二磊晶層140、第二電極154以及閘極電極156。第一電極110為汲極電極，第二電極154為源極電極。基底120具有主動區AC(Active region)以及圍繞主動區AC的終端區TM(Termination region)。本實施例中的功率半導體元件100為N型(第一導電類型)元件。基底120的材料包含碳化矽(Silicon Carbide，SiC)，為N型重摻雜基板。碳化矽材料為寬能隙半導體材料，適用於高壓功率元件，本實施例以4H-SiC為例。
第一磊晶層130堆疊於基底120上。第一磊晶層130可為多層，例如本實施例以三層為例，但本揭露不以此為限。第二磊晶層140位於第一磊晶層130背對基底120的一側，亦即第二磊晶層140為上磊晶層。第一磊晶層130以及第二磊晶層140皆與基底120具有相同導電類型(N型)，且第一磊晶層130以及第二磊晶層140的摻雜濃度較基底120的摻雜濃度低。
每一第一磊晶層130包含一個第一摻雜區132以及多個第二摻雜區134。第一摻雜區132為N型摻雜區，第二摻雜區134為P型摻雜區(第二導電類型)。第一摻雜區132位在終端區TM以及主動區AC中。具體來說，第一摻雜區132是部份地位在主動區AC靠近終端區TM的一側。第二摻雜區134皆位在終端區TM中。在本實施例中，每一第一磊晶層130都具有摻雜範圍相同的第一摻雜區132與第二摻雜區134，但本揭露不以此為限。
功率半導體元件100還包含位在主動區AC中的井區150、源極區域152、井區153以及閘極氧化物層158。井區150為P型摻雜區(P-well)，源極區域152為N型摻雜區，位於井區150中。第二電極154電性連接源極區域152。井區153為P型重摻雜區(P+- well)，電性連接井區150與第二電極154。閘極電極156設置於源極區域152上方。閘極氧化物層158位在第二磊晶層140上。閘極電極156位在閘極氧化物層158上。P型的井區150與N型的源極區域152之間構成通道區。
功率半導體元件100還包含第三摻雜區160，位在第二磊晶層140與閘極氧化物層158之間，且位在終端區TM中。第三摻雜區160為P型摻雜區。當逆向偏壓施加於功率半導體元件100時，第二電極154(源極電極)為接地，第一電極110(汲極電極)為正電壓。第三摻雜區160可使電場最大值移至第二磊晶層140中。本揭露藉由設置P型的第二摻雜區134於終端區TM中的第一磊晶層130(N型)，可使第一磊晶層130、第二磊晶層140以及終端區TM的邊緣的電場下降。
舉例來說，第1B圖示例性地繪示了等電位線於第一磊晶層130以及第二磊晶層140，箭號E示例性地繪示了根據等電位線分布自第二摻雜區134指向第二磊晶層140的電力線。相鄰的第一磊晶層130之間也具有類似的電位與電場分布。由此可知，由於第二摻雜區134分布在多層第一磊晶層130中且第二摻雜區134遍及整個終端區TM，可降低第一磊晶層130、第二磊晶層140以及終端區TM的邊緣的電應力(Electrical stress)。
在傳統的終端區設計中，終端區邊緣具有較高的電應力，易導致可靠度下降。上述的終端區TM設計可避免因終端區邊緣電應力大而導致可靠度下降的問題，且可進一步降低電場。如此一來，本揭露可不需要具有大面積終端區設計，即可達到降低電場的效果。藉由這樣的設計，可縮減功率半導體元件100的終端區TM的面積及整體體積。
此外，本揭露藉由設置第一摻雜區132於主動區AC以及終端區TM中，使得第一摻雜區132所在區域的電阻下降。如第1B圖所示，經過較長路徑的電流I1的流經第一摻雜區132。電流I1與電流I2使功率半導體元件100整體的導通電阻(Drain to source resistance in on-state，RDSon)下降。在本實施例中，第一摻雜區132與通道區相隔一距離，亦即第一摻雜區132無延伸至井區150與源極區域152下方，以避免降低崩潰電壓(Breakdown voltage)而導致提早發生電壓崩潰。換句話說，藉由設置第一摻雜區132在主動區AC以及終端區TM中，並同時設置第二摻雜區134 在終端區TM中，可具有降低終端區TM電場與導通電阻、以及維持或提升崩潰電壓的技術功效。
第一摻雜區132的摻雜濃度在大約5 x10 17cm -3至1x10 19cm -3的範圍中。第二摻雜區134的摻雜濃度在大約5x10 16cm -3至2x10 18cm -3的範圍中。在一些實施例中，位在不同第一磊晶層130的第一摻雜區132的摻雜濃度可彼此相同，也可彼此不同。在一些實施例中，位在相同第一磊晶層130的第二摻雜區134的摻雜濃度可相同或不相同。位在不同第一磊晶層130的第二摻雜區134的摻雜濃度可彼此相同，也可彼此不同。舉例來說，第一摻雜區132與第二摻雜區的深度D可根據實際需求調整。第一摻雜區132與第二摻雜區134的深度D較淺時，對應的摻雜濃度可較高。第一摻雜區132與第二摻雜區的深度D較深時，對應的摻雜濃度可較低。
位於同一第一磊晶層130的第二摻雜區134中的相鄰兩者之間具有間距L1，且間距L1可任意調整。第一摻雜區132與第二摻雜區134之間的間距L2也可任意調整。
第二摻雜區134的寬度W1可彼此相同，也可彼此不同。換句話說，第一摻雜區132與第二摻雜區134的尺寸及摻雜濃度之間可互相搭配，只要可使得第一磊晶層130、第二磊晶層140以及終端區TM的邊緣的電場下降即可。
第2圖為根據本揭露另一實施例之功率半導體元件100a的剖面圖。功率半導體元件100a與第1B圖所示的功率半導體元件100大致相同，其差異在於功率半導體元件100a的第一摻雜區132a可包含第一區1322a與第二區1324a，其中第一區1322a的摻雜濃度大於第二區1324a的摻雜濃度。換句話說，較靠近通道區的第二區1324a具有較低的摻雜濃度。在其他實施例中，第二區1324a也可能延伸至井區150與源極區域152(通道區)下方，只要可使整體的導通電阻下降並維持崩潰電壓即可。功率半導體元件100a具有與功率半導體元件100相同的技術功效，於此不再贅述。
第3圖為根據本揭露又一實施例之功率半導體元件100b的剖面圖。功率半導體元件100b與第1B圖所示的功率半導體元件100大致相同，其差異在於功率半導體元件100b的第一摻雜區132b分別具有不同寬度。距離基底120越近的第一摻雜區132b的寬度越寬，亦即各個第一摻雜區132b的寬度隨著與第二磊晶層140的距離增加而增加。如第3圖所示，位在下方的第一摻雜區132具有寬度W2、位在中間的第一摻雜區132具有寬度W3、位在上方的第一摻雜區132具有寬度W4。寬度W2大於寬度W3，且寬度W3大於寬度W4。在其他實施例中，第一摻雜區132b也可具有前述第2圖所示的第一區1322a與第二區1324a之設計，亦即第一摻雜區132b也可具有不同摻雜濃度。功率半導體元件100b具有與功率半導體元件100相同的技術功效，於此不再贅述。
第4圖為根據本揭露又一實施例之功率半導體元件100c的剖面圖。功率半導體元件100c與第3圖所示的功率半導體元件100b大致相同，其差異在於距離基底120越遠的第一摻雜區132c的寬度越寬，亦即各個第一摻雜區132c的寬度隨著與第二磊晶層140的距離增加而縮減。如第4圖所示，位在下方的第一摻雜區132c的寬度W4小於位在中間的第一摻雜區132c的寬度W3，而寬度W3小於位在上方的第一摻雜區132c的寬度W2。在其他實施例中，第一摻雜區132c也可具有前述第2圖所示的第一區1322a與第二區1324a之設計，亦即第一摻雜區132c也可具有不同摻雜濃度。功率半導體元件100b具有與功率半導體元件100相同的技術功效，於此不再贅述。
在其他實施例中，位在中間的第一磊晶層130的第一摻雜區132b的寬度也可大於或小於其他的第一摻雜區132b，只要可降低功率半導體元件100c整體的導通電阻即可。
第5圖為根據本揭露又一實施例之功率半導體元件100d的剖面圖。在本實施例中，第一磊晶層130可具有不同厚度。舉例來說，位在中間的第一磊晶層130a的厚度T2較另一第一磊晶層130的厚度T1更厚。在其他實施例中，也可使每一第一磊晶層130的厚度彼此都不相同，只要可達到降低終端區TM電場的技術功效即可。
綜上所述，本揭露藉由設置第二摻雜區於終端區中，可使第一磊晶層、第二磊晶層以及終端區的邊緣的電場下降，並提升可靠度。本揭露藉由設置第一摻雜區於主動區以及終端區中，使得第一摻雜區所在區域的電阻下降，並使功率半導體元件整體的導通電阻下降。藉由這樣的設計，可縮減功率半導體元件的終端區的面積及整體體積。
100,100a,100b,100c,100d:功率半導體元件 110:第一電極 120:基底 130,130a:第一磊晶層 132,132a,132b,132c:第一摻雜區 1322a:第一區 1324a:第二區 134:第二摻雜區 140:第二磊晶層 150,153:井區 152:源極區域 154:第二電極 156:閘極電極 158:閘極氧化物層 160:第三摻雜區 AC:主動區 TM:終端區 I1,I2:電流 D:深度 L1,L2:間距 T1,T2:厚度 W1,W2,W3,W4:寬度 E:箭號 1B-1B:線段
第1A圖為根據本揭露一實施例之功率半導體元件的上視圖。 第1B圖為沿著第1A圖中線段1B-1B的剖面圖。 第2圖為根據本揭露另一實施例之功率半導體元件的剖面圖。 第3圖為根據本揭露又一實施例之功率半導體元件的剖面圖 第4圖為根據本揭露又一實施例之功率半導體元件的剖面圖。 第5圖為根據本揭露又一實施例之功率半導體元件的剖面圖。
100:功率半導體元件
110:第一電極
120:基底
130:第一磊晶層
132:第一摻雜區
134:第二摻雜區
140:第二磊晶層
150,153:井區
152:源極區域
154:第二電極
156:閘極電極
158:閘極氧化物層
160:第三摻雜區
AC:主動區
TM:終端區
I1,I2:電流
D:深度
L1,L2:間距
W1:寬度
E:箭號

Claims (10)

  1. 一種功率半導體元件，包含： 一第一電極； 一基底，位在該第一電極上，該基底具有一主動區以及圍繞該主動區的一終端區； 至少一第一磊晶層，位於該基底上，其中該第一磊晶層具有一第一導電類型，該第一磊晶層包含： 一第一摻雜區，具有該第一導電類型且位在該終端區以及該主動區中；以及 複數個第二摻雜區，具有一第二導電類型且位在該終端區中； 一第二磊晶層，位於該第一磊晶層上； 一閘極電極，位於該第二磊晶層上且位在該主動區中；以及 一第二電極，位於該第二磊晶層上且位在該主動區中。
  2. 如請求項1所述之功率半導體元件，其中該第一摻雜區的摻雜濃度在5x10 17cm -3至1x10 19cm -3的範圍中。
  3. 如請求項1所述之功率半導體元件，其中該些第二摻雜區的摻雜濃度在5x10 16cm -3至2x10 18cm -3的範圍中。
  4. 如請求項1所述之功率半導體元件，其中該第一摻雜區包含一第一區與一第二區，其中該第一區位在該第二區與該些第二摻雜區之間，且該第一區的摻雜濃度大於該第二區的摻雜濃度。
  5. 如請求項1所述之功率半導體元件，其中該第一磊晶層的數量為複數，且該些第一磊晶層的該些第一摻雜區的寬度隨著與該第二磊晶層的距離增加而增加。
  6. 如請求項1所述之功率半導體元件，其中該第一磊晶層的數量為複數，且該些第一磊晶層的該些第一摻雜區的寬度隨著與該第二磊晶層的距離增加而縮減。
  7. 如請求項1所述之功率半導體元件，其中該第一磊晶層的數量為複數，且該些第一磊晶層具有不同厚度。
  8. 如請求項1所述之功率半導體元件，其中該些第二摻雜區中之一者的寬度與該些第二摻雜區中之另一者的寬度相異。
  9. 如請求項1所述之功率半導體元件，其中該些第二摻雜區中之一者的深度與該些第二摻雜區中之另一者的深度相異。
  10. 如請求項1所述之功率半導體元件，其中該些第二摻雜區中相鄰兩者間具有一間距，且該些第二摻雜區之間的該些間距中之一者與該些間距中的另一者相異。
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