TW202324943A - Power and area efficient digital-to-time converter with improved stability and operating method thereof - Google Patents

Abstract

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

Description

Power and area efficient digital time delay converter with improved stability and method of operation thereof

Cross References to Related Applications

This application claims priority and benefit to U.S. Patent Application No. 17/111,208, filed December 3, 2020, and U.S. Patent Application No. 17/449,250, filed September 28, 2021, which are hereby incorporated by reference Its entire content is incorporated herein.

This application relates to digital time-delay converters, and more particularly to power-efficient and area-efficient digital time-delay converters that are robust to process, voltage, and temperature variations.

Fractional-N phase-locked loops (PLLs) are key building blocks for frequency synthesizers and for low-jitter clocking applications using fixed frequency or spread spectrum. To provide improved performance on phase noise and fractional spurs while achieving low power, digital delay converters (DTCs) are used in fractional-N PLLs. The DTC converts a digital code or word into a time delay, which works in the PLL as a true fractional divider with high resolution. DTCs are also fundamental building blocks for other applications, including sampling oscilloscopes, direct digital frequency synthesis (DDFS), polar transmitters, radar, phased array systems, and time-interleaved ADC timing calibration.

It is known to form DTCs using complementary metal oxide semiconductor (CMOS) delay cells. But CMOS delay cells are sensitive to process, voltage, and temperature (PVT) variations. Therefore, improved power supply noise robustness can be obtained by implementing DTC with a capacitor charging circuit. The capacitor charging circuit charges the capacitor according to the digital word, which is converted by the DTC into a time delay. A digital-to-analog converter (DAC), such as a resistive DAC (R-DAC), converts a digital word into an initial voltage (Vinit) for charging a capacitor. Then, the Vinit-charged charging capacitor is further charged with a constant current until the charging capacitor voltage reaches the threshold voltage (Vtrip). The time delay is equal to the delay from Vinit to Vtrip from charging the Vinit charged charging capacitor. But the DAC consumes power and semiconductor die area. In addition, DTC may be affected by process, voltage and temperature variations.

A circuit is provided, comprising: a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors; a first current source configured to charge the plurality of capacitors with a charging current through the common terminal; and a comparator that There is a first input terminal coupled to the common terminal.

Additionally, a method for a digital time-delay converter is provided, the method comprising: charging an array of capacitors in a capacitive digital-to-analog converter in response to a digital code to form a charged array of capacitors; in response to a timing signal, utilizing the charging Current through the common terminal further charges the charged capacitor array to develop an increased voltage for the common terminal; and determining when the increased voltage is equal to the trip voltage.

Additionally, a circuit is provided, the circuit comprising: a voltage-to-current switched capacitive converter configured to convert a reference voltage to a first current; a charging capacitor; a current mirror configured to mirror the first current is a charging current for charging the charging capacitor; and a comparator having a first input coupled to the charging capacitor and a second input configured to receive a trip voltage.

Finally, a circuit is provided that includes: a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors; a first current source configured to cause the plurality of capacitors to utilize a discharge current conducted through the common terminal; a capacitor discharge; and a comparator having a first input terminal coupled to the common terminal.

These and other advantageous features can be better understood through the following embodiments.

A digital time-delay converter (DTC) is disclosed in which a capacitive DAC (CDAC) is used as a digitally controlled voltage generator for the charging capacitor as well as the charging capacitor itself. The resulting DTC has improved power efficiency and occupies a reduced semiconductor die area compared to conventional charged capacitive DTC structures. This reduction in die space increases density because more circuitry can be integrated into the same die space due to the reduced area for digital delay converter implementation. Also disclosed is a switched capacitor voltage-to-current converter for generating charging current to a charging capacitor for improved stability with respect to process, voltage, and temperature variations.

An exemplary DTC 100 is shown in FIG. 1 . The CDAC 105 includes an array of capacitors sharing a common terminal 145 that is charged to an initial voltage Vinit in response to a digital DTC code (dtc_code). As will be explained further herein, CDAC 105 functions such that Vinit is a fraction of the DAC reference voltage (Vref_dac). The number of different parts depends on the resolution of CDAC 105 and its encoding. For example, in a 3-bit binary coded implementation, the CDAC 105 can convert the DTC code dtc_code into one of eight possible Vinit settings: 0 V, 1/8 Vref_dac, 1/4 Vref_dac, 3/8 Vref_dac, 1/2 Vref_dac, 5/8 Vref_dac, 3/4 Vref_dac and 7/8 Vref_dac.

Since the capacitors in CDAC 105 are all connected in parallel with respect to common terminal 145 after being charged to Vinit, they act as a single charging capacitor. As the capacitor in CDAC 105 charges to Vinit, an edge of a timing signal such as the input clock signal (clk_in), which may be a rising or falling edge, triggers switch S1 to close, causing a current source such as current mirror 110 to begin utilizing a constant The charging current Ichg charges the capacitor. The comparator 115 is used to compare the voltage of the common terminal 145 in the CDAC 105 with the threshold voltage Vtrip. The output signal from comparator 115 may be inverted by inverter 120 to form an output clock signal (clk_dtc_out) for DTC 100 which is asserted to the supply voltage at the end of the time delay. Therefore, the time delay from DTC 100 is equal to the delay between the trigger edge of the input clock edge and the assertion of the output clock signal. In an alternate implementation, comparator 115 may be configured such that the output clock signal has a falling edge (discharges to ground) at the end of the time delay.

Some exemplary waveforms for charging capacitors in CDAC 105 are shown in FIG. 2 . In the following discussion, the capacitors in CDAC 105 are collectively referred to as charging capacitors because they are connected in parallel about common terminal 145 during the charge redistribution phase in which the capacitors are charged to Vinit. In the first waveform 200 , the charging capacitor is charged to an initial voltage Vinit1 that is greater than the initial voltage Vinit2 for the second waveform 205 . The trigger edge of the input clock signal occurs at time t0. Both waveforms increase linearly from a constant charging current Ichg. But because Vinit1 is greater than Vinit2, waveform 200 reaches Vtrip at time t1 faster than waveform 205 reaches Vtrip at time t2. Accordingly, the time delay Δt1 of waveform 200 from time t0 to time t1 is shorter than the time delay Δt2 of waveform 205 from time t0 to time t2.

Referring again to FIG. 1 , any suitable current source may be used to charge the charging capacitor with a constant charging current Ichg when switch S1 is closed. Particularly advantageously, the current source is formed by a switched capacitor voltage-to-current converter 135 used to make the DTC 100 robust to process, voltage and temperature variations, as will be explained further herein. The switched capacitor voltage-to-current converter 135 converts the input reference voltage Vrefp into a first current I. A current source such as a current mirror 110 mirrors the first current I into a charging current Ichg that charges the charging capacitor. To generate an input reference voltage Vrefp, a current source 125 biased by a bias voltage Vbias drives a reference current Iref into a resistor. In DTC 100 , current source 125 drives reference current Iref into resistor pair R2 and R1 , but it will be appreciated that a single resistor (or more than two resistors) could be used in alternative implementations. In an alternative implementation, a voltage reference circuit with a voltage buffer may be used instead of the current source 125 to generate the input reference voltage Vrefp.

Resistors R2 and R1 are arranged in series between current source 125 and ground. Resistors R1 and R2 form a voltage divider such that the voltage divider node 140 between resistors R1 and R2 is charged to a reference voltage Vref_dac which is equal to a divided version of the input reference voltage Vrefp, depending on Resistance of R1 and R2. By properly scaling these resistors, the output voltage range of CDAC 105 can be set relative to the input reference voltage Vrefp.

In some implementations, the resistor R2 can be shorted or removed so that the reference voltage Vref_dac is equal to the input reference voltage Vrefp, so that the offset of the comparator 115 can be compensated as follows. If comparator 115 is ideal, it discharges its output signal when its negative terminal input voltage Vn is equal to Vtrip at its positive input terminal. But due to non-ideality, the comparator 115 may instead discharge its output signal when the negative terminal input voltage Vn is equal to Vtrip plus some offset voltage which may be positive or negative. To compensate for this offset voltage, auto-zero sampling switch S3, coupled between the output terminal of comparator 115 and its negative input terminal, is closed during the auto-zero phase prior to charging the charging capacitor. During the auto-zero phase, switch S2 is coupled from voltage divider node 140 through auto-zero capacitor Caz to the negative input terminal of comparator 115, switch S2 is also closed to couple reference voltage Vref_dac to the first terminal of auto-zero capacitor Vac. One terminal, the auto-zero capacitor Vac has a second terminal connected to the negative input terminal of the comparator 115 . Due to the feedback through the auto-zero switch S3 during the auto-zero phase, the auto-zero capacitor Caz will be charged with the offset voltage during the auto-zero phase. During normal operation, switches S2 and S3 are then opened. Since the auto-zero capacitor Caz is precharged to cancel the offset voltage, when the common terminal 145 is charged to the trip voltage Vtrip, the comparator 115 will discharge its output signal and The output of the toggle inverter 120 .

CDAC 105 may be formed using any suitable coding of its capacitors. An exemplary binary coded CDAC 300 is shown in more detail in FIG. 3 . The reference voltage Vref_dac flows through the switch S2 to charge the common terminal 145 of the capacitor array 305 during the initial charging phase. CDAC 300 responds to a three-bit wide digit code dtc_code such that the capacitor array has four capacitors, including capacitor 4C, capacitor 2C, capacitor 1C, and a second (or dummy) capacitor 1C'. As the name implies, there is a binary progression to the capacitance of the capacitors such that capacitor 4C has twice the capacitance of capacitor 2C which in turn has twice the capacitance of each of the 1C/1C' capacitors. Each capacitor has a first plate coupled to a common terminal 145 or ground through a corresponding single pole double throw switch (SPDT). For example, capacitor 4C has a first plate coupled to SPDT switch S4, capacitor 2C has a first plate coupled to SPDT switch S5, capacitor 1C has a first plate coupled to SPDT switch S6, and capacitor 1C' has a first plate coupled to SPDT switch S6. The first board of S7. During the initial charging phase, the bottom switch S8 coupled between the second plate for each capacitor and ground is closed. The setting of each SPDT switch during the initial charge phase depends on the DTC code. As previously discussed, the three-bit DTC code corresponds to, for example, 8 different values of Vinit ranging from 0 V to 7/8 Vref_dac. For a 0 V setting, each SPDT switch selects ground instead of common terminal 145 . But as DTC codes increase, more and more SPDT switches choose the common terminal 145 instead of ground to charge their respective capacitors with the DAC reference voltage Vref_dac. For example, the maximum value of the three-digit DTC code can cause switches S4, S5, and S6 to select a common terminal, and switch S7 to select ground. In this case, capacitors S4, S5 and S6 are all charged to the DAC reference voltage during the initial charging phase.

With the appropriate capacitors charged in the initial charge phase in response to the DTC code, the charge redistribution phase occurs. The charge redistribution phase begins by opening bottom switch S8. This advantageously prevents the charge on the capacitors in capacitor array 305 from changing during the charge redistribution phase because the second plate for each capacitor is floating. More generally, the ground line can be replaced by a constant voltage source such that the bottom switch S8 is coupled between the second plate of each capacitor and the constant voltage source. It should be understood that switch S8 may be replaced by a plurality of switches S8 in alternative implementations. With bottom switch S8 open, switch S2 is also open to isolate the common terminal from the DAC reference voltage Vref at divider node 140 . All SPDT switches are then configured to select common terminal 145 such that the first plate for each capacitor is connected to common terminal 145 . Thus, the charge on the first plate is redistributed from those capacitors that were charged during the initial charging phase to those capacitors that were grounded during the initial charging phase. Note that the switching of the SPDT switches may be interleaved or asynchronous due to non-idealities, but since the bottom switch S8 is open, no charge injection occurs, due to the floating of the second plate for each capacitor, the bottom switch S8" lock" the total charge on all capacitors. The reallocation phase is then completed by closing the bottom switch S8. Common terminal 145 is then charged to Vinit so that the input clock can be asserted to trigger charging of the Vinit-charged charging capacitor through the closure of switch S1.

FIG. 4 shows an exemplary switched capacitive voltage-to-current converter 135 with a current mirror 110 . The differential amplifier 405 with the feedback capacitor C3 coupled between the output of the differential amplifier 405 and its negative input terminal forms an error integrator that integrates the difference between the input reference voltage Vrefp and its negative input terminal voltage . In one implementation, amplifier 405 drives the gate of NMOS transistor M4, the source of which is connected to the degeneration resistor Rdg (or ground in other implementations), and the drain of which is connected to the diode connection The drain and gate of the PMOS transistor M3. Transistor M3 and current mirror PMOS transistor M2 form a current mirror. Similarly, transistor M3 together with current mirror PMOS transistor M1 forms a current mirror 110 . The sources of transistors M1 , M2 and M3 are connected to the supply terminals for the supply voltage. The gates of transistors M1 and M2 are connected to the gate of diode-connected transistor M3. When amplifier 405 causes transistor M4 to conduct current, the current is thus mirrored through transistors M3 and M1 to form a first current I, which is mirrored by current mirror 110 to form a charging current Ichg. The size of the transistor M1 is determined relative to the transistor M2 so that the charging current Ichg is K times the first current I. In one implementation, the drain of transistor M2 is coupled to the first plate of capacitor C1 through switch S11 and is also coupled to ground through switch S9. The second plate of capacitor C1 is grounded. The first plate of capacitor C1 is also connected to ground through switch S10. Furthermore, the first plate of capacitor C1 is coupled to the first plate of capacitor C2 through switch S12. The second plate of capacitor C2 is grounded. A first plate of capacitor C2 is coupled to the negative input terminal of amplifier 405 through switch S13.

A clock source such as a crystal oscillator (not shown) generates clock signals for controlling the switches S9 , S10 , S11 , S12 and S13 . The clock signal oscillates between two phases at frequency F _CLK . For example, the first phase φ1 of the clock signal may correspond to when the clock signal is charged to the supply voltage, and the second phase φ2 may correspond to when the clock signal is discharged, although both phases may be used in alternative implementations. for the opposite. When the clock signal is in phase φ1, the switches S11 and S12 are closed. During phase φ1, current I charges capacitors C1 and C2 through closed switches S11 and S12. Switches S9, S10 and S13 are open during phase φ1. In phase φ2, switches S9, S10 and S13 are closed, and switches S11 and S12 are open. In phase φ2, the charge on capacitor C2 drives the negative input terminal on amplifier 405 . Capacitor C1 is discharged during phase φ2, and first current I is discharged to ground through closed switch S9. Given this clocking of the switches, it can be shown that the first current I is equal to 2*F _CLK *Vrefp*C1. The current mirror transistor M1 mirrors the first current I, so that the charging current Ichg is equal to the proportional constant K multiplied by the first current I. Therefore, the charging current Ichg is equal to K*2*F _CLK *Vrefp*C1. To show that this relationship for charge current Ichg is quite beneficial in reducing process, voltage and temperature variations for the timing delays from the DTCs disclosed herein, consider that the maximum timing delays for the DTCs disclosed herein can be Expressed as C _DAC * (Vtrip/Ichg), where C _DAC is the capacitance of the CDAC capacitor array (capacitance of the charging capacitor). If Vtrip and Vrefp are equal as before, then the maximum delay can be expressed as (1/K)*(1/F _CLK )*(C _DAC /C1). These factors are easily and precisely controlled in an integrated circuit including DTC 100 compared to conventional DTCs that rely on the precision of resistors or capacitors.

Mismatch errors among transistors M1 , M2 and M3 can be improved by switching matrix 410 using dynamic element matching (DEM) techniques. Switching matrix 410 dynamically switches the drain connections of transistors M1 , M2 and M3 such that the roles of transistors M1 , M2 and M3 are dynamically swapped while the relative mirror ratio between them remains unchanged. For example, in the first configuration of the switch matrix 410, the drain of the transistor M3 is connected to the drain of the transistor M4, as shown in FIG. 4 . But in the second configuration of the switch matrix 410, the drain of the transistor M3 is connected to the switch S11 instead. In this second configuration, the drain of current mirror transistor M2 can then be connected to the drain of transistor M4 through switching matrix 410 . Similarly, the drain of current mirror transistor M1 is normally coupled to switch S1 (FIG. 1), but is dynamically switched by switch matrix 410 to alternatively connect to switch S11 or the drain of transistor M4 in other switching configurations. pole. The resulting switching of the current mirror elements can be triggered in phase φ2 without affecting the capacitor charging operation.

Referring again to FIG. 4 , the offset of amplifier 405 can be removed by an auto-zero technique similar to that discussed with respect to comparator 115 . During clock phase φ1, the switch Saz1 connected between the negative input of the amplifier 405 and the output of the amplifier 405, and the switch Saz2 connected between the node for the reference voltage Vrefp and the first plate of the auto-zero capacitor Caz1 closure. The second plate of auto-zero capacitor Caz2 is connected to the negative input of amplifier 405 . The auto-zero switch Saz3 connected between capacitor C3 and the negative input of amplifier 405 is turned off during clock phase φ1 to maintain the charge stored on capacitor C3. The offset voltage for amplifier 405 is thus sampled on auto-zero capacitor Caz1 during clock phase φ2. In phase φ2, switches Saz1 and Saz2 are open and switch Saz3 is closed, so that the offset at amplifier 405 is canceled by precharged capacitor Caz1. When the error signal from capacitor C2 is forwarded by closing switch S13 during clock phase φ2, switch Saz3 is also closed to form an integrator with amplifier 405 and capacitor C3. Therefore, the use of the switched capacitor voltage-to-current converter 135 in the generation of the charging current Ichg is very advantageous in ensuring that the timing delays generated by the DTC are robust to process, voltage and temperature variations.

Turning now to FIG. 5 , an exemplary DTC 500 is shown in which switched capacitive voltage-to-current converter 135 and current mirror 110 are used to generate charging current Ichg as discussed with respect to DTC 100 . In DTC 500 , charging capacitor 505 is not integrated into the CDAC, but is charged separately with an initial voltage Vinit as set by DAC 510 . The remaining components of DTC 500 function as discussed with respect to DTC 100 . DTC 500 breaks down into DTC 100 if a single CDAC is used to form charging capacitor 505 and DAC 510 . However, even without using the power and die space savings offered by CDACs, DTC 500 is robust to process, voltage and temperature variations due to the use of switched capacitive voltage-to-current converter 135 to generate charge current Ichg.

An exemplary method of operation for a DTC containing a CDAC will now be discussed with reference to the flowchart of FIG. 6 . The method includes act 600 of charging an array of capacitors in a capacitive DAC to form a charged array of capacitors in response to a digital code. As an example of act 600, the common terminal 145 for the capacitor array is charged to an initial voltage Vinit. Additionally, the method includes act 605 , occurring in response to an edge of the timing signal, and comprising further charging the charged array of capacitors through the common terminal with a charging current to form an increased voltage for the common terminal. As an example of act 605, the CDAC capacitor is charged through common terminal 145 after the trigger edge of the input clock signal. Finally, the method includes an action 610 of deciding when the increased voltage is equal to the trip voltage. The comparison in comparator 115 is an example of act 610 .

A DTC as disclosed herein may be advantageously incorporated into any suitable mobile device or electronic system. For example, as shown in FIG. 7 , a cellular phone 700, a laptop computer 705, and a tablet PC 710 may all include a DTC in accordance with the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured with DTCs constructed in accordance with the present disclosure.

Referring again to DTC 100, in an alternate implementation where the charge capacitor formed by CDAC 105 is discharged rather than charged during the time delay, the same advantageous density and power enhancements and robustness to process, voltage and temperature variations can be provided . An exemplary discharge DTC 800 is shown in FIG. 8 . The CDAC 105 operates as discussed with respect to the DTC 100 to convert the digital code to the initial voltage Vinit stored by the CDAC capacitor relative to the common terminal 145 during the reallocation phase for the CDAC 105 . The current mirror 810 mirrors the first current from the switched capacitive voltage-to-current converter 805 to form a discharge current Idischarge. Current mirror 810 is connected to common terminal 145 through switch S1, similar to that discussed for DTC 100, so that when switch S1 closes in response to the trigger clock signal edge to initiate the time delay, voltage Vinit increases by CDAC with discharge current Idischarge. The capacitor discharges and begins to discharge.

Comparator 815 also operates similarly to that discussed with respect to comparator 115 to determine when initial voltage Vinit has decreased to equal trip voltage Vtrip1. However, although the trip voltage Vtrip for the DTC 100 is greater than the initial voltage Vinit, the trip voltage Vtrip1 is less than the initial voltage Vinit. Since the output of comparator 815 (clk_dtc_out) will go high at the end of the time delay when the CDAC capacitor has discharged below trip voltage Vtrip1, an inverter equivalent to inverter 120 in DTC 800 is not required. The rest of DTC 800 functions as discussed with respect to DTC 100 .

It should be understood that many modifications, substitutions and variations are possible in the materials, implement, configuration and method of use of the devices of the present disclosure without departing from the scope of the present disclosure. For this reason, the scope of the present disclosure should not be limited to the specific implementations shown and described herein, as they are by way of some examples only, and should be compared with the claims and their functions attached below. The category of equals is perfectly commensurate.

100, 500: Digital Time Delay Converter (DTC) 105, 300: capacitive digital-to-analog converter (CDAC) 110: current mirror 115: Comparator 120: Inverter 125: Current source 135:Switched capacitive voltage-to-current converter 140:Voltage divider node 145: common terminal Caz: Auto-Zero Capacitor Ichg: charging current Iref: reference current Vbias: bias voltage Vinit: initial voltage Vn: Negative terminal input voltage Vref_dac: DAC reference voltage Vrefp: input reference voltage Vtrip: trip voltage 200: the first waveform 205: Second waveform 305: capacitor array 405: Amplifier 410: switch matrix Rdg: negative feedback resistor 505: charging capacitor 510:DAC 600, 605, 610: action 700: cellular phone 705: Laptop 710: Tablet PC 800: Discharge DTC 805:Switched Capacitor Voltage-Current Converter 810: current mirror 815: comparator

1 is a diagram of an exemplary DTC in which a capacitive DAC (CDAC) is used as a charging capacitor that is charged during the time delay, according to aspects of the present disclosure.

FIG. 2 depicts some exemplary voltage waveforms for charging the charging capacitor in the DCT of FIG. 1 .

3 is a circuit diagram of a binary weighted CDAC for DTC according to aspects of the disclosure.

4 is a circuit diagram of a switched capacitive voltage-to-current converter and a current mirror in accordance with aspects of the present disclosure.

5 is a diagram of an exemplary DTC in which a switched capacitive voltage-to-current converter functions to generate a charging current for charging a capacitor, according to aspects of the present disclosure.

6 is a flowchart of an exemplary method of operation for a DTC in accordance with aspects of the present disclosure.

7 depicts some exemplary electronic systems each incorporating a DTC in accordance with aspects of the present disclosure.

8 is a diagram of an exemplary DTC in which a CDAC is used as a charging capacitor that is discharged during a time delay, according to aspects of the present disclosure.

The practice of the present disclosure and its advantages are best understood by reference to the following embodiments. It should be understood that like symbols are used to identify like elements depicted in one or more of the drawings.

100: Digital Time Delay Converter (DTC)

105: Capacitive digital-to-analog converter (CDAC)

110: current mirror

115: Comparator

120: Inverter

125: Current source

135:Switched capacitive voltage-to-current converter

140:Voltage divider node

145: common terminal

Caz: Auto-Zero Capacitor

Ichg: charging current

Iref: reference current

Vbias: bias voltage

Vinit: initial voltage

Vn: Negative terminal input voltage

Vref_dac: DAC reference voltage

Vrefp: input reference voltage

Vtrip: trip voltage

Claims (20)

A digital delay converter circuit, comprising: Charging capacitors, including common terminals; a switched capacitor voltage-to-current converter configured to convert the reference voltage to a first current; a current mirror configured to convert the first current to a second current and provide the second current to the charging capacitor through the common terminal; and A comparator has a first input terminal coupled to the common terminal. The circuit of claim 1, wherein the current mirror includes: A first switch, coupled between the current mirror and the common terminal, is configured to close in response to a timing signal. The circuit of claim 2, wherein the switched capacitive voltage-to-current converter includes: a first transistor; and an error amplifier having an output terminal coupled to the gate of the first transistor, wherein the current mirror includes a diode-connected transistor in series with the first transistor and a second transistor having a connection To this diode connect the gate of the gate of the transistor. The circuit of claim 3, wherein the first switch is coupled between the common terminal and the second transistor. The circuit of claim 3, wherein the switched capacitor voltage-to-current converter further comprises: The negative feedback resistor is coupled between the ground line and the source of the first transistor. The circuit of claim 3, wherein the switched capacitor voltage-to-current converter further comprises: An auto-zero switch is coupled between the output terminal of the error amplifier and the input terminal of the error amplifier. Such as the circuit of claim 3, further comprising: at least one resistor; and A current source configured to drive the at least one resistor with a reference current to generate the reference voltage. The circuit of claim 7, wherein the at least one resistor comprises a voltage divider. The circuit of claim 8, wherein the charging capacitor comprises a capacitive digital-to-analog converter. The circuit of claim 9, wherein the voltage divider comprises a first resistor coupled to a second resistor through a node, the circuit further comprising: A second switch is coupled between the node and the capacitive digital-to-analog converter. A method of operation for a digital time delay converter comprising: Responding to the digital code, charging the charging capacitor with the initial voltage; converting the reference voltage to a first current in a switched capacitor voltage-to-current converter; mirroring the first current as a charging current; After the charging capacitor is charged to the initial voltage, charging the charging capacitor with the charging current; and During charging of the charging capacitor with the charging current, it is determined when the voltage of the charging capacitor is equal to the trip voltage. The method of claim 11, further comprising: In response to the timing signal, charging the charging capacitor with the charging current is initiated. The method of claim 12, wherein the timing signal is a clock signal, and wherein initiating charging the charging capacitor with the charging current is in response to a clock edge of the clock signal. The method of claim 12, further comprising: In response to the timing signal, a first switch is closed to couple the charging capacitor to the charging current. The method of claim 12, wherein during charging the charging capacitor with the charging current, determining when the voltage of the charging capacitor is equal to the trip voltage is performed in a comparator having an auto-zero capacitor coupled to The input terminal of the charging capacitor, the method further comprising: The auto-zero capacitor is charged to cancel the offset of the comparator before determining when the voltage of the charging capacitor is equal to the trip voltage. A digital delay converter circuit, comprising: The capacitive digital-to-analog converter includes a plurality of capacitors and a plurality of first switches corresponding to the plurality of capacitors, each of the plurality of first switches is coupled between a common terminal and each of the plurality of capacitors between capacitors; second switch; a current source coupled to the common terminal through the second switch; and A comparator has a first input terminal coupled to the common terminal. The circuit of claim 16, wherein each first switch is a single pole double throw switch. Such as the circuit of claim 16, further comprising: A third switch coupled between ground and each capacitor of the plurality of capacitors. Such as the circuit of claim 16, further comprising: Inverter configured to invert the output signal from the comparator. Such as the circuit of claim 16, further comprising: An auto-zero capacitor is coupled between the common terminal and the first input terminal.

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