CN116325506A

CN116325506A - Power and area efficient digital-to-time converter with improved stability

Info

Publication number: CN116325506A
Application number: CN202180070908.8A
Authority: CN
Inventors: 吴争争; 宋超; K·纳加拉简
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2020-12-03
Filing date: 2021-11-18
Publication date: 2023-06-23
Also published as: KR20230084318A; TW202230996A; WO2022119722A2; TWI797839B; EP4256708A2; TW202324943A; JP2023543337A; WO2022119722A3

Abstract

Digital time-to-digital converters (DTCs) convert digital codes to time delays using capacitor digital-to-analog converters (CDACs) that act as charging capacitors. The DTC includes a switched capacitor voltage-to-current converter for forming a charging current (or discharging current) for charging (or discharging) the charging capacitor in response to a trigger clock edge for a start time delay. The comparator compares the voltage on the charging capacitor with a threshold voltage to determine the end of the time delay.

Description

Power and area efficient digital-to-time converter with improved stability

Cross Reference to Related Applications

The present application claims priority and benefit from U.S. patent application Ser. No. 17/111,208, filed on 3/12/2020, and U.S. patent application Ser. No. 17/449,250, filed on 28/9/2021, which are incorporated herein by reference in their entireties.

Technical Field

The present application relates to digital-to-time converters, and more particularly to power-efficient and area-efficient digital-to-time converters that are robust to process, voltage, and temperature variations.

Background

Fractional frequency Phase Locked Loops (PLLs) are key building blocks for frequency synthesizers and low jitter clock applications using fixed frequency or spread spectrum. In order to provide improved phase noise and fractional spur performance while achieving low power, digital-to-time converters (DTCs) are used in fractional frequency PLL. DTCs convert digital codes or words into time delays, which are used in PLLs as true fractional dividers with high resolution. DTCs are also basic building blocks suitable for other applications, including sampling oscilloscopes, direct Digital Frequency Synthesis (DDFS), polar transmitters, radar, phased array systems, and time interleaved ADC timing calibration.

It is known to use Complementary Metal Oxide Semiconductor (CMOS) delay cells to form the DTCs. CMOS delay cells are sensitive to process, voltage and temperature (PVT) variations. Thus, by implementing the DTC with a capacitor charging circuit, improved power supply noise robustness may be obtained. The capacitor charging circuit charges the capacitor according to the digital word converted to a time delay by the DTC. A digital-to-analog converter (DAC), such as a resistive DAC (R-DAC), converts the digital word into an initial voltage (Vinit) that charges the capacitor. The charge capacitor charged by Vinit is then further charged with a constant current until the charge capacitor voltage reaches a threshold voltage (Vtrip). The time delay is equal to the delay in charging the Vinit-charged charging capacitor from Vinit to Vtrip. But the DAC consumes power and semiconductor die area. Additionally, DTCs may be affected by process, voltage and temperature variations.

Disclosure of Invention

There is provided a circuit comprising: a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors; a first current source configured to charge a plurality of capacitors through a common terminal with a charging current; and a comparator having a first input terminal coupled to the common terminal.

Additionally, there is also provided a method for a digital-to-time converter, the method comprising: charging a capacitor array in a capacitive digital-to-analog converter in response to the digital code to form a charged capacitor array; in response to the timing signal, further charging the charged capacitor array with a charging current through the common terminal to form an increased voltage of the common terminal; and determining when the increased voltage is equal to the trip voltage.

Further, a circuit is provided, the circuit comprising: a voltage-to-current switched capacitor converter configured to convert a reference voltage to a first current; charging a capacitor; a current mirror configured to mirror the first current as a charging current for charging the charging capacitor; and a comparator having a first input coupled to the charging capacitor and a second input configured to receive the trip voltage.

Finally, a circuit is provided, the circuit comprising: a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors; a first current source configured to discharge the plurality of capacitors with a discharge current conducted through the common terminal; and a comparator having a first input terminal coupled to the common terminal.

These and other advantageous features will be better understood from the detailed description that follows.

Drawings

Fig. 1 is a diagram of an example DTC in which a Capacitive DAC (CDAC) is used as a charging capacitor that is charged during a time delay, according to one aspect of the present disclosure.

Fig. 2 illustrates some example voltage waveforms for charging a charging capacitor in the DCT of fig. 1.

Fig. 3 is a circuit diagram of a binary weighted CDAC for DTCs according to one aspect of the present disclosure.

Fig. 4 is a circuit diagram of a switched capacitor voltage-to-current converter and current mirror according to one aspect of the present disclosure.

Fig. 5 is a diagram of an example DTC in which switched capacitor voltage-current is used to generate a charging current for charging a capacitor, according to one aspect of the present disclosure.

Fig. 6 is a flow chart of an example method of operation of a DTC according to one aspect of the present disclosure.

Fig. 7 illustrates some example electronic systems each containing a DTC in accordance with an aspect of the disclosure.

Fig. 8 is a diagram of an example DTC in which the CDAC is used as a charging capacitor that is discharged during a time delay, according to one aspect of the present disclosure.

Implementations of the present disclosure and its advantages may be better understood by reference to the detailed description that follows. It should be appreciated that like reference numerals are used to identify one or more of the like elements illustrated in the figures.

Detailed Description

Digital time-to-converter (DTC) is disclosed, wherein a Capacitor DAC (CDAC) is used as a digitally controlled voltage generator for the charging capacitor as well as the charging capacitor itself. The resulting DTC has improved power efficiency and occupies a reduced semiconductor die area compared to conventional charged capacitor DTC architectures. This reduction in die space improves density because more circuitry can be integrated into the same die space due to the reduced area of the digital-to-time converter implementation. A switched capacitor voltage-to-current converter is also disclosed for generating a charging current to a charging capacitor to improve stability in terms of process, voltage and temperature variations.

An example DTC 100 is shown in fig. 1. The CDAC 105 includes an array of capacitors sharing a common terminal 145 that are charged to an initial voltage Vinit in response to a digital DTC code (dtc_code). As will be further explained herein, CDAC 105 is used such that Vinit is a fraction of the DAC reference voltage (vref_dac). The number of different scores is related to the resolution of the CDAC 105 and its encoding. For example, in a 3-bit binary coded implementation, the CDAC 105 may convert the DTC code dtc_code to one of eight possible settings for Vinit: 0V, 1/8Vref_dac, 1/4Vref_dac, 3/8Vref_dac, 1/2Vref_dac, 5/8Vref_dac, 3/4Vref_dac and 7/8Vref_dac.

Since the capacitors in the CDAC 105 are all connected in parallel with respect to the common terminal 145 after being charged to Vinit, they act as a single charging capacitor. In the case where the capacitor in CDAC 105 is charged to Vinit, an edge (which may be a rising or falling edge) of a timing signal, such as an input clock signal (clk in), triggers switch S1 to close, causing a current source, such as current mirror 110, to begin charging the capacitor with a constant charging current Ichg. The comparator 115 is used to compare the common terminal voltage in the CDAC 105 with the threshold voltage Vtrip. The output signal from the comparator 115 may be inverted by an inverter 120 to form an output clock signal (clk_dtc_out) for the DTC 100, which is asserted as the supply voltage at the end of the time delay. The time delay from DTC 100 is thus equal to the delay between the trigger edge of the input clock edge and the assertion of the output clock signal. In alternative implementations, the comparator 115 may be configured such that the output clock signal has a falling edge (discharges to ground) at the end of the time delay.

Some example waveforms for capacitor charging in the CDAC 105 are shown in fig. 2. In the following discussion, the capacitors in CDAC 105 are collectively referred to as charging capacitors because they are connected in parallel with respect to common terminal 145 during the charge redistribution phase where the capacitors are charged to Vinit. In the first waveform 200, the charge capacitor is charged to an initial voltage Vinit1, the initial voltage Vinit1 being greater than the initial voltage Vinit2 of the second waveform 205. The trigger edge of the input clock signal occurs at time t 0. Both waveforms increase linearly from the constant charge current Ichg. However, since Vinit1 is greater than Vinit2, waveform 200 reaches vttrip at time t1, time t1 being earlier than time t2 when waveform 205 reaches vttrip. The time delay Δt1 from time t0 to time t1 for waveform 200 is shorter than the time delay Δt2 from time t0 to time t2 for waveform 205.

Referring again to fig. 1, when switch S1 is closed, the charging capacitor may be charged with a constant charging current Ichg using any suitable current source. A particularly advantageous current source is formed by a switched capacitor voltage-to-current converter 135, which, as will be explained further herein, is used to make the DTC 100 robust to process, voltage and temperature variations. The switched capacitor voltage-to-current converter 135 converts the input reference voltage Vrefp into a first current I. A current source such as current mirror 110 mirrors the first current I as a charging current Ichg that charges a charging capacitor. To generate the input reference voltage Vrefp, a current source 125 biased by a bias voltage Vbias drives a reference current Iref into the resistor. In DTC 100, current source 125 drives reference current Iref into a pair of resistors R2 and R1, but it should be understood that a single resistor (or more than two resistors) may be used in alternative implementations. In alternative implementations, a voltage reference circuit with a voltage buffer may be used in place of current source 125 to generate the input reference voltage Vrefp.

Resistors R2 and R1 are arranged in series between the current source 125 and ground. The resistors R1 and R2 form a voltage divider such that the voltage divider node 140 between the resistor R1 and the resistor R2 is charged to a reference voltage vref_dac, which is equal to a divided version of the input reference voltage Vrefp, depending on the resistance of the resistors R1 and R2. By properly adjusting these resistances, the output voltage range of the CDAC 105 can be set relative to the input reference voltage Vrefp.

In some implementations, resistor R2 may be shorted or removed so that reference voltage vref_dac is equal to input reference voltage Vefp, so that the offset of comparator 115 may be compensated for as follows. If the comparator 115 is perfect, it will release its output signal when its negative side input voltage Vn is equal to vttrip at its positive input terminal. However, due to non-idealities, the comparator 115 may instead release its output signal when the negative terminal input voltage Vn is equal to Vtrip plus some offset voltage that may be positive or negative. To compensate for this offset voltage, during an auto-zero phase prior to charging the charging capacitor, an auto-zero sampling switch S3 coupled between the output of comparator 115 and its negative input terminal is closed. During the auto-zero phase, switch S2, which is coupled from voltage divider node 140 through auto-zero capacitor Caz to the negative input terminal of comparator 115, is also closed to couple reference voltage vref_dac to the first terminal of auto-zero capacitor Vac, which has a second terminal connected to the negative input terminal of comparator 115. Due to the feedback through the auto-zero switch S3 during the auto-zero phase, the auto-zero capacitor Caz will be charged with the offset voltage during the auto-zero phase. During normal operation, switches S2 and S3 are then opened. Since auto-zero capacitor Caz is precharged to offset the offset voltage, when common terminal 145 is charged to the trip voltage Vtrip, comparator 115 will release its output signal and trigger the output of inverter 120, regardless of the offset voltage of comparator 115.

The CDAC 100 may be formed using any suitable encoding of its capacitors. An example binary-coded CDAC 300 is shown in more detail in FIG. 3. The reference voltage vref_dac flows through switch S2 during the initial charging phase to charge the common terminal 145 of the capacitor array 305. The CDAC 300 is responsive to a three-bit wide digital code dtc_code such that the capacitor array has four capacitors, including capacitor 4C, capacitor 2C, capacitor 1C, and a second (or virtual) capacitor 1C'. As the name implies, there is a binary progression of the capacitance of the capacitor, such that the capacitance of capacitor 4C is twice that of capacitor 2C, and the capacitance of capacitor 2C is twice that of each 1C/1C' capacitor. Each capacitor has a first plate coupled to a common terminal 145 or ground through a corresponding single pole double throw Switch (SPDT). For example, capacitor 4C has a first plate coupled to SPDT switch S4, capacitor 2C has a first plate coupled to SPDT switch S5, capacitor 1C has a first plate coupled to SPDT switch S6, and capacitor 1C' has a first plate coupled to SPDT switch S7. During the initial charging phase, a bottom switch S8 coupled between the second plate of each capacitor and ground is closed. The setting of each SPDT switch during the initial charging phase is associated with a DTC code. As previously described, the three bit DTC code corresponds to eight different values of Vinit ranging from, for example, 0V to 7/8vref_dac. For a 0V setting, each SPDT switch selects ground instead of the common terminal 145. But as the DTC code increases, more and more SPDT switches select the common terminal 145 instead of ground to charge their respective capacitors with the DAC reference voltage vref_dac. For example, the maximum value of the three-bit DTC code may result in switches S4, S5, and S6 selecting the common terminal, while switch S7 selects ground. In this case, capacitors S4, S5 and S6 are all charged to the DAC reference voltage during the initial charging phase.

In response to the DTC code, a charge redistribution phase occurs with the appropriate capacitor charged during the initial charge phase. The charge redistribution phase begins by opening the bottom switch S8. This advantageously prevents the charge on the capacitors in the capacitor array 305 from changing during the charge redistribution phase, as the second plate of each capacitor floats. More generally, the ground may be replaced by a constant voltage source such that the bottom switch S8 is coupled between the second plate of each capacitor and the constant voltage source. It should be appreciated that in alternative implementations, the switch S8 may be replaced by a plurality of switches S8. With the bottom switch S8 open, switch S2 is also open to isolate the common terminal from the DAC reference voltage Vref at the voltage divider node 140. Then, all SPDT switches are configured to select the common terminal 145 such that the first plate of each capacitor is connected to the common terminal 145. The charge on the first plate is thus redistributed from those capacitors charged during the initial charge phase to those capacitors grounded during the initial charge phase. Note that the switching of SPDT switches may be staggered or asynchronous due to non-idealities, but no charge injection occurs due to the opening of the bottom switch S8, which "locks" the total charge on all capacitors due to the floating of the second plate of each capacitor. The reassignment phase is then completed by closing the bottom switch S8. The common terminal 145 is then charged to Vinit so that the input clock can be asserted (also referred to as "activated") to trigger the charging of the charging capacitor charged by Vinit by closing switch S1.

An example switched capacitor voltage-to-current converter 135 with a current mirror 110 is shown in fig. 4. The differential amplifier 405 forms an error integrator together with a feedback capacitor C3 coupled between the output of the differential amplifier 405 and its negative input terminal, the error integrator integrating the difference between the input reference voltage Vrefp and its negative input terminal voltage. The amplifier 405 drives the gate of the NMOS transistor M4, the source of the NMOS transistor M4 being connected to the degeneration resistor Rdg (or ground in other implementations) and the drain thereof being connected to the drain and gate of the diode-connected PMOS transistor M3. The transistor M3 forms a current mirror together with the current mirror PMOS transistor M2. Similarly, transistor M3 forms current mirror 110 with current mirror PMOS transistor M1. The sources of the transistors M1, M2, and M3 are connected to a power supply terminal of a power supply voltage. The gates of transistors M1 and M2 are connected to the gate of diode-connected transistor M3. When amplifier 405 causes transistor M4 to conduct a current, the current is thus mirrored through transistors M3 and M1 to form a first current I, which is mirrored by current mirror 110 to form charging current Ichg. Transistor M1 is sized relative to transistor M2 such that charging current Ichg is K times the first current I. The drain of transistor M1 is coupled to the first plate of capacitor C1 through switch S11 and is also coupled to ground through switch S9. The second plate of capacitor C1 is grounded. The first plate of capacitor C1 is also coupled to ground through switch S10. Additionally, a first plate of capacitor C1 is coupled to a first plate of capacitor C2 through switch S12. The second plate of the capacitor C2 is connected to ground. A first plate of capacitor C2 is coupled to the negative input terminal of amplifier 405 through switch S13.

A clock source such as a crystal oscillator (not shown) generates a clock signal to control the switches S9, S10, S11, S12, and S13. The clock signal having a frequency F _CLK Oscillating between two phases. For example, a first phase of a clock signal

Can correspond to the case where the clock signal is charged to the supply voltage, and the second phase +.>

May correspond to the case where the clock signal is discharged, but in alternative implementations the two phases may be opposite. When the clock signal is in phase->

When the switches S11 and S12 are closed. In the phase->

During this time, the current I charges the capacitors C1 and C2 through the closed switches S11 and S12. In the phase->

During this time, the switches S9, S10 and S13 are turned off. In the phase->

In (3), switches S9, S10 and S13 are closed, and switches S11 and S12 are open. In phase position

The charge on capacitor C2 drives the negative input terminal on amplifier 405. Capacitor C1 is in phase->

During which it is discharged and the first current I is discharged to ground through the closed switch S9. Given the clock of the switch, it can be shown that the first current I is equal to 2*F _CLK * Vrefp×c1. The current mirror transistor M1 mirrors the first current I such that the charging current Ichg is equal to K times the proportionality constant of the first current I. The charging current Ichk is thus equal to K2*F _CLK * Vrefp×c1. To illustrate that this relationship of charging current Ichg is very advantageous for reducing process, voltage and temperature variations from the DTCs disclosed herein, it is contemplated that the maximum timing delay of the DTCs disclosed herein may be expressed asC _DAC * (Vtrip/Ichg), wherein C _DAC Is the capacitance of the CDAC capacitor array (the capacitance of the charging capacitor). If Vtrip and Vrefp are equal as previously described, the maximum delay can be expressed as (1/K) ×1/F _CLK )*(C _DAC C1). These factors are easily and precisely controlled in an integrated circuit including DTC 100, as compared to conventional DTCs that rely on resistor or capacitor accuracy.

By switching matrix 410 using Dynamic Element Matching (DEM) techniques, mismatch errors between transistors M1, M2, and M3 can be improved. The switching matrix 410 dynamically switches the drain connections of transistors M1, M2, and M3 such that the roles of transistors M1, and M3 are dynamically swapped while the relative mirror ratio between them remains unchanged. For example, in a first configuration of the switching matrix 410, as shown in fig. 4, the drain of transistor M3 is connected to the drain of transistor M4. But in the second configuration of the switching matrix 410 the drain of transistor M3 is instead connected to switch S11. In this second configuration, the drain of current mirror transistor M2 may then be connected to the drain of transistor M4 through switching matrix 410. Similarly, the drain of current mirror transistor M1 is typically coupled to switch S1 (FIG. 1), but is dynamically switched by switching matrix 410 to be alternatively connected to the drain of switch S11 or transistor M4 in other switching configurations. The resulting switching of the current mirror element can be triggered in phase phi 2 without affecting the capacitor charging operation.

Referring again to fig. 4, the offset of amplifier 405 may be removed by auto-zero techniques similar to those discussed with respect to comparator 115. In clock phase

During this time, the switch Saz1 connected between the negative input of the amplifier 405 and the output of the amplifier 405 and the switch Saz2 connected between the node of the reference voltage Vrefp and the first plate of the auto-zero capacitor Caz1 are closed. The second plate of auto-zero capacitor Caz is connected to the negative input of amplifier 405. An auto-zero switch Saz3 connected between capacitor C3 and the negative input of amplifier 405 is at clock phase +.>

During which it is turned off to maintain the charge stored on capacitor C3. Thus, at clock phase->

During this time, the offset voltage of the amplifier 405 is sampled on the auto-zero capacitor Caz 1. In the phase->

Switches Saz1 and Saz2 are open and switch Saz3 is closed such that the offset at amplifier 405 is offset by the pre-charged capacitor Caz 1. When in clock phase->

During which the error signal from capacitor C2 is transmitted by closing switch S13, switch Saz3 is also closed to form an integrator with amplifier 405 and capacitor C3. Thus, the use of switched capacitor voltage-to-current converter 135 in generating charging current Ichg is highly advantageous to ensure that the timing delays produced by the DTCs are robust to process, voltage and temperature variations.

Turning now to fig. 5, an example DTC 500 is shown in which switched capacitor voltage-to-current converter 135 and current mirror 110 are used to generate charging current Ichg as discussed with respect to DTC 100. In the DTC 500, the charging capacitor 505 is not integrated into the CDAC, but is charged separately with the initial voltage Vinit set by the DAC 510. The remaining components of DTC 500 function as described with respect to DTC 100. If a single CDAC is used to form the charging capacitor 505 and DAC 510, then the DTC 500 resolves to DTC 100. However, even though there is no power and die space savings provided by using CDAC, DTC 500 is still robust to process, voltage and temperature variations due to the use of switched capacitor voltage-to-current converter 135 to generate charging current Ichg.

An example method of operation of a DTC containing a CDAC will now be discussed with reference to the flowchart of fig. 6. The method includes an act 600 of: the capacitor array in the capacitive digital-to-analog converter is charged in response to the digital code to form a charged capacitor array. Charging the common terminal 145 to the initial voltage Vinit for the capacitor array is an example of act 600. Additionally, the method includes an act 605 of: which occurs in response to an edge of the timing signal and includes further charging the charged capacitor array with a charging current through the common terminal to form an increased voltage of the common terminal. Charging the CDAC capacitor through common terminal 145 after a trigger edge of the input clock signal is an example of act 605. Finally, the method includes an act 610 of: it is determined when the increased voltage is equal to the trip voltage. The comparison in comparator 115 is an example of act 610.

The DTCs disclosed herein may be advantageously incorporated into any suitable mobile device or electronic system. For example, as shown in fig. 7, a cellular telephone 700, a laptop computer 705, and a tablet PC 710 may each include a DTC according to the present disclosure. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, may also be configured with DTCs constructed in accordance with the present disclosure.

Referring again to DTC 100, the same advantageous density and power enhancement and robustness to process, voltage and temperature variations may be provided in the following alternative implementations: wherein the charging capacitor formed by the CDAC 105 discharges rather than charges during the time delay. An example of discharging DTC 800 is shown in fig. 8. CDAC 105 operates as discussed with respect to DTC 100 for converting digital codes to an initial voltage Vinit stored by the CDAC capacitor relative to common terminal 145 during a reassignment phase of CDAC 105. The current mirror 810 mirrors the first current from the switched capacitor voltage-to-current converter 805 to form a discharge current Idischarge. The current mirror 810 is connected to the common terminal 145 through switch S1 similar to that discussed for DTC 100 such that when switch S1 is closed to begin a time delay in response to triggering a clock signal edge, the voltage Vinit begins to discharge as the discharge current Idischarge discharges the CDAC capacitor.

The function of comparator 815 is also similar to that discussed with respect to comparator 115 for determining when the initial voltage Vinit decreases to be equal to the trip voltage Vtrip1. However, the trip voltage Vtrip for the DTC 100 is greater than the initial voltage Vinit, but the trip voltage Vtrip1 is less than the initial voltage Vinit. Since the output (clk_dtc_out) of the comparator 815 will go high at the end of the time delay (when the CDAC capacitor has discharged to less than the trip voltage Vtrip 1), an equivalent inverter to inverter 120 is not required in DTC 800. The functions of the remainder of DTC 800 are as discussed with respect to DTC 100.

It should be understood that many modifications, substitutions, and changes may be made in the materials, apparatuses, configurations, and methods of use of the apparatus of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the particular implementations shown and described herein, as they are merely a few examples, but rather should be fully commensurate with the scope of the following claims and functional equivalents thereof.

Claims

1. A circuit, comprising:

a capacitive digital-to-analog converter including a common terminal and a plurality of capacitors;

a first current source configured to charge the plurality of capacitors through the common terminal with a charging current; and

a comparator has a first input terminal coupled to the common terminal.

2. The circuit of claim 1, further comprising:

a first switch coupled between the first current source and the common terminal, the first switch configured to be responsive to a timing signal.

3. The circuit of claim 1, further comprising:

at least one resistor; and

a second current source configured to drive a reference current through the at least one resistor to generate a reference voltage.

4. The circuit of claim 3, further comprising:

a switched capacitor voltage-to-current converter configured to convert the reference voltage to a first current, wherein the first current source comprises a current mirror configured to generate the charging current based on the first current.

5. The circuit of claim 4, wherein the at least one resistor comprises a voltage divider having voltage divider nodes for a digital-to-analog (DAC) reference voltage for the capacitive digital-to-analog converter.

6. The circuit of claim 5, further comprising:

a second switch is coupled between the voltage divider node and the common terminal.

7. The circuit of claim 5, wherein a second input terminal of the comparator is coupled to the voltage divider node.

8. The circuit of claim 7, wherein the circuit is a digital-to-time converter comprising:

an inverter configured to invert the output signal from the comparator to form an output clock signal for the digital-to-time converter.

9. The circuit of claim 5, wherein the voltage divider comprises:

a first resistor coupled between the voltage divider node and the second current source, an

A second resistor is coupled between the voltage divider node and ground.

10. The circuit of claim 1, further comprising:

a second capacitor is coupled between the first input terminal and the common terminal of the comparator.

11. The circuit of claim 1, further comprising:

and a switch connected between an output terminal of the comparator and the first input terminal.

12. The circuit of claim 1, wherein the capacitive digital-to-analog converter further comprises:

a plurality of first switches corresponding to the plurality of capacitors, each first switch of the plurality of first switches coupled between a first plate of a corresponding capacitor of the plurality of capacitors and the common terminal, the first plurality of first switches configured to be responsive to a digital code.

13. The circuit of claim 12, wherein the second plate of each of the plurality of capacitors is switchably coupled to ground.

14. The circuit of claim 12, wherein the plurality of capacitors comprises a series of capacitors having a binary series of capacitances.

15. A method for operating a digital-to-time converter, comprising:

charging a capacitor array in a capacitive digital-to-analog converter in response to the digital code to form a charged capacitor array;

in response to a timing signal, further charging the charged capacitor array with a charging current through a common terminal to form an increased voltage of the common terminal; and

determining when the increased voltage is equal to the trip voltage.

16. The method of claim 15, further comprising:

converting the reference voltage into a first current in a switched capacitor voltage-to-current converter; and

the first current is mirrored in a current mirror to form the charging current, wherein a time delay of the digital-to-time converter is equal to a delay from a trigger edge of the timing signal to when the increased voltage is equal to the trip voltage.

17. The method of claim 16, further comprising:

generating a reference current; and

the reference current is driven through a resistor to form the reference voltage.

18. The method of claim 17, further comprising:

the trip voltage is generated from the reference current.

19. The method of claim 18, wherein charging the capacitor array in the capacitive digital-to-analog converter to form the charged capacitor array comprises:

in a first phase, charging a subset of capacitors in the capacitor array to the trip voltage to provide charge to the subset of capacitors; and

in a second phase, the charge is redistributed from the subset of capacitors to all capacitors in the capacitor array to form the charged capacitor array.

20. The method of claim 19, further comprising: during the redistribution of the charge, the capacitor array is isolated from the constant voltage source by opening one or more switches coupled between the capacitor array and the constant voltage source.

21. The method of claim 15, further comprising:

a switch is closed in response to the timing signal to couple a current source to the common terminal, the current source configured to transmit the charging current.

22. A circuit, comprising:

a voltage-to-current switched capacitor converter configured to convert a reference voltage to a first current;

charging a capacitor;

a current mirror configured to mirror the first current as a charging current for charging the charging capacitor; and

a comparator has a first input coupled with the charging capacitor and a second input configured to receive a trip voltage.

23. The circuit of claim 22, further comprising:

a switch configured to close in response to a timing signal to couple the current mirror to the charging capacitor.

24. The circuit of claim 22, further comprising:

a capacitive digital-to-analog converter includes a capacitor array for forming the charging capacitor.

25. The circuit of claim 21, wherein the circuit is included within a cellular telephone.

26. A circuit, comprising:

a first current source configured to discharge the plurality of capacitors with a discharge current conducted through the common terminal; and

a comparator has a first input terminal coupled to the common terminal.

27. The circuit of claim 26, further comprising:

a first switch coupled between the first current source and the common terminal, the first switch configured to close in response to a timing signal.

28. The circuit of claim 26, further comprising:

at least one resistor; and

29. The circuit of claim 28, further comprising:

a switched capacitor voltage-to-current converter configured to convert the reference voltage to a first current, wherein the first current source comprises a current mirror configured to mirror the first current to the discharge current.

30. The circuit of claim 29, wherein the at least one resistor comprises a voltage divider having voltage divider nodes for a digital-to-analog (DAC) reference voltage for the capacitive digital-to-analog converter.