KR20230084318A - Power and Area Efficient DIGITAL-TO-TIME CONVERTER with Improved Reliability - Google Patents

Abstract

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter (VIC) for forming a charge current (or discharge current) to charge (or discharge) the charge capacitor in response to a triggering clock edge initiating a time delay. A comparator compares the voltage on the charging capacitor to a threshold voltage to determine the end of the time delay.

Description

Power and Area Efficient DIGITAL-TO-TIME CONVERTER with Improved Reliability

[0001] This application claims priority to and benefit from U.S. Patent Application No. 17/111,208, filed on December 3, 2020, and U.S. Patent Application No. 17/449,250, filed on September 28, 2021, hereby The entire contents of the above applications are incorporated by reference.

[0002] FIELD OF THE INVENTION This application relates to digital-to-time converters (DTCs) and, more particularly, to a power-efficient and area-efficient digital-to-time converter (DTC) that is robust to process, voltage, and temperature variations.

[0003] Fractional-N phase-locked loops (PLLs) are key building blocks of frequency synthesizers as well as low-jitter clocking applications using either fixed frequency or spread spectrum. To provide improved performance for phase noise and fractional spurs while achieving low power, digital-to-time converters (DTCs) are used in fractional-N PLLs. The DTC converts a digital code or word into a time delay, acting as a high resolution true fractional frequency divider in the PLL. DTCs are also a basic building block suitable for sampling oscilloscopes, direct digital frequency synthesis (DDFS), polarity transmitters, radar, phase-array systems, and other applications including time-interleaved ADC timing corrections. admit.

[0004] It is known to form a DTC using complementary metal-oxide semiconductor (CMOS) delay cells. However, CMOS delay cells are sensitive to process, voltage, and temperature (PVT) changes. Thus, improved supply noise robustness can be obtained by implementing the DTC with a capacitor charging circuit. The capacitor charging circuit charges the capacitor according to the digital word converted to a time delay by the DTC. A digital-to-analog converter (DAC), such as a resistive DAC (R-DAC), converts the digital word into an initial voltage (Vinit) across a charging capacitor. The Vinit-charged charge capacitor is then further charged with constant current until the charge capacitor voltage reaches the threshold voltage Vtrip. The time delay is equal to the delay from charging the Vinit-charged capacitor from Vinit to Vtrip. However, DACs consume power and semiconductor die area. Also, DTCs can suffer from process, voltage, and temperature variations.

[0005] a capacitive digital-to-analog converter (DAC) including a common terminal and a plurality of capacitors; a first current source configured to charge a plurality of capacitors through a common terminal with a charging current; and a comparator having a first input terminal coupled to the common terminal.

[0006] Also, charging the capacitor array in a capacitive digital-to-analog converter (DAC) in response to the digital code to form a charged capacitor array; further charging the charged capacitor array through the common terminal with a charging current in response to the timing signal to form an increasing voltage across the common terminal; and determining when the increasing voltage is equal to the trip voltage.

[0007] Moreover, a switched capacitor voltage-to-current converter (VIC) configured to convert the reference voltage into a first current; charging capacitor; a current mirror configured to mirror the first current as a charging current for charging the charging capacitor; and a comparator having a first input coupled to the charging capacitor and a second input configured to receive a trip voltage.

[0008] Finally, a capacitive digital-to-analog converter (DAC) including a common terminal and a plurality of capacitors; a first current source configured to discharge the plurality of capacitors with a discharge current conducted through the common terminal; and a comparator having a first input terminal coupled to the common terminal.

[0009] These and other advantageous features may be better appreciated from the detailed description that follows.

[0010] FIG. 1 is a diagram of an example DTC in which a capacitive DAC (CDAC) functions as a charging capacitor that is charged during a time delay, in accordance with an aspect of the present disclosure.
[0011] FIG. 2 illustrates some exemplary voltage waveforms for charging of the charging capacitor in the DTC of FIG. 1.
[0012] FIG. 3 is a circuit diagram of a binary weighted CDAC for DTC, in accordance with an aspect of the present disclosure.
[0013] FIG. 4 is a circuit diagram of a switched capacitor voltage-to-current converter (VIC) and current mirror, in accordance with an aspect of the present disclosure.
[0014] FIG. 5 is a diagram of an example DTC in which a switched capacitor voltage-to-current converter (VIC) functions to generate a charging current for a charging capacitor, in accordance with an aspect of the present disclosure.
[0015] FIG. 6 is a flow diagram of an example method of operation for DTC, in accordance with an aspect of the present disclosure.
7 illustrates some example electronic systems each including a DTC, in accordance with an aspect of the present disclosure.
[0017] FIG. 8 is a diagram of an example DTC in which the CDAC functions as a charging capacitor that is discharged for a time delay, in accordance with an aspect of the present disclosure.
[0018] Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numbers are used to identify like elements illustrated in one or more of the drawings.

[0019] A digital-to-time converter (DTC) is disclosed in which a capacitor DAC (CDAC) functions as a digitally controlled voltage generator for the charging capacitor and also for the charging capacitor itself. Compared to traditional charged capacitor DTC architectures, the resulting DTC improves power efficiency and occupies a reduced semiconductor die area. This reduction in die space improves density as more of the same circuitry can be integrated into the same die space due to the reduced area for digital-to-time converter (DTC) implementation. A switched capacitor voltage-to-current converter (VIC) for generation of a charge current for a charge capacitor to improve stability over process, voltage, and temperature changes is also disclosed.

[0020] An exemplary DTC 100 is shown in FIG. 1 . The CDAC 105 includes a capacitor array sharing a common terminal 145 that is charged to an initial voltage (Vinit) in response to a digital DTC code (dtc_code). As will be further described herein, CDAC 105 functions such that Vinit is a fraction of the DAC reference voltage (Vref_dac). The number of different fractions depends on the resolution of CDAC 105 and its encoding. For example, in a 3-bit binary encoded implementation, CDAC 105 can convert the DTC code (dtc_code) to one of the following 8 possible settings for Vinit: 0 V, 1/8 Vref_dac, 1/4 Vref_dac , 3/8 Vref_dac, 1/2 Vref_dac, 5/8 Vref_dac, 3/4 Vref_dac, and 7/8 Vref_dac.

[0021] Since the capacitors of CDAC 105 are all connected in parallel to common terminal 145 after being charged to Vinit, they function as a single charged capacitor. With the capacitors of CDAC 105 charged to Vinit, an edge (could be a rising edge or a falling edge) of a timing signal such as the input clock signal clk_in triggers switch S1 to close, causing the current mirror ( 110) starts charging the capacitors with a constant charge current Ichg. Comparator 115 serves to compare the common terminal voltage of CDAC 105 with a threshold voltage Vtrip. The output signal from comparator 115 may be inverted by inverter 120 to form the output clock signal clk_dtc_out for DTC 100 that is asserted to the power supply voltage at the end of the time delay. Thus, the time delay from DTC 100 is equal to the delay between the triggering edge of the input clock edge and the assertion of the output clock signal. In an alternative implementation, comparator 115 may be configured such that the output clock signal has a falling edge (discharge to ground) at the end of the time delay.

[0022] Some exemplary waveforms for charging the capacitors of CDAC 105 are shown in FIG. 2 . In the discussion that follows, the capacitors of CDAC 105 are collectively referred to as charging capacitors because they are connected in parallel with respect to common terminal 145 in the charge redistribution phase where they are charged to Vinit. In the first waveform 200, the charging capacitor is charged to an initial voltage Vinit1 greater than the initial voltage Vinit2 for the second waveform 205. The triggering edge of the input clock signal occurs at time t0. Both waveforms increase linearly from a constant charge current (Ichg). However, waveform 200 reaches Vtrip at a time t1 earlier than the time t2 at which waveform 205 reaches Vtrip because Vinit1 is greater than Vinit2. Thus, the time delay Δt1 from time t0 to time t1 for waveform 200 is less than the time delay Δt2 from time t0 to time t2 for waveform 205.

[0023] Referring again to FIG. 1 , any suitable current source may be used to charge the charging capacitor with a constant charging current Ichg when switch S1 is closed. A particularly advantageous current source is provided by a switched capacitor voltage-to-current converter (VIC) 135 that functions to make the DTC 100 robust to process, voltage, and temperature variations, as will be further described herein. is formed A switched capacitor voltage-to-current converter (VIC) 135 converts the input reference voltage Vrefp into a first current I. A current source such as current mirror 110 mirrors the first current I into a charging current Ichg that charges the charging capacitor. To generate an input reference voltage Vrefp, a current source 125 as biased by a bias voltage Vbias drives a reference current Iref into a resistor. In DTC 100, current source 125 drives reference current Iref into a pair of resistors R2 and R1, although in alternative implementations a single resistor (or more than two resistors) may be used. You will recognize that you can. In an alternative implementation, a voltage reference circuit with a voltage buffer may be used instead of the current source 125 to generate the input reference voltage Vrefp.

[0024] Resistors R2 and R1 are arranged in series between the current source 125 and ground. Resistors R1 and R2 are connected to a reference voltage where voltage divider node 140 between resistors R1 and R2 equals a divided version of input reference voltage Vrefp according to the resistances to resistors R1 and R2. Form a voltage divider to be charged to (Vref_dac). By appropriate adjustment of these resistors, the output voltage range of CDAC 105 can be set with respect to the input reference voltage Vrefp.

[0025] In some implementations, resistor R2 can be shorted or removed so that reference voltage Vref_dac equals input reference voltage Vrefp so that the offset of comparator 115 can be compensated for as follows. If comparator 115 is perfect, comparator 115 will discharge its output signal when its negative terminal input voltage (Vn) equals the Vtrip at its positive input terminal. However, due to nonidealities, comparator 115 may instead discharge its output signal when the negative terminal input voltage (Vn) is equal to the sum of Vtrip and some offset voltage, which may be positive or negative. . To compensate for this offset voltage, an auto-zero sampling switch (S3) coupled between the output of comparator 115 and its negative input terminal is closed during the auto-zero phase prior to charging of the charging capacitor. do. In the auto-zero phase, switch S2 coupled from voltage divider node 140 through auto-zero capacitor Caz to the negative input terminal of comparator 115 is also closed, so that the negative input of comparator 115 The reference voltage Vref_dac is coupled to a first terminal of an auto-zero comparator Vac having a second terminal connected thereto. Due to the feedback through the auto-zero switch S3 in the auto-zero phase, the auto-zero capacitor Caz will be charged to the offset voltage during the auto-zero phase. During normal operation, switches S2 and S3 are then opened. Due to pre-charging of the auto-zero capacitor (Caz) to cancel the offset voltage, comparator 115 then causes common terminal 145 to charge to the trip voltage (Vtrip) regardless of the offset voltage of comparator 115. When it is, it discharges its own output signal and toggles the output of the inverter 120.

[0026] CDAC 100 may be formed using any suitable encoding of its capacitors. An exemplary binary encoded CDAC 300 is shown in more detail in FIG. 3 . A reference voltage (Vref_dac) flows through switch S2 during the initial charging stage to charge common terminal 145 of capacitor array 305. CDAC 300 is a 3-bit wide digital code ( dtc_code). As implied by the names, there is a binary sequence for the capacitance of the capacitors such that capacitor 4C has twice the capacitance of capacitor 2C which in turn has twice the capacitance of each of the 1C/1C' capacitors . Each capacitor has a first plate coupled to ground or common terminal 145 through a corresponding single-pole-double-throw (SPDT) switch. For example, capacitor 4C has a first plate coupled to SPDT switch S4, capacitor 2C has a first plate coupled to SPDT switch S5, and capacitor 1C has an SPDT switch ( S6) and capacitor 1C' has a first plate coupled to SPDT switch S7. During the initial charging phase, the bottom switch S8 coupled between the second plate of each capacitor and ground is closed. The setting of each SPDT switch during the initial charging stage depends on the DTC code. As previously discussed, a 3-bit DTC code corresponds to 8 different values of Vinit ranging from, for example, 0V to 7/8 Vref_dac. For the 0V setting, each SPDT switch selects ground instead of common terminal 145. However, as the DTC code increases, more and more SPDT switches choose common terminal 145 instead of ground to charge their individual capacitors with the DAC reference voltage (Vref_dac). For example, a maximum value for a 3-bit DTC code can cause switches S4, S5, and S6 to select a common terminal, while switch S7 selects ground. In that case, capacitors S4, S5, and S6 are all charged to the DAC reference voltage during the initial charging phase.

[0027] When the appropriate capacitors are charged in the initial charge phase in response to the DTC code, the charge redistribution phase occurs. The charge redistribution phase is initiated by opening the lower switch (S8). This advantageously prevents the charge on the capacitors in the capacitor array 305 from being charged during the charge redistribution phase since the second plate for each capacitor is floating. More generally, the ground may be replaced with a constant voltage source such that the bottom switch S8 is coupled between the second plate of each capacitor and the constant voltage source. It will be appreciated that in alternative implementations switch S8 may be replaced with a plurality of switches S8. When the bottom switch S8 is open, switch S2 is also open to isolate the common terminal from the DAC reference voltage Vref at voltage divider node 140. All SPDT switches are then configured to select common terminal 145 such that the first plate for each capacitor is connected to common terminal 145. Thus, the charge on the first plates is redistributed from the capacitors charged in the initial charging phase to the capacitors grounded in the initial charging phase. Nonidealities may cause the switching of the SPDT switches to be staggered or unsynchronized, but no charge injection occurs due to the opening of the bottom switch (S8), which is due to the floating of the second plate for each of the capacitors. Note that "locks" the total charge on . The redistribution phase is then completed by closing the bottom switch S8. Common terminal 145 is then charged to Vinit so that the input clock can be asserted to trigger charging of the Vinit-charged charge capacitor via the closure of switch S1.

[0028] An exemplary switched capacitor voltage-to-current converter (VIC) 135 with current mirror 110 is shown in FIG. 4 . A differential amplifier 405 having a feedback capacitor C3 coupled between the output of the differential amplifier 405 and its negative input terminal integrates the difference between the input reference voltage Vrefp and its negative input terminal voltage. form an error integrator. Amplifier 405 drives the gate of NMOS transistor M4, which has its source connected to transformer resistor Rdg (or ground in other implementations) and its drain connected to the gate and drain of diode-connected PMOS transistor M3. Transistor M3 forms a current mirror with current mirror PMOS transistor M2. Similarly, transistor M3 together with current mirror PMOS transistor M1 forms current mirror 110. The sources of transistors M1, M2, and M3 are connected to the power supply terminal for the power supply voltage. The gates of transistors M1 and M2 are connected to the gate of diode-connected transistor M3. When amplifier 405 causes transistor M4 to conduct current, that current then transistor to form a first current I that is mirrored by current mirror 110 to form charging current Ichg. are mirrored through M3 and M1. Transistor M1 is sized relative to transistor M2 such that the charging current Ichg is a factor K times the first current I. The drain of transistor M1 is coupled to the first plate of capacitor C1 through switch S11 and also coupled to ground through switch S9. The second plate of capacitor C1 is connected to ground. Also, the first plate of capacitor C1 is coupled to ground through switch S10. Also, the first plate of capacitor C1 is coupled to the first plate of capacitor C2 through switch S12. The second plate of capacitor C2 is connected to ground. The first plate of capacitor C2 is coupled to the negative input terminal of amplifier 405 through switch S13.

[0029] A clock source such as a crystal oscillator (not illustrated) generates clock signals for controlling the switches S9, S10, S11, S12, and S13. The clock signal oscillates between two phases at frequency F _CLK . For example, a first phase φ1 of the clock signal may correspond when the clock signal is charging to the power supply voltage, while a second phase φ2 may correspond when the clock signal is discharging, but these two phases are alternatively It may be reversed in implementations. When the clock signal is in phase φ1, the switches S11 and S12 are closed. During phase φ1, current I charges capacitors C1 and C2 through closed switches S11 and S12. Switches S9, S10, and S13 are open during phase φ1. In phase φ2, switches S9, S10, and S13 are closed while switches S11 and S12 are open. In phase φ2, the charge on capacitor C2 drives the negative input terminal of amplifier 405. Capacitor C1 is discharged during phase φ2, and first current I is discharged to ground through closed switch S9. Given this clocking of the switches, it can be shown that the first current I is equal to 2*F _CLK *Vrefp*C1. The current mirror transistor M1 mirrors the first current I such that the charging current Ichg is equal to K times the proportional constant of the first current I. Therefore, the charge current Ichg is equal to K*2*F _CLK *Vrefp*C1. To show that this relationship to charge current (Ichg) is very advantageous for reducing process, voltage, and temperature variations on the timing delay from the DTCs disclosed herein, the maximum timing delay for the DTCs disclosed herein Consider that C can be expressed as C _DAC * (Vtrip/Ichg), where C _DAC is the capacitance of the CDAC capacitor array (capacitance of the charging capacitor). As discussed above, if Vtrip and Vrefp are equal, the maximum delay can be expressed as (1/K) * (1/F _CLK ) * (C _DAC /C1). These factors are easily and precisely controlled in the integrated circuit including DTC 100, in contrast to conventional DTCs which rely on the precision of resistors or capacitors.

[0030] Mismatch errors between the transistors M1 , M2 , and M3 may be improved by using dynamic element matching (DEM) techniques through the switching matrix 410 . Switching matrix 410 dynamically switches the drain connections of transistors M1, M2, and M3 so that the roles of transistors M1, M2, and M3 are dynamically swapped while the relative mirror ratios between them change. keep from becoming For example, in the first configuration of switching matrix 410, the drain of transistor M3 is connected to the drain of transistor M4 as shown in FIG. However, in the second configuration of switching matrix 410, the drain of transistor M3 is connected to switch S11 instead. In this second configuration, the drain of current mirror transistor M2 can then be connected to the drain of transistor M4 through switching matrix 410 . Similarly, the drain of current mirror transistor M1 is normally coupled to switch S1 (FIG. 1), but in other switching configurations the switching matrix ( 410) is dynamically switched. The resulting swapping of the current mirror elements can be triggered in phase φ2 without affecting the capacitor charging operations.

[0031] Referring again to FIG. 4 , the offset of amplifier 405 may be removed by an auto-zero technique similar to that discussed with respect to comparator 115 . During clock phase φ1, switch Saz1 connected between the negative input of amplifier 405 and the output of amplifier 405 as well as the node for reference voltage Vrefp and the first plate of auto-zero capacitor Caz1 A switch (Saz2) connected therebetween is closed. The second plate of the auto-zero capacitor Caz2 is connected to the negative input of amplifier 405. An auto-zero switch Saz3 connected between capacitor C3 and the negative input of amplifier 405 is open during clock phase φ1 to conserve the charge stored in capacitor C3. Thus, the offset voltage for amplifier 405 is sampled on auto-zero capacitor Caz1 during clock phase φ2. In phase φ2, switches Saz1 and Saz2 are open and switch Saz3 is closed such that the offset in amplifier 405 is canceled by the pre-charged capacitor Caz1. While the error signal from capacitor C2 is propagated by closing switch S13 during clock phase φ2, switch Saz3 is also closed to form an integrator with amplifier 405 and capacitor C3. Thus, using a switched capacitor voltage-to-current converter (VIC) 135 in the generation of the charge current Ichg is a matter of ensuring that the timing delay created by the DTC is robust to process, voltage, and temperature variations. very advantageous in this regard.

[0032] Referring now to FIG. 5 , an example in which a switched capacitor voltage-to-current converter (VIC) 135 and current mirror 110 function to generate a charge current Ichg as discussed with respect to DTC 100. An enemy DTC 500 is shown. In DTC 500, charging capacitor 505 is not integrated into the CDAC, but is instead separately charged to the initial voltage Vinit as set by DAC 510. The remaining components of DTC 500 function as discussed with respect to DTC 100 . When a single CDAC is used to form charging capacitor 505 and DAC 510, DTC 500 is converted to DTC 100. However, even without the power and die space savings provided by the use of a CDAC, DTC 500 still uses a switched capacitor voltage-to-current converter (VIC) 135 to generate charge current Ichg. It is robust to process, voltage, and temperature variations.

[0033] An example method of operation for a CDAC-included DTC will now be discussed with reference to the flowchart of FIG. 6 . The method includes an operation 600 of charging a capacitor array in a capacitive digital-to-analog converter (DAC) in response to a digital code to form a charged capacitor array. Charging common terminal 145 for the capacitor array to an initial voltage Vinit is an example of operation 600 . The method also includes further charging the charged capacitor array, through the common terminal, with a charging current to form an increasing voltage across the common terminal, which occurs in response to an edge of the timing signal. (605). Charging the CDAC capacitors via common terminal 145 after the triggering edge of the input clock signal is an example of operation 605 . Finally, the method includes an act 610 of determining when the increasing voltage is equal to the trip voltage. The comparison at comparator 115 is an example of operation 610 .

[0034] A DTC as disclosed herein may advantageously be incorporated into any suitable mobile device or electronic system. For example, as shown in FIG. 7, cellular phone 700, laptop computer 705, and tablet PC 710 may all include a DTC in accordance with the present disclosure. Additionally, other exemplary electronic systems such as music players, video players, communication devices, and personal computers may be configured with DTCs configured in accordance with the present disclosure.

[0035] Referring again to DTC 100, in alternative implementations in which the charged capacitor formed by CDAC 105 is instead discharged during a time delay instead of charging, the same advantageous density and power improvements as well as process, voltage, and temperature Robustness to changes can be provided. An exemplary discharge DTC 800 is shown in FIG. 8 . CDAC 105 is used as discussed with respect to DTC 100 to convert the digital code to the initial voltage Vinit stored by CDAC capacitors across common terminal 145 during the redistribution phase for CDAC 105. function together The current mirror 810 mirrors the first current from the switched capacitor voltage-to-current converter (VIC) 805 to form a discharge current (Idischarge). A current mirror 810 is connected to common terminal 145 through switch S1, similar to that discussed for DTC 100, to switch S1 in response to a triggering clock signal edge to initiate a time delay. When is closed, the voltage (Vinit) starts to discharge as the discharge current (Idischarge) discharges the CDAC capacitor.

[0036] Comparator 815 also functions similarly as discussed with respect to comparator 115, determining when initial voltage Vinit decreases to equal trip voltage Vtrip1. However, the trip voltage Vtrip of the DTC 100 is greater than the initial voltage Vinit, whereas the trip voltage Vtrip1 is less than the initial voltage Vinit. Since the output of comparator 815 (clk_dtc_out) will go high at the end of the time delay when the CDAC capacitors have discharged to less than trip voltage Vtrip1, an inverter equivalent to inverter 120 of DTC 800. there is no need for The rest of the functionality of DTC 800 functions as discussed with respect to DTC 100.

[0037] It will be appreciated that many modifications, substitutions and changes may be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope of the disclosure. In light of this, as the specific implementations illustrated and described herein are merely some examples herein, the scope of the disclosure should not be limited to the scope of such specific implementations, but rather the claims appended below and their functional equivalents should be It must fully correspond to the scope.

Claims (30)

As a circuit,
a capacitive digital-to-analog converter (DAC) including a common terminal and a plurality of capacitors;
a first current source configured to charge the plurality of capacitors through the common terminal with a charging current; and
and a comparator having a first input terminal coupled to the common terminal. According to claim 1,
a first switch coupled between the first current source and the common terminal;
wherein the first switch is configured to respond to a timing signal. According to claim 1,
at least one resistor; and
and a second current source configured to drive a reference current through the at least one resistor to generate a reference voltage. According to claim 3,
Further comprising a switched capacitor voltage-to-current converter (VIC) configured to convert the reference voltage into a first current;
wherein the first current source comprises a current mirror configured to generate the charging current based on the first current. According to claim 4,
wherein the at least one resistor comprises a voltage divider having a voltage divider node for a digital-to-analog (DAC) reference voltage for the capacitive digital-to-analog converter (DAC). According to claim 5,
and a second switch coupled between the voltage divider node and the common terminal. According to claim 5,
and a second input terminal of the comparator is coupled to the voltage divider node. According to claim 7,
The circuit is a digital-to-time converter (DTC),
wherein the DTC includes an inverter configured to invert an output signal from the comparator to form an output clock signal for the digital-to-time converter (DTC). According to claim 5,
The voltage divider is
a first resistor coupled between the voltage divider node and the second current source; and
and a second resistor coupled between the voltage divider node and ground. According to claim 1,
and a second capacitor coupled between the first input terminal of the comparator and the common terminal. According to claim 1,
and a switch coupled between an output terminal of the comparator and the first input terminal. According to claim 1,
The capacitive DAC (digital-to-analog converter),
Further comprising a plurality of first switches corresponding to the plurality of capacitors,
each first switch in the plurality of first switches is coupled between the common terminal and a first plate for a corresponding capacitor in the plurality of capacitors;
wherein the plurality of first switches are configured to respond to a digital code. According to claim 12,
and a second plate of each capacitor in the plurality of capacitors is switchably coupled to ground. According to claim 12,
wherein the plurality of capacitors comprises a series of capacitors having a binary sequence of capacitances. As a method for operating a digital-to-time converter (DTC),
charging the capacitor array in a capacitive digital-to-analog converter (DAC) in response to the digital code to form a charged capacitor array;
further charging the charged capacitor array through the common terminal with a charging current in response to a timing signal to form an increasing voltage across the common terminal; and
and determining when the increasing voltage equals a trip voltage. According to claim 15,
converting a reference voltage into a first current in a switched capacitor voltage-to-current converter (VIC); and
mirroring the first current at a current mirror to form the charging current;
The time delay for the digital-to-time converter (DTC) is equal to the delay from the triggering edge of the timing signal until the increasing voltage equals the trip voltage. How to make it work. According to claim 16,
generating a reference current; and
further comprising driving the reference current through a resistor to form the reference voltage. According to claim 17,
generating the trip voltage from the reference current. According to claim 18,
Charging the capacitor array in the capacitive digital-to-analog converter (DAC) to form the charged capacitor array comprises:
in a first phase, charging a subset of capacitors in the capacitor array to the trip voltage to provide charge to the subset of capacitors; and
In a second phase, operating a digital-to-time converter (DTC) comprising redistributing the charge from the subset of capacitors to all capacitors in the capacitor array to form the charged capacitor array. way to do it. According to claim 19,
isolating the capacitor array from the constant voltage source while redistributing the charge by opening one or more switches coupled between the capacitor array and the constant voltage source. way to do it. According to claim 15,
operating a digital-to-time converter (DTC), further comprising closing a switch in response to the timing signal to couple a current source configured to source the charging current to the common terminal. method. As a circuit,
a switched capacitor voltage-to-current converter (VIC) configured to convert the reference voltage into a first current;
charging capacitor;
a current mirror configured to mirror the first current as a charging current for charging the charging capacitor; and
and a comparator having a first input coupled to the charging capacitor and a second input configured to receive a trip voltage. 23. The method of claim 22,
and a switch configured to close in response to a timing signal to couple the current mirror to the charging capacitor. 23. The method of claim 22,
and a capacitive digital-to-analog converter (DAC) comprising a capacitor array to form the charging capacitor. According to claim 21,
The circuit of claim 1 , wherein the circuit is included within a cellular telephone. As a circuit,
a capacitive digital-to-analog converter (DAC) including a common terminal and a plurality of capacitors;
a first current source configured to discharge the plurality of capacitors with a discharge current conducted through the common terminal; and
and a comparator having a first input terminal coupled to the common terminal. 27. The method of claim 26,
a first switch coupled between the first current source and the common terminal;
wherein the first switch is configured to close in response to a timing signal. 27. The method of claim 26,
at least one resistor; and
and a second current source configured to drive a reference current through the at least one resistor to generate a reference voltage. 29. The method of claim 28,
Further comprising a switched capacitor voltage-to-current converter (VIC) configured to convert the reference voltage into a first current;
wherein the first current source comprises a current mirror configured to mirror the first current to the discharge current. According to claim 29,
wherein the at least one resistor comprises a voltage divider having a voltage divider node for a DAC reference voltage for the capacitive digital-to-analog converter (DAC).

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