TW202322431A - Light emitting diode chip and light emitting diode device - Google Patents

Abstract

A light emitting diode chip including an epitaxy stacked layer, a first and a second electrodes is provided. The epitaxy stacked layer includes a first-type and a second-type semiconductor layers, a light-emitting layer and an unintentionally doped semiconductor layer. The first and the second electrodes are respectively electrically connected to the first-type and a second-type semiconductor layers. At least the unintentionally doped semiconductor layer has a coarse structure among the epitaxy stacked layer. Furthermore, a light emitting diode device is also provided.

Description

Light-emitting diode chip and light-emitting diode device

The present invention relates to a photoelectric element, and in particular to a light-emitting diode wafer, a light-emitting diode device and a light-emitting diode module.

Light Emitting Diode (Light Emitting Diode, LED) is a light-emitting semiconductor electronic component. It is widely used due to its advantages such as high energy conversion efficiency, short reaction time, long life, small size, and high reliability. Signal lights, car lights, outdoor large display panels, mobile phone backlights, etc. At present, those skilled in the art are still striving to improve the luminous efficiency and brightness of light-emitting diodes.

The invention provides a light-emitting diode wafer, a light-emitting diode device and a light-emitting diode module, which have high luminous efficiency.

An embodiment of the present invention provides a light-emitting diode wafer, including an epitaxial stack, a first electrode, a second electrode, and a first reflective layer. The epitaxial stack includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer. The light emitting layer is located between the first type semiconductor layer and the second type semiconductor layer. The first electrode is disposed on the first type semiconductor layer and electrically connected with the first type semiconductor layer. The orthographic projection of the light emitting layer on the first type semiconductor layer is dislocated from the orthographic projection of the first electrode on the first type semiconductor layer. The second electrode is disposed on the second-type semiconductor layer and electrically connected with the second-type semiconductor layer. The first reflective layer is disposed on the epitaxial stack, the first electrode and the second electrode. The orthographic projection of the first reflective layer on the second-type semiconductor layer is dislocated from the orthographic projection of the second electrode on the second-type semiconductor layer.

An embodiment of the present invention provides a light-emitting diode device, including the above-mentioned light-emitting diode chip, a first electrode pad, and a carrier substrate. The first electrode pad is arranged on one side of the light-emitting diode wafer, and is electrically connected with the first electrode. The carrier substrate is disposed on the other side of the light-emitting diode chip, and is electrically connected with the second electrode. The carrier substrate has a first surface and a second surface opposite to each other. The LED chip and the first electrode pad are arranged on the first surface.

An embodiment of the present invention provides a light-emitting diode module, including the above-mentioned light-emitting diode device, a circuit substrate, a third electrode pad, and a fourth electrode pad. The third electrode pad is electrically connected to the circuit substrate, and the third electrode pad is electrically connected to the first electrode pad. The fourth electrode pad is electrically connected to the circuit substrate, and the fourth electrode pad is electrically connected to the second electrode pad.

In an embodiment of the present invention, the above light-emitting diode chip further includes a first reflective stack, including a first insulating layer, a first reflective layer, and a second insulating layer. The first reflective layer is disposed between the first insulating layer and the second insulating layer. The first insulating layer is disposed on the epitaxial stack, the first electrode and the second electrode and has a plurality of first through holes. The first reflective layer is disposed on the first insulating layer and has a plurality of second through holes. The orthographic projections of the second through holes on the second-type semiconductor layer overlap with the orthographic projections of the second electrodes on the second-type semiconductor layer. The second insulating layer is disposed on the first reflective layer and has a plurality of third through holes. These first through holes, these second through holes and these third through holes expose the second electrode, and the orthographic projection area of the second through holes on the second-type semiconductor layer is greater than or equal to that of the first through holes or the third through holes. The orthographic projection area of the hole on the second type semiconductor layer, wherein the orthographic projection area of the first through hole and the third through hole on the second type semiconductor layer are the same.

In an embodiment of the present invention, the aforementioned LED chip further includes a first connection metal layer. The first connecting metal layer is disposed on the second insulating layer and is electrically connected to the second electrode through the first through holes, the second through holes and the third through holes.

In an embodiment of the present invention, the above-mentioned first reflective stack further includes a second reflective layer. The second reflective layer is disposed on the first reflective layer and between the second insulating layer and the first insulating layer. The second reflective layer has a plurality of fourth through holes, the orthographic projections of these fourth through holes on the second type semiconductor layer overlap the orthographic projection of the second electrode on the second type semiconductor layer, and the fourth through holes are on the second type semiconductor layer. The area of the orthographic projection on the second type semiconductor layer is greater than or equal to the area of the orthographic projection of the second through hole on the second type semiconductor layer, or the area of the orthographic projection of the fourth through hole on the second type semiconductor layer is greater than or equal to the area of the first through hole Orthographic projection area of the hole or the third through hole on the second-type semiconductor layer. The first through holes, the second through holes, the third through holes and the fourth through holes expose the second electrodes.

In an embodiment of the present invention, the aforementioned LED chip further includes a first connection metal layer. The first connecting metal layer is disposed on the second insulating layer and is electrically connected to the second electrode through the first through holes, the second through holes, the third through holes and the fourth through holes.

In an embodiment of the present invention, the aforementioned LED chip further includes a second reflective stack. The second reflective stack is disposed on the first reflective stack. The second reflective stack further includes a third insulating layer, a third reflective layer and a fourth insulating layer. The third reflective layer is disposed between the third insulating layer and the fourth insulating layer. The third insulating layer is disposed on the first reflective stack and has a plurality of fifth through holes. The third reflective layer is disposed on the third insulating layer and has a plurality of sixth through holes. The orthographic projections of the sixth through holes on the second-type semiconductor layer overlap with the orthographic projections of a part of the second electrode on the second-type semiconductor layer. The fourth insulating layer is disposed on the second reflective layer and has a plurality of seventh through holes. These fifth through holes, these sixth through holes and these seventh through holes expose this part of the second electrode, and the orthographic projection area of the sixth through holes on the second-type semiconductor layer is greater than or equal to that of the fifth through holes or The orthographic projection area of the seventh through hole on the second type semiconductor layer, wherein the orthographic projection areas of the fifth through hole and the seventh through hole on the second type semiconductor layer are the same. The area of the orthographic projection of the sixth through hole on the second type semiconductor layer of the third reflective layer disposed on the third insulating layer is greater than or equal to the second through hole disposed on the first insulating layer of the first reflective layer on the second type semiconductor layer. Orthographic projection area on the semiconductor layer, the first via hole on the first insulating layer, the third via hole on the second insulating layer, the fifth via hole on the third insulating layer and the seventh via hole on the fourth insulating layer The orthographic projection areas of the through holes on the second type semiconductor layer are the same.

In an embodiment of the present invention, the above light-emitting diode chip further includes a first connection metal layer, a first current conduction layer, and a second current conduction layer. The first connection metal layer is disposed on the second reflective stack. The first current conducting layer and the second current conducting layer are located between the first reflective stack and the second reflective stack. The first current conducting layer is disposed on the first electrode and electrically connected to the first electrode. The second current conducting layer is disposed on the second electrode and electrically connected with the second electrode. The first connecting metal layer is electrically connected to the second current conducting layer through the fifth through holes, the sixth through holes and the seventh through holes.

In an embodiment of the present invention, the above-mentioned first electrode further includes a plurality of first electrode parts separated from each other, and the second electrode further includes a plurality of second electrode parts separated from each other. The second electrode parts are arranged around the first electrode parts. The first current conducting layer is electrically connected to a plurality of separated first electrode parts and the second current conducting layer is electrically connected to a plurality of separated second electrode parts, and the first connection metal layer is connected to the second current conducting layer through the second current conducting layer. A plurality of separated second electrodes are electrically connected.

In an embodiment of the present invention, one of the above-mentioned first electrode portions is used as an etching stopper layer.

In an embodiment of the present invention, the above-mentioned first electrode further includes at least one main body and a plurality of fingers extending from the main body. The fingers extend toward the edge of the light-emitting diode chip, and the second electrode further includes a plurality of electrode parts separated from each other.

In an embodiment of the present invention, the above light-emitting diode chip further includes an etching stopper layer. The etch stop layer is disposed on the first type semiconductor layer. The main body covers the etching barrier layer.

In an embodiment of the present invention, the above light emitting diode chip further includes a current blocking layer and an ohmic contact layer. The current blocking layer and the ohmic contact layer are disposed between the ohmic contact layer and the second-type semiconductor layer, and the ohmic contact layer covers the current blocking layer.

In an embodiment of the present invention, the above-mentioned epitaxial stack has a platform portion and a depression portion. The platform portion includes a partial first-type semiconductor layer, a light-emitting layer and a second-type semiconductor layer. The recess includes another partial first-type semiconductor layer. The second electrode is disposed on the platform portion, and the first electrode is disposed on the depression portion.

In an embodiment of the present invention, one of the above-mentioned first electrode portions is used as an etching barrier layer, and the first type semiconductor layer and the etching barrier layer have a through hole. The first electrode pad is disposed in the through hole.

In an embodiment of the present invention, the above light-emitting diode chip further includes an etching stopper layer. The etch stop layer is disposed on the first type semiconductor layer. The main body covers the etching barrier layer, and the first type semiconductor layer and the etching barrier layer have through holes. The first electrode pad is disposed in the through hole.

In an embodiment of the present invention, the above light-emitting diode device further includes a second connection metal layer. The second connecting metal layer is disposed on the first surface of the carrier substrate. The light-emitting diode chip is bonded and electrically connected to the second connecting metal layer on the carrier substrate through the first connecting metal layer.

In an embodiment of the present invention, the above-mentioned carrier substrate is a conductive substrate.

In an embodiment of the present invention, the above light emitting diode device further includes a second electrode pad. The second electrode pad is disposed on the second surface of the carrier substrate.

Based on the above, in the light-emitting diode chip, light-emitting diode device, and light-emitting diode module of the embodiments of the present invention, since the light-emitting layer and the first electrode are arranged in dislocation with each other, when the light-emitting layer emits light, most of the light beam Light will not be blocked by the first electrode. Moreover, due to the misplaced relationship between the first reflective layer and the second electrode, when the light-emitting layer emits light, most of the light beam will be reflected by the first reflective layer to emit light, and a small part of the light beam will be reflected by the second electrode to emit light. Light is emitted, so the light-emitting diode chip, light-emitting diode device and light-emitting diode module have good luminous efficiency. Moreover, when the light-emitting diode module is assembled, because the first electrode pad of the light-emitting diode module is of the same electrical property as the surrounding first-type semiconductor layer (the uppermost layer of the epitaxial stack), it can largely avoid In the wire-bonding process, when the wire of the first electrode pad is deflected and connected to the uppermost semiconductor layer of the epitaxial stack, the probability of short circuit and leakage due to the electrical difference between the wire and the semiconductor layer increases the margin of the process ( process window), it can also increase the stability of the light-emitting diode module during the assembly process.

An embodiment of the present invention provides a light-emitting diode wafer, including an epitaxial stack, a first electrode, and a second electrode. The epitaxial stack includes a first-type semiconductor layer, a light-emitting layer, a second-type semiconductor layer and an unintentionally doped semiconductor layer. The light emitting layer is located between the first type semiconductor layer and the second type semiconductor layer. The first type semiconductor layer is located between the unintentionally doped semiconductor layer and the light emitting layer. The first type semiconductor layer is doped with first type carriers. The second type semiconductor layer is doped with second type carriers. The electrical properties of the first-type carriers are different from those of the second-type carriers. In the epitaxial stack, at least the unintentionally doped semiconductor layer has a roughened structure overlapping the light-emitting layer. The first electrode is electrically connected with the first type semiconductor layer. The second electrode is electrically connected with the second type semiconductor layer.

In an embodiment of the present invention, in the epitaxial stack, the first-type semiconductor layer further has a roughened structure in which the light-emitting layers are overlapped.

In an embodiment of the present invention, the above-mentioned light-emitting layer has a first side and a second side opposite to each other. The first type semiconductor layer and the unintentionally doped semiconductor layer are located on the first side, and the second type semiconductor layer, the first electrode and the second electrode are located on the second side.

In an embodiment of the present invention, the above light-emitting diode chip further includes a reflective stack. The reflective stack is disposed on the second side and on the second-type semiconductor layer, and the reflective stack further includes a first insulating layer, a first reflective layer, a second reflective layer, and a second insulating layer. The first insulating layer is disposed between the first type semiconductor layer and the first reflective layer. The second reflective layer is disposed between the first reflective layer and the second insulating layer.

In an embodiment of the present invention, the above-mentioned orthographic projection of the first reflective layer on the first-type semiconductor layer is a first orthographic projection. The orthographic projection of the second reflection layer on the first type semiconductor layer is the second orthographic projection. The orthographic projection of the second electrode on the first-type semiconductor layer is a third orthographic projection. The third orthographic projection is misaligned with the first orthographic projection and the second orthographic projection.

In an embodiment of the present invention, the above-mentioned light-emitting diode chip further includes a third insulating layer, which is disposed on the first side and on the unintentionally doped semiconductor layer, and the third insulating layer has an overlapping arrangement of the light-emitting layer coarse structure.

In an embodiment of the present invention, the above-mentioned second electrode has a plurality of electrode parts separated from each other.

In an embodiment of the present invention, the above-mentioned first-type carriers are N-type carriers, and the second-type carriers are P-type carriers.

An embodiment of the present invention provides a light-emitting diode device, which includes the above-mentioned light-emitting diode chip, a first electrode pad, and a carrier substrate. The first electrode pad is disposed on one side of the light-emitting diode chip and is electrically connected with the first electrode. The carrier substrate is disposed on the other side of the light-emitting diode chip, and is electrically connected with the second electrode.

Based on the above, in the light-emitting diode wafer and the light-emitting diode device according to the embodiment of the present invention, when the light-emitting layer emits light beams, since the unintentionally doped semiconductor layer with a roughened structure overlaps with the light-emitting layer, The coarsening structure is located on the delivery path of the light beam. When the light beam goes out to the side of the light-emitting layer, it will be scattered by the roughened structure, so that the light-taking efficiency of the light-emitting diode chip and the light-emitting diode device increases.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

FIG. 1A is a schematic top view of a light emitting diode chip according to a first embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of the LED wafer in FIG. 1A . FIG. 1C is a schematic cross-sectional view of a light emitting diode device using the light emitting diode wafer shown in FIG. 1A . FIG. 1D is a schematic cross-sectional view of a light emitting diode module using the light emitting diode chip shown in FIG. 1A . FIG. 1E is a schematic top view of the light emitting diode module shown in FIG. 1D .

Please refer to FIG. 1A and FIG. 1B. In this embodiment, the light-emitting diode wafer 100 includes a growth substrate GS, an epitaxial stack ESL, first and second electrodes E1, E2, an etching stopper layer ECL, and an ohmic contact layer OCL. , a current blocking layer CBL, a first reflective stack RS1, and a first connection metal layer CML1. In the following paragraphs, the above-mentioned components and the arrangement relationship between the components will be described in detail.

The growth substrate GS is a substrate for growing an epitaxial stacked ESL, such as a sapphire (Sapphire) substrate, a gallium nitride (Gallium Nitride, GaN) substrate, a silicon carbide (Silicon Carbide, SiC) substrate, a silicon (Silicon) substrate , Gallium Arsenide (GaAs) substrate or other substrates suitable for growing epitaxial stacked ESL, the present invention is not limited thereto. In this embodiment, the growth substrate GS is a patterned substrate, for example, a periodic pattern (pattern is not shown) is provided on its surface, and is, for example, a patterned sapphire substrate. In some embodiments, the surface of the growth substrate GS used to prepare the growth of the epitaxial stack ESL, for example, is provided with an unintentionally doped semiconductor layer, which acts as a nucleation layer (Nucleation layer) or a buffer layer (Buffer Layer), and its The material is, for example, gallium arsenide (GaAs), gallium phosphide (GaP), aluminum indium gallium phosphide (AlInGaP), gallium nitride (GaN) or aluminum nitride (AlN), but not limited thereto. In some other embodiments, the growth substrate GS may not be provided with an unintentionally doped semiconductor layer, but not limited thereto.

The epitaxial stack ESL includes a first-type semiconductor layer SL1 , a light-emitting layer EL (also called an active layer) and a second-type semiconductor layer SL2 . The light emitting layer EL is located between the first type semiconductor layer SL1 and the second type semiconductor layer SL2. The first-type semiconductor layer SL1 is in contact with the growth substrate GW. In detail, the epitaxial stack ESL includes a platform portion Mesa and a depression portion CP. The platform portion Mesa includes a partial first-type semiconductor layer SL1 , a light-emitting layer EL, and a second-type semiconductor layer SL2 . The concave portion CP includes another partial first-type semiconductor layer SL1 .

The first-type and second-type semiconductor layers SL1 and SL2 are electrically opposite to each other. Specifically, the first-type and second-type semiconductor layers SL1 and SL2 are, for example, intentionally doped with N-type and P-type dopants in intrinsic semiconductors (i.e., first-type and second-type carriers, second-type carriers, The electrical properties of the first-type carriers are different from those of the second-type carriers), and they are used as N-type and P-type doped semiconductor layers respectively, among which the first-type and second-type semiconductor layers SL1, SL2 and the light-emitting layer EL are used The material of the intrinsic semiconductor may be gallium nitride (GaN), indium gallium nitride (InGaN), gallium phosphide (GaP), aluminum indium gallium phosphide (AlInGaP) or aluminum gallium nitride (AlGaN), but not in this limit. The structure of the luminescent layer EL is, for example, a multiple quantum well layer (Multiple Quantum Well, MQW) or a single quantum well layer (Single Quantum Well , SQW), but not limited thereto.

The materials of the first and second electrodes E1 and E2 are, for example, metal materials, such as chromium (Cr), aluminum (Al), titanium (Ti), nickel (Ni), platinum (Pt), gold (Au ) or combinations thereof, but not limited to. The first electrode E1 is disposed on the first-type semiconductor layer SL1 of the recess portion CP, and is in contact with the first-type semiconductor layer SL1 to be electrically connected thereto. The second electrode E2 is disposed on the second-type semiconductor layer SL2 of the platform portion Mesa, and is electrically connected to the second-type semiconductor layer SL2 through the ohmic contact layer OCL. The orthographic projection of the light emitting layer EL on the first-type semiconductor layer SL1 is misaligned with the orthographic projection of the first electrode E1 on the first-type semiconductor layer SL1 . In other words, the light emitting layer EL and the first electrode E1 do not overlap with each other.

Please refer to FIG. 1A, the first electrode E1 includes a main body MP and a plurality of fingers FP extending from it, wherein the number of the main body MP and the number of fingers FP is one and two respectively, in other not shown embodiments Among them, there may be more than two main body parts, each of which has a plurality of extending fingers. Those with ordinary knowledge in the technical field can set the quantity correspondingly according to requirements, and the present invention is not limited thereto. The fingers FP extend toward the edge E of the LED chip 100 , and there is a distance between the fingers FP and the edge E of the LED chip 100 . On the other hand, the second electrode E2 includes a plurality of electrode portions EDP separated from each other, and there is an interval between any two electrode portions EDP. A part of the electrode parts EDP is located on both sides of the fingers FP, and a part of the electrode parts EDP is located between the two fingers FP.

The material of the etching stop layer ECL can be chromium, aluminum, titanium, nickel, platinum, gold, tungsten (W), copper tungsten (CuW) or a combination thereof, and indium tin oxide. The function of the etch stop layer ECL will be described later. Please refer to FIG. 1B , in this embodiment, the etch stop layer ECL is disposed on the first-type semiconductor layer SL1 of the recess portion CP, and is in contact with the first-type semiconductor layer SL1 . The main body MP of the first electrode E1 covers the etch stop layer ECL.

The current blocking layer CBL is, for example, a material layer with a high resistance value, so that the current is less likely to pass through its position. In this embodiment, the material of the current blocking layer CBL can be, for example, a dielectric material, such as silicon oxide (SiO _x ), silicon nitride (SiN _x ) or a distributed Bragg reflector (Distributed Bragg Reflector, DBR), But not limited to this. The current blocking layer CBL is, for example, a patterned current blocking layer, and at least one current blocking layer CBL is disposed on the second-type semiconductor layer SL2 of the platform portion Mesa and is in contact with the second-type semiconductor layer SL2 .

The ohmic contact layer OCL is, for example, a material layer capable of forming an ohmic contact with the interface of the second-type semiconductor layer SL2, and its material is, for example, indium tin oxide (Indium Tin Oxide, ITO), nickel-gold alloy (Ni/Au), gold-beryllium alloy (Au/Be), gold-germanium alloy (Au/Ge) or other suitable metals or alloys, the present invention is not limited thereto. The ohmic contact layer OCL is disposed on the second-type semiconductor layer SL2 and the current blocking layer CBL of the platform portion Mesa, and is in contact with the second-type semiconductor layer SL2 and the current blocking layer CBL. Moreover, the ohmic contact layer OCL covers the current blocking layer CBL, so when the current flows to the ohmic contact layer OCL, it will avoid the area where the current blocking layer CBL is located, so that the current is more uniformly transmitted in the ohmic contact layer OCL, thus the ohmic contact layer OCL The contact layer OCL can also be regarded as a current spreading layer (Current Spreading Layer).

The first reflective stack RS1 includes a first insulating layer IL1 , a first reflective layer RL1 and a second insulating layer IL2 . The first insulating layer IL1 is disposed on the epitaxial stack ESL, the first and second electrodes E1 , E2 , the ohmic contact layer OCL, and the current blocking layer CBL, and covers the above elements. The first reflective layer RL1 is located between the first and second insulating layers IL1 and IL2. The first insulating layer IL1 has a plurality of first via holes V1. The first reflective layer RL1 has a plurality of second via holes V2. The second insulating layer IL2 has a plurality of third vias V3. The size of the second through hole V2 is larger than the size of the first through hole V1 or the third through hole V3 , and the sizes of the first through hole V1 and the third through hole V3 are substantially equal to each other. These first, second and third through holes V1 - V3 together expose the second electrode E2 . In more detail, a first through hole V1 and a third through hole V1, V3 are located within a range of a second through hole V2. In addition, the orthographic projection of the first reflective layer RL1 on the second-type semiconductor layer SL2 is misaligned with the orthographic projection of the second electrode E2 on the second-type semiconductor layer SL2 . That is, the first reflective layer RL1 itself does not overlap the second electrode E2. From another point of view, the orthographic projections of the second via holes V2 on the second-type semiconductor layer SL2 of the first reflective layer RL1 overlap with the orthographic projections of the second electrode E2 on the second-type semiconductor layer SL2 .

It should be noted that the first to third through holes do not necessarily have the above-mentioned size relationship. In other embodiments, the size of the second through hole can be equal to the size of the first through hole (the third through hole), and those skilled in the art can design the size of the through hole according to their own design requirements. The present invention does not This is not the limit.

The material of the first and second insulating layers IL1 and IL2 may be silicon dioxide, polyimide (PI), organic polymer material, organic glue or other suitable insulating materials, but not limited thereto.

The first reflective layer RL1 is a material layer with a reflective function, which can be a distributed Bragg reflector (Distributed Bragg Reflector, DBR), aluminum, aluminum-copper alloy (Al/Cu), silver (Ag), silver-copper alloy (Ag /Cu), gold, other suitable metals or alloys, or an insulating layer with a reflective function, wherein the distributed Bragg reflector is an optical stack in which multiple layers with high and low refractive index layers are stacked periodically, But not limited to this. In this embodiment, the first reflective layer RL1 can be aluminum, aluminum-copper alloy (Al/Cu), silver (Ag), silver-copper alloy (Ag/Cu), gold, other suitable metals or alloys but electrically floating. place. In other words, the first reflective layer RL1 does not communicate with the current path in the light emitting diode chip 100 .

The material of the first connection metal layer CML1 can be gold, gold-tin alloy (Au/Sn), tin-silver-copper alloy (Sn/Ag/Cu, SAC), tin-bismuth alloy (Sn/Bi), tin-silver alloy (Sn/ Ag), gold indium alloy (Au/In), bismuth (Bi), copper tungsten (CuW), tin, platinum, silver, nickel, titanium, aluminum, copper (Cu) or silver. The first connection metal layer CML1 is disposed on the second insulating layer IL2 and is electrically connected to the second electrode E2 through the first, second and third via holes V1 - V3 . In this embodiment, the first connection metal layer CML1 is a metal layer used to connect external components, and its specific function will be described later.

Based on the above, in the light-emitting diode chip 100 of this embodiment, since the orthographic projection of the light-emitting layer EL on the first-type semiconductor layer SL1 is misaligned with the orthographic projection of the first electrode E1 on the first-type semiconductor layer SL1, that is to say The light-emitting layer EL and the first electrode E1 are not overlapped, so when the light-emitting layer EL emits light beams L (including light beams L1 and L2), the light beam L1 is less likely to be blocked by the first electrode E1 and travel to the light-emitting diode chip 100 The light-emitting diode chip 100 is emitted from the direction of the first side SD1, wherein the first side SD1 is used as the light-emitting side. On the other hand, since the orthographic projections of the second through holes V2 of the first reflective layer RL1 on the second-type semiconductor layer SL2 overlap with the orthographic projections of the second electrode E2 on the second-type semiconductor layer SL2, that is to say, the first reflection The layer RL1 and the second electrode E2 are not overlapped. Therefore, when the light beam L2 exits toward the other side SD2 of the light-emitting diode chip 100, most of the light beam L2' in the light beam L2 will be absorbed by the first reflective layer RL1. Reflected and emitted toward the direction of the first side SD1, and the light beam L2 ″ will be reflected by the second electrode E2 again and emitted toward the direction of the first side SD1, so the light emitting diode chip 100 of this embodiment has good Luminous efficiency.

In addition, since the fingers FP extend toward the edge E of the light-emitting diode, the current can be transmitted to the light-emitting layer EL at different locations along the extending direction of the finger FP. Therefore, the light-emitting diode chip of this embodiment 100 can further improve the luminous efficiency.

Please refer to FIG. 1C. FIG. 1C is a light-emitting diode device 200 using the light-emitting diode chip 100 shown in FIG. 1A and FIG. The substrate CS, the first electrode pad EP1, the second electrode pad EP2, and the second connection metal layer CML2. It should be noted that only differences from FIG. 1A and related components mentioned in the following paragraphs are shown in FIG. 1C . For other components, please refer to the labels in FIG. 1A . In the following paragraphs, the above-mentioned components and the configuration of the components will be described in detail.

The light-emitting diode chip 100' is similar to the light-emitting diode chip 100, most of which are described in the above paragraphs, and will not be repeated here. The main difference is that the light-emitting diode chip 100' does not have a growth substrate GS. Also, the light emitting diode wafer 100' includes an insulating layer IL. The insulating layer IL covers the bottom surface BS1 , the side surface SS of the first-type semiconductor layer SL1 and part of the bottom surface BS2 of the second-type semiconductor layer SL2 . The insulating layer IL has a via hole V in common with the etch stop layer ECL.

The carrier substrate CS is, for example, a substrate for carrying the LED chip 100 ′, such as a silicon substrate, copper tungsten (CuW) substrate, molybdenum (Mo) substrate, gallium nitride substrate, sapphire (Sapphire) substrate or silicon carbide Substrate, but not limited to. Depending on the selection of different materials, the carrier substrate CS can be a conductive or non-conductive substrate. If the material is the aforementioned silicon, copper tungsten, molybdenum, gallium nitride, or silicon carbide, it is a conductive substrate. If the material is sapphire , it is a non-conductive substrate. The carrier substrate CS is disposed on one side SD2 of the light emitting diode chip 100', and has opposite first and second surfaces S1, S2, wherein the first surface S1 is a surface facing the light emitting diode chip 100', and the second surface is facing the light emitting diode chip 100'. The two surfaces S2 are surfaces facing away from the LED chip 100 ′.

The materials of the first and second electrode pads EP1 and EP2 are, for example, chromium, aluminum, titanium, nickel, platinum, copper, gold, tin, tin-silver-copper alloy, gold-tin alloy or combinations thereof. The first and second electrode pads EP1 and EP2 are respectively disposed on the first side SD1 and the second side SD2 of the LED chip 100'. The first electrode pad EP1 is disposed in the through hole V and contacts the etching barrier layer ECL, and is electrically connected to the first electrode E1 through the etching barrier layer ECL. The second electrode pad EP2 is disposed on the second surface S2 and is electrically connected to the carrier substrate CS.

The material selection of the second connection metal layer CML2 is similar to that of the first connection metal layer CML1 , which will not be repeated here. The second connection metal layer CML2 is disposed on the first surface S1 and is in contact with the carrier substrate CS and the first connection metal layer CML1 respectively. In this embodiment, the light emitting diode chip 100' can be bonded to the carrier substrate CS through the first metal connection layer CML1 and then through the second connection metal layer CML2.

Based on the above, in the light emitting diode device 200 of this embodiment, because the light emitting diode chip 100' similar to the embodiment of FIG. 1A is applied, it has good luminous efficiency.

Please refer to FIG. 1D. FIG. 1D is a light-emitting diode module 300 using the light-emitting diode chip 100 shown in FIG. 1A and FIG. 1B. The light-emitting diode device 300 includes the light-emitting diode device 200 of FIG. , The third and fourth electrode pads EP3, EP4. It should be noted that in FIG. 1D only differences from FIG. 1C and related components mentioned in the following paragraphs are shown. For other components, please refer to the labels in FIG. 1A and FIG. 1C . In the following paragraphs, the above-mentioned components and the configuration of the components will be described in detail.

The description of the light emitting diode device 200 is similar to the description in the above paragraphs, and will not be repeated here.

The circuit substrate CBS is, for example, a substrate having circuit layers (not shown) or electrode pads (not shown) thereon.

The material selection of the third and fourth electrode pads EP3 and EP4 is similar to that of the first electrode pad EP1 , which will not be repeated here. The third and fourth electrode pads EP3 and EP4 are disposed on the surface S of the circuit substrate CBS. And, one of the third and fourth electrode pads EP3 and EP4 is larger than the other. The third electrode pad EP3 is electrically connected to the first electrode pad EP1 through a wire W, and the fourth electrode pad EP4 can be electrically connected to the second electrode pad EP2 through a die-bonding material DB (such as solder paste or silver glue). connect. In other embodiments, the fourth electrode pad EP4 may directly contact the second electrode pad EP2 to be electrically connected to each other, and the present invention is not limited thereto. Therefore, the circuit substrate CBS can, for example, input a current I to the light-emitting diode device 200 through the third electrode pad EP3, and the current I passes through the wire W, the first electrode pad EP1, the etching barrier layer ECL, and the first electrode E1 in sequence, And the lateral transmission is carried out in the first-type semiconductor layer SL1. Then, it is transferred to the light-emitting layer EL approximately in the vertical direction, so that the light-emitting layer EL emits light, and flows back to the circuit substrate CBS through the fourth electrode pad EP4.

It should be noted that the above method of connecting the first and third electrode pads EP1 and EP3 through the wire W is, for example, a wire bonding process, and the connection between the wire W and the first and third electrode pads will form a crystal ball CYB (wire contact), and the crystal ball CYB will be welded to the first electrode pad EP1.

Based on the above, in the light emitting diode module 300 of this embodiment, because the light emitting diode chip 100' similar to the embodiment of FIG. 1A is applied, it has good luminous efficiency. In addition, please refer to FIG. 1E , since the first electrode pad EP1 is disposed in the through hole V, and the surrounding of the through hole V is the first type semiconductor layer SL1 having the same electrical properties as the first electrode pad EP1 . Therefore, when the light-emitting diode module 300 is assembled, it can be largely avoided that when the wire W is deflected during the wire-bonding process, the first electrode pad EP1 may interfere with the surrounding first-type semiconductor layer SL1 (the uppermost layer of the epitaxial stack). ) connection, and because the surrounding semiconductor layer is electrically identical to the first electrode pad EP1, the probability of short circuit and electric leakage can be largely avoided, and at the same time, the margin of the manufacturing process of the light emitting diode module 300 in the assembly process can be increased ( process window) and stability.

2A to 2W are flowcharts of manufacturing the LED wafer, LED device and LED module shown in FIG. 1A , FIG. 1C , and FIG. 1D .

Referring to FIG. 2A , a growth wafer GW is provided, wherein the material of the growth wafer GW is the same as that of the growth substrate GS, and will not be repeated here. In this embodiment, the growth wafer GW is a patterned wafer, such as a patterned sapphire wafer. For example, the growth wafer GW is provided with a plurality of growth blocks GP. In the following paragraphs or figures, a single growth block GP is used as an example to illustrate the growth of the light emitting diode chip 100 .

Referring to FIG. 2B , an epitaxial stack ESL is formed on the growth wafer GW, wherein the epitaxial stack ESL includes a first-type semiconductor layer SL1 , a light-emitting layer EL, and a second-type semiconductor layer SSL. That is to say, in the specific growth steps in FIG. 2B , the first-type semiconductor layer SL1 , the light-emitting layer EL, and the second-type semiconductor layer SSL are sequentially formed on the growth wafer GW. The methods of growing epitaxial stacked ESL are, for example, Metal Organic Chemical-Vapor Deposition (MOCVD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Sputtering method (sputter deposition method) or other suitable related epitaxy process is not limited thereto.

Referring to FIG. 2C , the epitaxial stack ESL is etched to remove part of the second-type semiconductor layer SL2 , part of the light-emitting layer EL and part of the first-type semiconductor layer SL1 to expose part of the first-type semiconductor layer SL1 and a local growth wafer GW (not shown in the exposure state) to form a platform portion Mesa and a depression portion CP. The etching method is, for example, dry chemical etching, wet chemical etching, physical etching or a combination of the above three etching methods, and the present invention is not limited thereto.

Referring to FIG. 2D , a patterned current blocking layer CBL is formed on the second-type semiconductor layer SL2 of the platform portion Mesa.

Referring to FIG. 2E , an ohmic contact layer OCL is formed on the second-type semiconductor layer SL2 and covers the patterned current blocking layer CBL.

Referring to FIG. 2F , an etch stop layer ECL is formed on the first-type semiconductor layer SL1 of the recessed portion CP.

2G, the first electrode E1 and the second electrode E2 are respectively formed on the first-type semiconductor layer SL1 and the second-type semiconductor layer SL2, wherein the first electrode E1 includes at least one main body MP and a plurality of fingers FP , the main body MP covers the etch stop layer ECL. The second electrode E2 includes a plurality of electrode parts EDP separated from each other.

2H, the first insulating layer IL1 of the first reflective stack RS1 is formed on the epitaxial stack ESL, the first and second electrodes E1, E2, and the partial first insulating layer IL1 is etched to make the first insulating layer The layer IL1 has a plurality of first vias V1. The etching method is the same as the method of etching the epitaxial stack ESL, and will not be repeated here.

Referring to FIG. 2I , the first reflective layer RL1 of the first reflective stack RS1 is formed on the first insulating layer IL1 , wherein the first reflective layer RL1 has a plurality of second through holes V2 . It is worth mentioning that the method of forming the first reflective layer RL1 is a lift-off process. In detail, a photoresist layer (not shown) is coated on the first insulating layer IL1 first. Then, the local area of the photoresist layer is exposed and developed to remove the local area of the photoresist layer and define the area other than the size, number and position of the second via holes V2 and expose the first insulating layer IL1. Next, the material of the first reflective layer RL1 is deposited on the exposed photoresist layer and the exposed first insulating layer IL1 in areas other than the photoresist layer. , and finally form the first reflective layer RL1 having a plurality of second via holes V2.

Referring to FIG. 2J, the second insulating layer IL2 of the first reflective stack RS1 is formed on the first reflective layer RL1, and part of the second insulating layer IL2 is etched so that the second insulating layer IL2 has a plurality of third through holes V3. . The etching method is the same as the method of etching the epitaxial stack ESL, and will not be repeated here. So far, the first reflective stack RS1 has been formed.

Alternatively, the second insulating layer IL2 is etched by wet etching or dry etching or a combination thereof. In addition, in other embodiments, the first and third through holes V1 and V3 may also be formed together. That is to say, the first via hole V1 may not be etched on the first insulating layer IL1 first, and in the step of FIG. The first and third through holes V1 and V3 are not limited in the present invention.

Referring to FIG. 2K, the first connection metal layer CML1 is formed on the first reflective stack RS1, and the first connection metal layer CML1 is filled into the first, second, and third via holes V1~V3, so that the first The connection metal layer CML1 is electrically connected to the second electrode E2. So far, the growth wafer GW has gone through the above steps to form a light emitting diode wafer WF having a plurality of light emitting diode chips 100 .

Referring to FIG. 2L , firstly, two first positioning elements PE1 are arranged on both sides of the plurality of light emitting diode chips 100 inside the light emitting diode wafer WF. Then, the dicing process (Scribe) is performed on the light-emitting diode wafer WF, that is, multiple scribes C are formed in the epitaxial stack ESL and the growth wafer GW, and part of the growth wafer GW is removed for dicing. The blocks GP of these growing wafers GW are produced, and each block GP of the growing wafer GW includes, for example, a light emitting diode chip 100 .

Referring to FIG. 2M, the light emitting diode wafer WF is split along these cuts C, so that the light emitting diode wafer WF is split along these cuts C, so that these light emitting diode wafers 100 separations. In this embodiment, the splitting process can be performed by a splitting device (not shown), such as a chopper, but not limited thereto. The local growth wafer GW of each growth wafer block GP serves as the growth substrate GS of the light emitting diode chip 100 . So far, the light emitting diode chips 100 have been substantially fabricated. It should be noted that the cross section of the light emitting diode chip 100 in FIG. 2M is schematically shown, please refer to the cross section in FIG. 1A for the specific cross section. In addition, in other embodiments, a wafer thinning process may be performed before the splitting process to reduce the thickness of the growth substrate GS on which the wafer GW is grown.

Next, the manufacturing method of the light emitting diode device 200 will be described in the following paragraphs.

Continuing the steps after the dicing process in FIG. 2L , please refer to FIG. 2N , a carrier wafer CW is provided, wherein the carrier wafer CW also has a plurality of preset configuration regions PD corresponding to a plurality of growth blocks GP. In each default configuration area PD, a second connection metal layer CML2 is provided. Two or at least one second positioning element PE2 is disposed at a diagonal position of the second connection metal layer CML2. Two third positioning elements PE3 are also disposed on both sides of the preset configuration areas PD, wherein the two third positioning elements PE3 respectively correspond to the two first positioning elements PE1.

Referring to FIG. 2O, the light-emitting diode wafer WF in FIG. 2L is aligned and bonded with the carrier wafer CW in FIG. 2N, so that the multiple second connection metal layers CML2 on the carrier wafer CW correspond It is bonded and electrically connected to a plurality of first metal connection layers CML1 in a plurality of growth blocks GP, wherein the light emitting diode wafer WF and the first, second and third positioning elements PE1~ on the carrier wafer CW PE3 is used for assisting the alignment so that the second connection metal layers CML2 can be accurately bonded to the first metal connection layers CML1 . In this embodiment, for example, the first positioning element PE1 is not engaged with the third positioning element PE3. In other embodiments, the first positioning element PE1 can be engaged with the third positioning element PE3, and the present invention is not limited thereto.

Referring to FIG. 2P , the growth wafer GW is removed, wherein the method of removing the growth wafer GW includes a laser lift-off process (Laser Lift-off Process) or a wet chemical etching process. During the laser lift-off process, the high temperature of the laser will reduce the metal ions in the epitaxial stack EPL to metal. Therefore, after the laser lift-off process, an etching process, such as a wet chemical etching process, can be performed on the surface of the epitaxial stack EPL to remove metal, such as gallium. So far, the LED chips 100 on the LED wafer WF are transferred and bonded to the carrier wafer CW.

It should be noted that the above-mentioned FIG. 2N to FIG. 2P is a continuation of the steps in FIG. 2L, that is, a plurality of light-emitting diode chips 100 are transferred to a plurality of preset configuration areas PD on the carrier wafer CW at one time, and then removed. The entire growing wafer GW is a many-to-many transfer step. In other unshown embodiments, the steps in FIG. 2O can also be continued, that is, after separating the light emitting diode chips 100, they are then transferred to the second metal connection layer CML2 one by one, that is, one-to-one The transfer bonding step of the light-emitting diode wafer 100 is removed by laser lift-off process or wet chemical etching process, and the metal, such as gallium metal, is removed respectively. (Gallium), the present invention is not limited thereto.

In the following paragraphs, the light emitting diode chip 100 in a predetermined configuration area PD will be described.

Please refer to FIG. 2Q. Since the epitaxial stack EPL was previously formed as a periodic pattern on the surface of the growth wafer GW, when the growth wafer GW is removed, there will actually be left on the surface of the first-type semiconductor layer SL1. Periodic structure PS. In this step, a thinning process is first performed on the first-type semiconductor layer SL1 of the epitaxial stack EPL. The method of the thinning process is, for example, performing a dry etching process or a wet chemical etching process to remove a part of the first-type semiconductor layer SL1 and the unintentionally doped semiconductor layer to expose the surface S3 of the first-type semiconductor layer SL1 . Next, a surface roughening process is performed on the surface S3. The method of the surface roughening process is, for example, performing a wet chemical etching process to form a non-periodic rough structure UPS on the surface S3.

Referring to FIG. 2R , an etching process is performed around the first-type semiconductor layer SL1 to expose a part of the first insulating layer IL1 .

In other unshown embodiments, the steps in FIG. 2Q can also be continued. After a thinning process is performed to remove the local first-type semiconductor layer SL1 and unintentionally doped semiconductor layers, the continuation of FIG. In step 2R, an etching process is performed around the first-type semiconductor layer SL1 to expose a part of the first insulating layer IL1 , and then a surface roughening process is performed on the surface S3 . The method of the surface roughening process is, for example, performing a wet chemical etching process to form a non-periodic rough structure UPS on the surface S3.

Referring to FIG. 2S , an insulating layer IL is formed on the first-type semiconductor layer SL1 and the first insulating layer IL1 , wherein the insulating layer IL covers the bottom and side surfaces of the first-type semiconductor layer SL1 and part of the surface of the first insulating layer IL1 . Furthermore, a dry etching process or a wet chemical etching process is performed on the positions of the main body MP and the etch stop layer ECL to form the via hole V and remove the first type semiconductor layer SL1 and part of the etch stop layer ECL in the via hole V. The function of the etch stop layer ECL is to prevent the dry etching process from etching the main portion MP of the first electrode E1. Side surfaces of the etch stop layer ECL are substantially aligned with side surfaces of the insulating layer IL. Alternatively, the insulating layer IL is disposed in the through hole V and exposes part of the etch stop layer ECL.

Referring to FIG. 2T , a first electrode pad EP1 is formed in the through hole V, so that the first electrode pad EP1 is in contact with the etch barrier layer ECL. The first electrode pad EP1 can be electrically connected to the first-type semiconductor layer SL1 through the etch stop layer ECL and the first electrode E1 .

Referring to FIG. 2U , a second electrode pad EP2 is formed on the second surface S2 of the carrier wafer CW. So far, a plurality of light emitting diode devices 200 have been formed on the carrier wafer CW, and one light emitting diode device 200 is disposed in each preset configuration area PD.

Referring to FIG. 2V , the dicing and cleaving process is performed on the carrier wafer CW carrying a plurality of light emitting diode devices 200 to separate the light emitting diode devices 200 from each other. So far, the light emitting diode device 200 has been substantially completed.

Next, the manufacturing method of the light emitting diode module 300 will be described in the following paragraphs.

Continuing the steps in FIG. 2V , please refer to FIG. 2W , providing a circuit substrate CBS, and forming third and fourth electrode pads EP3 and EP4 on the surface S of the circuit substrate CBS.

Please refer to Figure 2X, the third and fourth electrode pads EP3 and EP4 are electrically connected to the first and second electrode pads EP1 and EP2 respectively. A die-bonding material (such as silver glue, solder paste or other suitable metal materials) is formed on one of the pads EP3 and EP4 (for example, the fourth electrode pad EP4 ), and a die-bonding process is performed. Next, the second electrode pad EP2 of the light-emitting diode device 200 is bonded to the fourth electrode pad EP4 formed with a crystal-bonding material, and the first electrode pad EP1 of the light-emitting diode device 200 is bonded in a wire bonding process. It is connected with the third electrode pad EP3. So far, the light emitting diode module 300 has been substantially completed.

It must be noted here that the following embodiments continue to use part of the content of the previous embodiments, omitting the description of the same technical content. For the same component names, reference can be made to part of the content of the previous embodiments, and the following embodiments will not be repeated.

FIG. 3A is a schematic top view of a light-emitting diode chip according to a second embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of the LED wafer in FIG. 3A . FIG. 3C is a schematic cross-sectional view of an LED device using the LED wafer shown in FIG. 3A . FIG. 3D is a schematic cross-sectional view of a light emitting diode module using the light emitting diode chip shown in FIG. 3A . FIG. 3E is a schematic top view of the light emitting diode module shown in FIG. 3D .

The light emitting diode wafer 100a of FIG. 3A and FIG. 3B is substantially similar to the light emitting diode wafer 100 of FIG. The reflective layer RL2, wherein the second reflective layer RL2 is a material layer with a reflective function, which can be a distributed Bragg reflector (Distribute Bragg Reflector, DBR), aluminum, aluminum-copper alloy (Al/Cu), silver (Ag), Silver-copper alloy (Ag/Cu), gold, other suitable metals or alloys, or an insulating layer with reflective function, where the distributed Bragg reflector is a stack of layers with high and low refractive index layers stacked periodically An optical stack, but not limited to. In this embodiment, the second reflective layer RL2 can be aluminum, aluminum-copper alloy (Al/Cu), silver (Ag), silver-copper alloy (Ag/Cu), gold, other suitable metals or alloys but electrically floating. place. In other words, the second reflective layer RL2 does not communicate with the current path in the light emitting diode chip 100 . The first reflective stack RS1a of this embodiment includes two reflective layers.

In detail, the second reflective layer RL2 is disposed on the first reflective layer RL1 and between the first and second insulating layers IL1 and IL2. The second reflective layer RL2 has a plurality of fourth through holes V4, and the orthographic projections of the fourth through holes V4 on the second-type semiconductor layer SL2 overlap with the orthographic projections of the second electrode E2 on the second-type semiconductor layer SL2. In other words, the second reflective layer RL2 and the second electrode E2 do not overlap with each other.

In addition, in this embodiment, the size of the fourth through hole V4 is greater than the size of any of the first, second and third through holes V1-V3, and one first, one second and one third through hole V1 ~V3 is located within the range of a fourth via V4, and the size relationship of the other vias is similar to that shown in FIG. 1A , which will not be repeated here. Moreover, the first to fourth through holes V1 - V4 jointly expose the second electrode E2 . The first connecting metal layer CML1 is electrically connected to the second electrode E2 through the first to fourth vias V1 - V4 .

In other embodiments, the size of the fourth through hole can be equal to the size of the first, second or third through hole. Those skilled in the art can design the size of the through hole according to their own design requirements. The present invention does not It is not limited to the relationship between the size of the above-mentioned through holes.

Based on the above, compared with the LED chip 100 in FIG. 1A , although most of the light beams can be reflected by the first reflective layer RL1 , a small part of the light beams will still pass through the first reflective layer RL1 . In the light-emitting diode chip 100a of this embodiment, the first reflective stack RS1a is provided with a second reflective layer RL2 in addition to the first reflective layer RL1, and the second reflective layer RL2 can further penetrate this small part. The light beams of the first reflective layer RL1 are further reflected and directed towards the direction of the first side SD1, so the light emitting diode chip 100a has higher luminous efficiency.

Please refer to FIG. 3C, the light emitting diode device 200a of FIG. 3C is substantially similar to the light emitting diode device 200 of FIG. ', the light emitting diode chip 100a' is similar to the light emitting diode chip 100a, the main difference is that: the light emitting diode chip 100a' includes an insulating layer IL. The insulating layer IL covers the bottom surface BS1 of the first-type semiconductor layer SL1 and the bottom surface BS3 of the first insulating layer IL1 . The insulating layer IL, the first type semiconductor layer SL1 and the etching stopper layer ECL have a through hole Va in common. In addition, in this embodiment, the first electrode pad EP1 does not fill the entire through hole Va, and there is a gap between it and the first-type semiconductor layer SL1 .

In other unshown embodiments, the insulating layer IL may further extend into the through hole V and cover part of the etch barrier layer ECL, and the first electrode pad EP1 does not fill the entire through hole Va, which is similar to the first type semiconductor There are gaps between the layers SL1.

Please refer to FIG. 3D, the light-emitting diode module 300a in FIG. 3D is roughly similar to the light-emitting diode module 300 in FIG. body device 200a.

Based on the above, compared with the light emitting diode device 200 and the light emitting diode module 300 in Fig. 1C and Fig. 1D, the light emitting diode device 200a and the light emitting diode module 300a in Fig. 3C and Fig. 3D have Higher luminous efficiency.

4A to 4Y are flowcharts of manufacturing the LED wafer, LED device, and LED module shown in FIG. 3A , FIG. 3C , and FIG. 3D .

FIGS. 4A to 4I are substantially similar to the related descriptions of FIGS. 2A to 2I , and are not repeated here. Continuing from FIG. 4I , please refer to FIG. 4J , the second reflective layer RL2 of the first reflective stack RS1a is formed on the first reflective layer RL1 , wherein the second reflective layer RL2 has a plurality of fourth through holes V4 . Similarly, the method of forming the second reflective layer RL2 is also similar to the method of forming the first reflective layer RL1 , which is a lift-off process, and will not be repeated here.

FIG. 4K to FIG. 4L are substantially similar to the relevant descriptions of FIG. 2J to FIG. 2K , and will not be repeated here. So far, the growth wafer GW has gone through the above steps to form a light emitting diode wafer WFa having a plurality of light emitting diode chips 100a.

FIG. 4M to FIG. 4N are substantially similar to the relevant descriptions in FIG. 2L to FIG. 2M , and are not repeated here. So far, the light emitting diode chips 100a have been substantially fabricated.

Next, the manufacturing method of the light-emitting diode device 200a will be described in the following paragraphs.

Continuing the steps after the dicing process in FIG. 4M , referring to FIG. 4O , a carrier wafer CW is provided, wherein the entire surface of the carrier wafer CW is formed with a second connection metal layer CML2 , and a plurality of third positioning elements PE3 are formed thereon.

Please refer to FIG. 4P, the light emitting diode wafer WFa of FIG. 4M is aligned and bonded with the carrier wafer CW of FIG. It is bonded to the second connection metal layer CML2.

Please refer to FIG. 4Q, the growth substrate GW of the light-emitting diode wafer WFa will be removed and the metal, such as gallium metal ( Gallium), exposing the epitaxial stack EPL.

4R to 4W are substantially similar to the relevant descriptions of FIGS. 2Q to 2V , and will not be repeated here. So far, the light emitting diode devices 200a have been substantially completed.

Next, the manufacturing method of the light emitting diode module 300a will be described in the following paragraphs.

FIG. 4X and FIG. 4Y are substantially similar to the related descriptions of FIG. 2W to FIG. 2X , and are not repeated here. So far, the light emitting diode modules 300a have been substantially completed.

5A is a schematic cross-sectional view of a light-emitting diode chip according to a third embodiment of the present invention. FIG. 5B is a schematic top view of the LED chip in FIG. 5A . FIG. 5C is a schematic cross-sectional view of a light emitting diode device using the light emitting diode wafer shown in FIG. 5A . FIG. 5D is a schematic cross-sectional view of a light emitting diode module using the light emitting diode chip shown in FIG. 5A . FIG. 5E is a schematic top view of the light emitting diode module shown in FIG. 5D .

The light emitting diode chip 100b of FIG. 5A and FIG. 5B is substantially similar to the light emitting diode chip 100 of FIG. Two reflection stacks RS2, first and second current conducting layers CCL1, CCL2. In the following paragraphs, the above-mentioned components and the arrangement relationship between the above-mentioned components will be described in detail.

The second reflective stack RS2 includes a third insulating layer IL3 , a third reflective layer RL3 and a fourth insulating layer IL4 . The third reflective layer RL3 is disposed between the third and fourth insulating layers IL3 and IL4. The third insulating layer IL3 is disposed on the first reflective stack RS1 and is in contact with the first reflective layer RL1 or the second reflective layer RL2 of the first reflective stack RS1 . The third insulating layer IL3 has a plurality of fourth via holes V4. The third reflective layer RL3 has a plurality of fifth via holes V5. The fourth insulating layer IL4 has a plurality of sixth via holes V6. The size of the fifth through hole V5 is greater than the size of the fourth through hole V4 or the sixth through hole V6 , and the sizes of the fourth through hole V4 and the sixth through hole V6 are substantially equal to each other. In more detail, a fourth through hole V4 and a sixth through hole V6 fall within a range of a fifth through hole V5. The orthographic projections of the fourth through holes V4 of the third reflective layer RL3 on the second-type semiconductor layer SL2 overlap with the orthographic projections of a part of the second electrode E2 on the second-type semiconductor layer SL2 . In addition, in this embodiment, the first-type semiconductor layer SL1 and the growth substrate GS have an inclined plane IS, and a part of the first and second reflective stacks RS1 and RS2 are conformally disposed on the inclined plane IS.

In other embodiments, the size of the sixth through hole may be equal to the size of the fifth and seventh through holes. The size of the sixth through hole can also be equal to the size of the first, second, and third through holes. Those skilled in the art can design the size of the through holes according to their own design requirements, and the present invention is not limited thereto.

The selection of materials for the third and fourth insulating layers IL3 and IL4 is similar to that of the first and second insulating layers IL1 and IL2 , which will not be repeated here. The third reflective layer RL3 is a material layer with a reflective function, which can be a distributed Bragg reflector (Distributed Bragg Reflector, DBR), aluminum, aluminum-copper alloy (Al/Cu), silver (Ag), silver-copper alloy (Ag /Cu), gold, other suitable metals or alloys, or an insulating layer with a reflective function, wherein the distributed Bragg reflector is an optical stack in which multiple layers with high and low refractive index layers are stacked periodically, But not limited to this. In this embodiment, the third reflective layer RL3 can be aluminum, aluminum-copper alloy (Al/Cu), silver (Ag), silver-copper alloy (Ag/Cu), gold, other suitable metals or alloys but electrically floating. place. In other words, the third reflective layer RL3 does not communicate with the current path in the light emitting diode chip 100b.

The first and second current conducting layers CCL1 and CCL2 are disposed between the first and second reflective stacks RS1 and RS2. Specifically, the first and second current conduction layers CCL1 and CCL2 are located on the same layer, and the first current conduction layer CCL1 is disposed on and overlapped with the first electrode E1, while the second current conduction layer CCL2 is disposed on the second electrode E2 on and overlapping it. The first current conducting layer CCL1 extends into the first, second and third via holes V1 - V3 to contact and be electrically connected to the first electrode E1 . The second current conducting layer CCL2 also extends into the first, second and third via holes V1 - V3 , and is in contact with and electrically connected to the second electrode E2 .

On the other hand, the first connection metal layer CML1 is disposed on the second reflective stack RS2, and is electrically connected to the second current conducting layer CCL2 through the fourth, fifth and sixth vias V4-V6 therein, and Indirectly electrically connected with the second electrode E2.

In addition, please refer to FIG. 5A , in this embodiment, the first electrode E1b includes a plurality of first electrode parts EDP1 separated from each other, and the second electrode EP2 includes a plurality of second electrode parts EDP2 separated from each other. The second electrode portions EDP2 surround the first electrode portions EDP1. Compared with the light-emitting diode chip 100 in FIG. 1A, since the first electrode E1b of the light-emitting diode chip 100b adopts the design of the separated first electrode part EDP1, the first electrode is separated from the light-emitting diode chip E1b. The proportion of area occupied by the light emitting diode chip 100b is lower, so the light emitting diode chip 100b has higher luminous efficiency. In addition, one of the first electrode parts EDP1 functions as an etching stopper layer ECL.

Based on the above, compared with the light-emitting diode chip 100 in FIG. 1A, in the light-emitting diode chip 100b of this embodiment, since the second reflective stack RS2 is further provided on the first reflective stack RS1, the second The third reflective layer RL3 in the reflective stack RS2 can further reflect part of the light beams that have passed through the first reflective layer RL1, and shoot to the direction of the first side SD1, so the light emitting diode chip 100b has a higher luminous efficiency. Moreover, because the second reflective stack RS2 has a reflective layer RL3 sandwiched between two insulating layers IL3 and IL4 , it can provide a better protection function.

Please refer to FIG. 5C, the light emitting diode device 200b of FIG. 5C is substantially similar to the light emitting diode device 200 of FIG. ', the light emitting diode chip 100b' is similar to the light emitting diode chip 100b, the main difference is that: the light emitting diode chip 100b' includes an insulating layer IL and a protective layer PL. The insulating layer IL covers the first type semiconductor layer SL1, the first reflective stack RS1, and exposes the first electrode part EDP1 serving as the etching stopper layer ECL. The protection layer PL covers the insulating layer IL and the first-type semiconductor layer SL1. The insulating layer IL and the protection layer PL share a through hole V', and the first electrode pad EP1 is disposed in the through hole V' and spaced from the insulating layer IL and the protection layer PL by a distance. In addition, since the first-type semiconductor layer SL1 , the insulating layer IL and the protection layer PL have a non-periodic structure UPS, it is helpful for light extraction.

Please refer to FIG. 5D, the light emitting diode module 300b in FIG. 5D is substantially similar to the light emitting diode module 300 in FIG. 1D, the main difference is that the light emitting diode module 300a of FIG. body device 200b.

Based on the above, compared with the light emitting diode device 200 and the light emitting diode module 300 in Fig. 1C and Fig. 1D, the light emitting diode device 200b and the light emitting diode module 300b in Fig. 5C and Fig. 5D have Higher luminous efficiency.

6A to 6S are flowcharts of manufacturing the LED wafer, LED device, and LED module shown in FIG. 5A , FIG. 5C , and FIG. 5D .

The descriptions of FIG. 6A and FIG. 6B are substantially similar to the related descriptions of FIG. 2A and FIG. 2B , and will not be repeated here.

Referring to FIG. 6C , the epitaxial stack ESL is etched to remove part of the second-type semiconductor layer SL2 , part of the light-emitting layer EL and part of the first-type semiconductor layer SL1 to form a plurality of platform portions Mesa and a plurality of depressions. Part CP, the etching method is, for example, dry chemical etching, wet chemical etching, physical etching or a combination of the above three etching methods, and the present invention is not limited thereto.

Please refer to FIG. 6D , the dicing process (Scribe) is performed on the edge of the growth block EP to cut through the first-type semiconductor layer SL1 and the local growth wafer GW, so that the first-type semiconductor layer SL1 and the growth wafer GW have a common A bevel IS.

Referring to FIG. 6E , a patterned current blocking layer CBL, an ohmic contact layer OCL, and a second electrode E2 are sequentially formed on a part of the plurality of platform parts Mesa, and an ohmic contact layer OCL is formed on another part of these platform parts Mesa. , and the first electrode E1 is formed on the plurality of recesses CP, wherein the first and second electrodes E1 and E2 respectively have a plurality of first electrode portions EDP1 separated from each other and a plurality of second electrode portions EDP2 separated from each other.

Please refer to FIG. 6F , the description of FIG. 6F is substantially similar to that of FIG. 2H to FIG. 2J , and will not be repeated here. The main difference is that a part of the first reflective stack RS1 is formed on the slope IS.

Referring to FIG. 6G, the first and second current conducting layers CCL1 and CCL2 are formed on the first reflective layer RS1, wherein the first and second current conducting layers CCL1 and CCL2 overlap with the first and second electrodes E1 and E2 respectively. Moreover, the first current conducting layer CCL1 is electrically connected to a plurality of separated first electrode parts EDP1 and the second current conducting layer CCL2 is electrically connected to a plurality of separated second electrode parts EDP2.

Referring to FIG. 6H , forming the second reflective stack RS2 on the first reflective stack RS1, wherein this step includes: first forming the third insulating layer IL3 of the second reflective stack RS2 on the first reflective stack RS1, On the first and second current conducting layers CCL1 , CCL2 , and on the growth wafer GW, the third insulating layer IL3 has a plurality of fifth through holes V5 . Then form the third reflective layer RL3 of the second reflective stack RS2 on the third insulating layer IL3, wherein the third reflective layer RL3 has a plurality of sixth through holes V6, and the method of forming the third reflective layer RL3 is similar to that of the first reflective layer. The layer RL1 will not be described in detail here. Finally, a fourth insulating layer IL4 of the second reflective stack RS2 is formed on the third reflective layer RL3, wherein the fourth insulating layer IL4 has a plurality of seventh through holes V7. So far, the formation of the second reflective stack RS2 has been completed.

Referring to FIG. 6I, the first connection metal layer CML1 is formed on the second reflective stack RS2, and the first connection metal layer CML1 is filled into the fifth, sixth, and seventh via holes V5~V7, so that the first The connecting metal layer CML1 is electrically connected to the second electrode E2 through the second current conducting layer CCL2, and a part of the first connecting metal layer CML1 covers the slope IS. So far, the growth wafer GW has gone through the above steps to form a light emitting diode wafer WFb having a plurality of light emitting diode chips 100b. However, if a single light emitting diode chip 100b is to be formed, it can be fabricated in the manner shown in FIG. 2L to FIG. 2M , which will not be repeated here.

Next, the manufacturing method of the light-emitting diode device 200b will be described in the following paragraphs.

Continuing from FIG. 6I, please refer to FIG. 6J and FIG. 6K. The steps in FIG. 6J and FIG. 6K are similar to those in FIG. 4O and FIG. 4P. In FIG. 6J, the entire second connection metal layer CML2 is formed on the carrier wafer CW. No more details are given here, and for simplicity, FIG. 6K is a schematic illustration of the light-emitting diode device 100b in a single growth block.

Please refer to FIG. 6L , the growth substrate GW of the light-emitting diode device 100b is removed and the surface metal, such as gallium metal (Gallium metal), is removed through a laser lift-off process or a wet chemical etching process. ), exposing the surface of the first-type semiconductor layer SL1 of the epitaxial stack EPL. Similarly, since the epitaxial stack EPL is a pattern previously formed on the growth wafer GW, when the growth wafer GW is removed, there will actually be a periodic structure PS on the surface of the first-type semiconductor layer SL1 .

Referring to FIG. 6M , an etching process is first performed on the periphery of the first-type semiconductor layer SL1 and the first reflective stack RS1 . Next, an etching process is performed on a first electrode portion EDP1 expected to be used as an etch barrier layer ECL in the first electrode E1 to form a via hole Vb.

Referring to FIG. 6N , an insulating layer IL is formed on the first-type semiconductor layer SL1 , the etching stopper layer ECL and the first reflective stack RS1 .

Referring to FIG. 6O , a wet chemical etching process is performed on the first-type semiconductor layer SL1 to form a non-periodic rough structure UPS on its surface.

Referring to FIG. 6P, a protection layer PL is formed on the insulating layer IL, the etch stop layer ECL and the first reflective stack RS1. Furthermore, an etching process is performed on the position of the etching stopper layer ECL to etch part of the protection layer PL and the insulating layer IL to expose part of the etching stopper layer ECL.

Referring to FIG. 6Q , the first electrode pad EP1 is formed at the position of the etching barrier layer ECL, so that the first electrode pad EP1 is electrically connected to the etching barrier layer ECL. Furthermore, a second electrode pad EP2 is formed on the other surface of the carrier wafer CW. So far, a plurality of light emitting diode devices 200b have been formed on the carrier wafer CW, and one light emitting diode device 200b is disposed in each preset configuration area PD. Then, a dicing process may be performed on the carrier wafer CW to separate the light emitting diode devices 200b from each other.

Next, the manufacturing method of the light emitting diode module 300b will be described in the following paragraphs.

Please refer to FIG. 6R and FIG. 6S . The descriptions in FIG. 6R and FIG. 6S are substantially similar to the steps in FIG. 2W and FIG. 2V , and will not be repeated here. So far, the light emitting diode module 300b has been substantially completed.

It should be noted that, in the embodiment of the present invention, the light emitting diode devices 200, 200a, 200b are all shown as being provided with the second electrode pad EP2. However, in other unshown embodiments, if the material of the carrier substrate CW is selected as a conductive substrate that can conduct electricity, then the second electrode pad EP2 can be omitted.

To sum up, in the light emitting diode chip, light emitting diode device, and light emitting diode module of the embodiment of the present invention, since the light emitting layer and the first electrode are arranged in a misaligned position, when the light emitting layer emits light, most The light beam will not be blocked by the first electrode to emit light. Moreover, due to the misplaced relationship between the first reflective layer and the second electrode, when the light-emitting layer emits light, most of the light beam will be reflected by the first reflective layer to emit light, and a small part of the light beam will be reflected by the first reflective layer. After the through hole (such as the second through hole) emits light, it is reflected by the second electrode to emit light. Therefore, the light emitting diode chip, light emitting diode device and light emitting diode module have good luminous efficiency. Moreover, when the light-emitting diode module is assembled, because the first electrode pad of the light-emitting diode module is of the same electrical property as the surrounding first-type semiconductor layer (the uppermost layer of the epitaxial stack), it can largely avoid In the wire-bonding process, when the wire of the first electrode pad is deflected and connected to the uppermost semiconductor layer of the epitaxial stack, the probability of short circuit and leakage due to the electrical difference between the wire and the semiconductor layer increases the margin of the process ( process window), it can also increase the stability of the light-emitting diode module during the assembly process.

7A is a schematic cross-sectional view of a light emitting diode device according to a fourth embodiment of the present invention. FIG. 7B is a schematic top view of the embodiment of FIG. 7A .

Please refer to FIG. 7A and FIG. 7B. In this embodiment, the light-emitting diode device 200c includes a light-emitting diode wafer 100c, a carrier substrate CS, a first electrode pad EP1, a second electrode pad EP2, and a first connection metal layer CML1. , the second connection metal layer CML2. The light-emitting diode wafer 100c includes an epitaxial stack ESLc, first and second electrodes E1, E2, and a reflective stack RSLc, wherein the epitaxial stack ESLc further includes first-type and second-type semiconductor layers SL1, SL2, light emitting layer EL, unintentionally doped (Unintentionally Doped) semiconductor layer US, wherein the material of the unintentionally doped semiconductor layer US includes, for example, gallium nitride, aluminum gallium nitride, indium gallium nitride or aluminum nitride, or is The present invention is not limited to other materials whose crystal lattices are not much different from those of the first-type and second-type semiconductor layers SL1 and SL2 . The reflective stack RSLc includes first and second reflective layers RL1 and RL2 and first and second insulating layers IL1 and IL2. In addition, the LED chip 100c further includes insulating layers IL, IL', a current blocking layer CBL, and an ohmic contact layer OCL. Referring to FIG. 7A , the second electrode E2 includes a plurality of electrode parts EDP2 separated from each other. The configuration relationship among the above elements will be described in detail in the following paragraphs.

Referring to FIG. 7A and FIG. 7B again, the epitaxial stack ESLc has a platform portion Mesa and a depression portion CP. The platform portion Mesa includes partial first-type and second-type semiconductor layers SL1, SL2, unintentionally doped semiconductor layer US, and light-emitting layer EL, while the depression portion CP includes another partial first-type semiconductor layer SL1 and unintentionally doped Doped semiconductor layer US. In the epitaxial stack ESLc of this embodiment, at least the unintentionally doped semiconductor layer US has a roughening structure a, and the roughening structure a overlaps with the light emitting layer EL. The light emitting layer EL has opposite sides and is divided into upper side and lower side. Taking the light-emitting layer EL as a reference, the first-type semiconductor layer SL1, the unintentionally doped semiconductor layer US, the insulating layers IL, IL', the first electrode E1, and the first electrode pad EP1 are all arranged on the upper side of the light-emitting layer EL, and The second-type semiconductor layer SL2, the current blocking layer CBL, the ohmic contact layer OCL, the reflection stack RSLc, the first and second connection metal layers CML1, CML2, the carrier substrate CS, and the second electrode pad EP2 are arranged on the light emitting layer EL. underside.

First, please refer to the upper side of the light emitting layer EL. The first-type semiconductor layer SL1 is disposed on the light-emitting layer EL and is in contact with and electrically connected with it. The unintentionally doped semiconductor layer US is disposed on and in contact with the first-type semiconductor layer SL1 . The insulating layer IL is disposed on and in contact with the unintentionally doped semiconductor layer US. The insulating layer IL' is disposed on and in contact with the insulating layer IL, and covers the insulating layer IL, the unintentionally doped semiconductor layer US, the first-type semiconductor layer SL1, and the sidewall of the first insulating layer IL1 of the reflective stack RSLc, Moreover, the insulating layer IL' exposes a part of the first electrode E1, wherein the first electrode pad EP1 is disposed on the exposed part of the first electrode E1 and is electrically connected to it, and the first electrode pad EP1 and the insulating layer IL' With gap G. In addition, since part of the insulating layer IL' is in contact with part of the unintentionally doped semiconductor layer US provided with the roughening structure a (or called conformal arrangement), part of the insulating layer IL' also has the roughening structure a'.

On the other hand, refer to the lower side of the light emitting layer EL. The second-type semiconductor layer SL2 is disposed under the light-emitting layer EL, contacts it and is electrically connected. The current blocking layer CBL is disposed under and in contact with the second-type semiconductor layer SL2. The ohmic contact layer OCL is disposed under the second-type semiconductor layer SL2 and is in contact with and electrically connected to it, and covers the current blocking layer CBL. The second electrode E2 is disposed under the ohmic contact layer OCL, contacts it and is electrically connected to it. The first insulating layer IL1 covers the first electrode E1 , the epitaxial stack RSLc, the ohmic contact layer OCL, and part of the second electrode E2 , and the first insulating layer RL1 exposes part of the second electrode E2 . The first reflective layer RL1 is disposed under and in contact with the first insulating layer RL1 , and the second reflective layer RL2 is disposed under and in contact with the first reflective layer RL1 , wherein the first and second reflective layers RL1 and RL2 are electrically floating. The second insulating layer RL2 covers the first and second reflective layers RL1 and RL2. The first insulating layer IL1 has a plurality of via holes V1'. The first reflective layer RL1 has a plurality of second via holes V2'. The second reflective layer RL2 has a plurality of through holes V3'. The second insulating layer IL2 has a plurality of via holes V4'. These through holes V1'~V4' jointly expose the second electrode E2. Moreover, the first connection metal layer CML1 is disposed under and contacts the second insulating layer IL2, and extends to the second electrode E2 through the via holes V1'~V4', contacts it and is electrically connected to it. The second connection metal layer CML2 is disposed under the first connection metal layer CML1 and is in contact with and electrically connected to it. The carrier substrate CS is disposed under the second connection metal layer CML2 and is in contact with and electrically connected to the surface S1. The second electrode pad EP2 is disposed under the carrier substrate CS and is in contact with and electrically connected to the surface S2 of the carrier substrate CS. In addition, it should be noted that the material of the carrier substrate CS in this embodiment is a conductive substrate that can conduct electricity, such as molybdenum (Mo), copper (Cu), copper tungsten (CuW) or an alloy substrate.

Based on the above, in the light-emitting diode device 200c of this embodiment, when the light-emitting layer EL emits light beams L (including light beams L1, L2), due to the unintentionally doped semiconductor layer US provided with the roughened structure a, the design The insulating layer IL' with the roughened structure a' is overlapped with the light-emitting layer EL, so the roughened structures a and a' are located on the transmission path of the light beam L. When the light beam L exits above the light emitting layer EL, it will be scattered by the roughened structure a or a', so that the light extraction efficiency of the light emitting diode chip 100c is increased.

Moreover, because the first and second orthographic projections of the first and second reflective layers RL1 and RL2 on the first-type semiconductor layer SL1 are respectively misaligned with the third orthographic projection of the second electrode E2 on the first-type semiconductor layer SL1 . In other words, the positions of the through holes V1', V2' of the first and second reflective layers RL1, RL2 correspond to the positions of the second electrode E2. Therefore, when the light beam L1 emits downward, it will be reflected by the first and second reflective layers RL1, RL2 or the second electrode E2, and then emitted to the upper side of the light-emitting layer EL, and then scattered by the roughened structure a or a'. In other words, the arrangement relationship between the above-mentioned first and second reflective layers RL1, RL2 and the second electrode E2 can make the part of the light beam L1 emitted by the light-emitting layer EL be reflected back to the upper side of the light-emitting layer EL, so the light-emitting two electrodes of this embodiment The polar wafer 100c has good luminous efficiency.

8 and 9 are schematic cross-sectional views of light-emitting diode devices according to a fifth embodiment and a sixth embodiment of the present invention, respectively.

Please refer to FIG. 8, the light emitting diode device 200d in FIG. 8 is similar to the light emitting diode device 200c in FIG. 7A and FIG. Among them, in addition to the unintentionally doped semiconductor layer US having the roughening structure a, the first-type semiconductor layer SL1 further has the roughening structure a″. Therefore, the light emitting diode chip 100d of this embodiment can have higher light extraction efficiency.

In the embodiment of FIG. 8, the roughened structure a' exposed to the outside is the roughened structure of the insulating layer. In other not shown embodiments, the roughened structure a' exposed to the outside can be unintentionally doped, for example. The roughened structure of the semiconductor layer, the roughened structure of the insulating layer, or the roughened structure of the first-type doped semiconductor layer, or any combination of the three, the present invention is not limited thereto.

Please refer to FIG. 9, the light emitting diode device 200e in FIG. 9 is similar to the light emitting diode device 200d in FIG. The unintentionally doped semiconductor layer US similar to FIG. 7 is not included, and, in the epitaxial stack ESLe, only the first-type semiconductor layer SL1 has the roughened structure a″. Comparing the light-emitting diode wafers 100e and 100c in FIGS. 9 and 7 , the design with the roughened structure a on the unintentionally doped semiconductor layer US has better light extraction efficiency.

In addition, it should be noted that the light-emitting diode devices 200c-200e shown in FIG. 7 to FIG. 9 can be applied to the circuit substrate CBS as shown in FIG. The third and fourth electrode pads EP3 and EP4 are electrically connected to form a corresponding light-emitting diode module, wherein the first electrode pad EP1 is electrically connected to the third electrode pad EP3 on the circuit substrate CBS by wire bonding The second electrode pad EP2 is electrically connected to the fourth electrode pad EP4 on the circuit substrate CBS by eutectic or solder paste or solder connection and through a heating process.

10A to 10S are flowcharts of manufacturing the light emitting diode device of FIGS. 7A to 7B .

Referring to FIG. 10A , a growing wafer GW is provided. And forming an epitaxial stack ESLc on the growth wafer GW, more specifically, forming an unintentionally doped semiconductor layer US, a first-type semiconductor layer SL1, a light-emitting layer EL, and a second-type semiconductor layer SL2 in sequence. Grow wafers on GW. In the following paragraphs or drawings, a part of the growing wafer GW is used as an example to illustrate the growing light-emitting diode wafer 100c.

Referring to FIG. 10B , the epitaxial stack ESLc is etched to remove part of the second-type semiconductor layer SL2 , part of the light-emitting layer EL and part of the first-type semiconductor layer SL1 to expose part of the first-type semiconductor layer SL1 , forming the platform portion Mesa and the depression portion CP.

Referring to FIG. 10C , a patterned current blocking layer CBL and an ohmic contact layer OCL are sequentially formed on the second-type semiconductor layer SL2 of the platform portion Mesa.

Referring to FIG. 10D, the first and second electrodes E1 and E2 are formed on the first-type semiconductor layer SL1 and the ohmic contact layer OCL. The first and second electrodes E1 and E2 can be formed in the same process step, or can be divided into Different process steps are used to form the first and second electrodes E1 and E2.

Referring to FIG. 10E , a reflective stack RSLc is formed to cover the epitaxial stack ESLc, wherein the reflective stack RSLc includes first and second insulating layers IL1 and IL2 , first and second reflective layers RL1 and RL2 . More specifically, firstly, the first insulating layer IL1 is formed to cover the epitaxial stack ESLc, the first and second electrodes E1, E2, and part of the first insulating layer IL1 is etched to form a plurality of through holes V1'. Next, a first reflective layer RL1 is formed on the first insulating layer IL1, and a part of the first reflective layer RL1 is etched to form a plurality of through holes V2'. Next, a second reflective layer RL2 is formed on the first reflective layer RL1, and a part of the second reflective layer RL2 is etched to form a plurality of through holes V3'. Finally, a second insulating layer IL2 is formed on the first and second reflective layers RL1 and RL2, and a part of the second reflective layer RL2 is etched to form a plurality of through holes V4'. The through holes V1'~V4' overlap with each other, and the position of the second electrode E2 corresponds to the position of the through holes V1'~V4'.

Referring to FIG. 10F , it should be noted that, unlike the previous FIG. 10E which only shows one light emitting unit U, FIG. 10F shows multiple light emitting units U. After the steps in FIG. 10A to FIG. 10E , a plurality of light emitting units U connected to each other as shown in FIG. 10H have been formed on the growth wafer GW. In FIG. 10F , an etching process is used to etch away part of the reflective stack RSLc and part of the first-type semiconductor layer SL1 as shown in FIG. 10E , so as to expose part of the surface of the growth wafer GW. In addition, a scribe process is performed on the exposed surface of the growth wafer GW, so that a scribe C is cut out on the surface of this part, and a part of the growth wafer GW is exposed on the surface of the cut scribe C, so that these light-emitting units U are separated from each other.

Referring to FIG. 10G, the first connection metal layer CML1 is formed on the reflective stack RSLc, and part of the first connection metal layer CML1 extends to the second electrode E2 through the via holes V1'~V4', so as to be connected to the second electrode. E2 is electrically connected. Due to the relationship of the via holes V1'˜V4', the surface of the first connection metal layer CML1 is not a flat surface, but has a concave surface.

Referring to FIG. 10H , the first connection metal layer CML1 is subjected to a planarization process so that the originally recessed surface of the first connection metal layer CML1 becomes a flat surface, wherein the planarization process is, for example, a polishing process, but not limited thereto.

Please refer to FIG. 10I (wherein FIG. 10I shows a complete growth wafer GW and a complete carrier wafer CW) and FIG. 10J (wherein FIG. 10J shows a part of a growth wafer GW (called a growth substrate) and a part of The carrier wafer CW (referred to as the carrier substrate CS)) provides the carrier wafer CW provided with the second connection metal layer CML2. And a bonding process is performed to connect the first connection metal layer CML1 to the second connection metal layer CML2.

Referring to FIG. 10K , the growth wafer GW is removed, wherein the method of removing the growth wafer GW includes a laser lift-off process (Laser Lift-off Process) or a wet chemical etching process. During the laser lift-off process, the high temperature of the laser will reduce the metal ions in the epitaxial stack EPLc to metal. Therefore, after the laser lift-off process, an etching process, such as a wet chemical etching process, can be performed on the surface of the epitaxial stack EPLc to remove metals, such as gallium metal (Gallium). These LED wafers 100c are then transferred and bonded onto the carrier wafer CW.

Referring to FIG. 10L , an insulating layer IL is formed on the unintentionally doped semiconductor layer US, and a part of the insulating layer IL is etched to have an opening O to expose a part of the unintentionally doped semiconductor layer US.

Please refer to FIG. 10M, within the scope of the opening O, an etching process is performed on the unintentionally doped semiconductor layer US to form a roughened structure a, wherein the etching process is, for example, wet chemical etching, but it is not taken as a limit.

Referring to FIG. 10N , a patterned etch stopper layer PR is formed on part of the insulating layer IL and the roughened structure a, and the patterned etch stopper layer PR exposes part of the insulating layer IL, wherein the material of the patterned etch stopper layer PR is, for example, two silicon oxide, photoresist or a combination thereof.

Referring to FIG. 10O , an etching process is performed on the insulating layer IL, the unintentionally doped semiconductor layer US, the first-type semiconductor layer SL1 , part of the first electrode E1 , and part of the first insulating layer IL1 to make part of the first electrode E1 And a part of the first reflective layer RL1 is exposed, wherein the exposed part of the first electrode E1 is called the electrode pad placement region EPR, and the etching process in this step is, for example, a dry etching process, but not limited thereto.

Referring to FIG. 10P, the patterned etch stop layer PR is removed.

Referring to FIG. 10Q, an insulating layer IL' is formed to cover the insulating layer IL, the unintentionally doped semiconductor layer US, the first type semiconductor layer SL1, the first insulating layer IL1, the first reflective layer RL1 and part of the first electrode E1 , and the insulating layer IL′ exposes another part of the first electrode E1.

Referring to FIG. 10R , the first electrode pad EP1 is formed in the electrode pad installation region EPR so as to be electrically connected to the first electrode E1 , wherein the method of forming the first electrode pad EP1 is a lift-off process. Alternatively, in other unshown embodiments, the current blocking layer may be formed on the electrode pad disposition area first, and then the first electrode pad is formed to cover the current blocking layer, and the present invention is not limited thereto.

Referring to FIG. 10S , a second electrode pad EP2 is formed on the other surface S2 of the carrier wafer CW. So far, the light emitting diode device 200c has been substantially manufactured.

In other not shown embodiments, the light emitting diode device 200c may not include the second electrode pad EP2 as shown in FIG. It is electrically connected with the circuit substrate CBS in FIG. 1D to form a corresponding light-emitting diode module. The above-mentioned electrical connection method is, for example, connecting the surface S2 of the carrier substrate CS with the electrode pads on the circuit substrate CBS. The electrical connections are made by solder paste or solder connection and through heating process.

It should be noted that those skilled in the art can perform fine-tuning according to the manufacturing process of FIG. 10A to FIG. 10S to obtain the light-emitting diode devices 200c and 200d as shown in FIG. 8 or FIG. 9 , which will not be repeated here.

To sum up, in the light-emitting diode wafer and light-emitting diode device of the embodiment of the present invention, when the light-emitting layer emits light beams, since the unintentionally doped semiconductor layer with a roughened structure overlaps with the light-emitting layer , so the roughened structure is located on the transmission path of the beam. When the light beam goes out to the side of the light-emitting layer, it will be scattered by the roughened structure, so that the light-taking efficiency of the light-emitting diode chip and the light-emitting diode device increases.

11A is a schematic cross-sectional view of a light-emitting diode device according to a seventh embodiment of the present invention. FIG. 11B is a schematic top view of the embodiment of FIG. 11A . FIG. 11C and FIG. 11D are transmission spectra of anti-reflection layers of different embodiments. FIG. 12A and FIG. 12B are comparison diagrams of the optical effects of the light emitting diode device applying the anti-reflection layer of FIG. 11C and FIG. 11D and the light emitting diode device of the comparative example, respectively.

Please refer to FIG. 11A and FIG. 11B. The light emitting diode device 200f in FIG. 11A and FIG. 11B is similar to the light emitting diode device 200c in FIG. 7A and FIG. impurity semiconductor layer US, and the first-type semiconductor layer SL1 in the epitaxial stack ELSe does not have the rough structure as shown in FIG. 7B . The reflective stack RSLe includes first and second reflective layers RL1 and RL2 and first and second insulating layers IL1 and IL2, the configuration of which is similar to that shown in FIG. 7B , and is disposed on the lower side of the epitaxial stack ELSe. In addition, the light emitting diode device 200f further includes an anti-reflection stack ARSL, which mainly includes: an anti-reflection layer ARL and insulating layers IL', IL'', wherein the anti-reflection layer ARL is located between the insulating layers IL', IL'' Moreover, the anti-reflection layer ARL and the insulating layer IL′ jointly cover the side surfaces of the insulating layer IL″. The insulating layer IL'' covers the first insulating layer IL1, the first-type semiconductor layer SL1 and a part of the first electrode E1, and exposes another part of the first electrode E1. The insulating layer IL' covers the anti-reflection layer ARL and the insulating layer IL'', and exposes another part of the first electrode E1. The first electrode pad EP1 is disposed on another part of the exposed first electrode E1, and the first electrode pad EP1 is in contact with the insulating layers IL', IL'', that is, the first electrode pad EP1 is in contact with the insulating layers IL', IL' ' does not have the interval shown in FIG. 7B , but in other embodiments, there may also be a non-zero interval, and the present invention is not limited thereto.

Moreover, in this embodiment, the anti-reflection layer ARL includes a plurality of first and second refraction layers (not shown), wherein these first and second refraction layers are stacked alternately with each other, and the material of the first refraction layer includes pentoxide Ditantalum (Ta ₂ O ₅ ), zirconium dioxide (ZrO ₂ ), niobium pentoxide (Nb ₂ O ₅ ), hafnium oxide (HfO ₂ ), titanium dioxide (TiO ₂ ), or combinations thereof. The material of the second refraction layer includes silicon dioxide (SiO ₂ ), and the wavelength of the light beam to be transmitted can be adjusted according to the thickness design of the material layer with different refractive index. In other words, the anti-reflection layer ARL has a specific wavelength band The effect of light penetration of the light beam is similar to that of a filter layer. The materials of the insulating layers IL' and IL'' can be, for example, inorganic materials including silicon dioxide (SiO ₂ ) or organic materials including epoxy resin (Epoxy), polyimide (Polyimide), polymer materials, organic adhesive materials, Organic insulating materials or materials with photosensitive functions, but not limited thereto.

In the embodiment of FIG. 11C , the light transmission spectrum of the anti-reflection layer ARL mainly allows the light in the green band (500-600 nanometers) to penetrate. In the embodiment of FIG. 11D , the light transmission spectrum of the anti-reflection layer ARL The transmission spectrum mainly allows light in the blue light band (440-480 nm) to pass through, and the present invention is not limited thereto.

In order to highlight the light-emitting effect of the light-emitting diode device 200f of the embodiment of the present invention, a light-emitting diode device (not shown) of a comparative embodiment is presented here, which is different from the light-emitting diode device 200f of FIG. 11B The main difference is that the light-emitting diode device of the comparative example does not have the anti-reflection stack ARSL. Please refer to FIG. 12A and FIG. 12B. It can be seen that: by setting the anti-reflection laminate ARSL with the transmission spectrum similar to FIG. 12A or FIG. As far as the device is concerned, it can concentrate the light emission angle of the beam of a specific wavelength band, while the beam of other wavelength band cannot penetrate the anti-reflection laminated layer ARSL.

FIG. 13 is a schematic cross-sectional view of a light-emitting diode device according to an eighth embodiment of the present invention.

Please refer to FIG. 13, the light emitting diode device 200f is substantially similar to the light emitting diode device 200f, the main difference is that: in the area close to the first electrode pad EP1, the anti-reflection layer ARL exposes the insulating layer IL'' side.

The manufacturing process of the light emitting diode device 200f in FIG. 11A and FIG. 11B is substantially similar to the manufacturing process of the light emitting diode device 200c in FIG. 7A and FIG. 7B , and the differences are explained as follows.

Continuing from FIG. 10K, please refer to FIG. 14A to provide a temporary substrate TS bonded to the conductive substrate CS to reduce the stress of the light-emitting diode element and wafer warpage, and etch the unintentionally doped as shown in FIG. 10K The semiconductor layer US.

Referring to FIG. 14B , the first-type semiconductor layer SL1 is subjected to a planarization process, wherein the planarization process is, for example, a grinding process, but not limited thereto. During the planarization process, nanometer-sized particles can be added to To assist planarization, in one embodiment, the roughness of the first-type semiconductor layer SL1 is less than 100 microns, more preferably, the roughness of the first-type semiconductor layer SL1 is less than 1 micron, but not limited thereto.

Referring to FIG. 14C, an etching process is performed on the first-type semiconductor layer SL1, part of the first electrode E1, and part of the first insulating layer IL1, so that part of the first electrode E1 and part of the first reflective layer RL1 are exposed. Part of the first electrode E1 is called the electrode pad disposition region EPR, and the etching process in this step is, for example, a dry etching process, but not limited thereto.

Referring to FIG. 14D, an anti-reflection layer ARSL is formed. In detail, the insulating layer IL'' of the anti-reflection stack ARSL is first formed, wherein the insulating layer IL'' covers the first reflective layer RL1, the first insulating layer IL1, the first electrode E1, and the first-type semiconductor layer SL1, and The partial insulating layer IL″ is etched by an etching process to expose the partial first electrode E1. Then an anti-reflection layer ARL of the anti-reflection stack ARSL is formed, wherein the anti-reflection layer ARL covers the insulating layer IL'', and a part of the anti-reflection layer ARL is etched by an etching process to expose a part of the first electrode E1. Next, an insulating layer IL' is formed, wherein the insulating layer IL' covers the anti-reflection layer ARL and the insulating layer IL'', and a part of the insulating layer IL' is etched by an etching process to expose a part of the first electrode E1.

Referring to FIG. 14E , the first electrode pad EP1 is formed in the electrode pad installation region EPR so as to be electrically connected to the first electrode E1 , wherein the method of forming the first electrode pad EP1 is a lift-off process.

It should be noted that those skilled in the art can perform fine-tuning according to the manufacturing process shown in FIG. 14A to FIG. 14E to obtain the light emitting diode device 200f as shown in FIG. 13 , which will not be repeated here.

In addition, it should be noted that in the light-emitting diode devices 200c~200e shown in FIG. 7B, FIG. 8, and FIG. on the upper side. Alternatively, in the light-emitting diode devices 200f and 200g in FIG. 11B or FIG. 13, the roughened structure as shown in FIG. 7B, FIG. 8, and FIG. 9 can be formed on the first-type semiconductor layer SL1. limit.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100, 100', 100a, 100b, 100c, 100d, 100e: light emitting diode chips 200, 200a, 200b, 200c, 200d, 200e, 200f, 200g: light emitting diode device 300, 300a, 300b: light emitting diode modules a, a', a'': coarse structure A-A', B-B', C-C', D-D': section ARL: anti-reflection layer ARS: anti-reflective laminate BS1, BS2: bottom surface C: Scratches CCL1: the first current conducting layer CCL2: Second current conducting layer CBL: current blocking layer CBS: circuit substrate CML1: the first connection metal layer CML2: the second connection metal layer CP: depression CS: carrier substrate CW: carrier wafer CYB: crystal ball d: spacing DB: Die Bonding Materials E: edge E1: first electrode E2: second electrode EL: light emitting layer EDP: electrode part EDP1: first electrode part EDP2: second electrode part EP1: First electrode pad EP2: Second electrode pad EP3: Third electrode pad EP4: Fourth electrode pad EPR: electrode pad setting area ESL, ESLc, ESLd, ELSe: epitaxy stack ECL: etch stop layer FP: finger GS: Growth Substrate GP: Growth block IL, IL', IL'': insulating layer IL1: first insulating layer IL2: Second insulating layer IL3: third insulating layer IL4: fourth insulating layer L1, L2: light beam MP: Main body Mesa: Platform Department O: open OCL: ohmic contact layer PD: default configuration area PS: periodic structure PR: Patterned etch stop layer PE1: the first positioning element PE2: Second positioning element PE3: The third positioning element RL1: the first reflective layer RL2: second reflective layer RL3: The third reflective layer RS1, RS1a: first reflective stack RS2: second reflective stack RSLe: reflective stack S1: first surface S2: second surface S3: surface SS: side SD1: First side SD2: Second side SL1: first type semiconductor layer SL2: Second type semiconductor layer U: light emitting unit US: Unintentionally doped semiconductor layer UPS: non-periodic rough structure Va, Vb, V1'~V4': through holes V1: the first via V2: the second through hole V3: The third via V4: The fourth through hole V5: fifth via V6: the sixth through hole V7: the seventh via WF, WFa: light emitting diode wafer

FIG. 1A is a schematic top view of a light emitting diode chip according to a first embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of the LED wafer in FIG. 1A . FIG. 1C is a schematic cross-sectional view of a light emitting diode device using the light emitting diode wafer shown in FIG. 1A . FIG. 1D is a schematic cross-sectional view of a light emitting diode module using the light emitting diode chip shown in FIG. 1A . FIG. 1E is a schematic top view of the light emitting diode module shown in FIG. 1D . 2A to 2X are flowcharts of manufacturing the LED wafer, LED device, and LED module shown in FIG. 1A , FIG. 1C , and FIG. 1D . FIG. 3A is a schematic top view of a light-emitting diode chip according to a second embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of the LED wafer in FIG. 3A . FIG. 3C is a schematic cross-sectional view of an LED device using the LED wafer shown in FIG. 3A . FIG. 3D is a schematic cross-sectional view of a light emitting diode module using the light emitting diode chip shown in FIG. 3A . FIG. 3E is a schematic top view of the light emitting diode module shown in FIG. 3D . 4A to 4Y are flowcharts of manufacturing the LED wafer, LED device, and LED module shown in FIG. 3A , FIG. 3C , and FIG. 3D . 5A is a schematic cross-sectional view of a light-emitting diode chip according to a third embodiment of the present invention. FIG. 5B is a schematic top view of the LED chip in FIG. 5A . FIG. 5C is a schematic cross-sectional view of a light emitting diode device using the light emitting diode wafer shown in FIG. 5A . FIG. 5D is a schematic cross-sectional view of a light emitting diode module using the light emitting diode chip shown in FIG. 5A . FIG. 5E is a schematic top view of the light emitting diode module shown in FIG. 5D . 6A to 6S are flowcharts of manufacturing the LED wafer, LED device, and LED module shown in FIG. 5A , FIG. 5C , and FIG. 5D . 7A is a schematic cross-sectional view of a light emitting diode device according to a fourth embodiment of the present invention. FIG. 7B is a schematic top view of the embodiment of FIG. 7A . 8 and 9 are schematic cross-sectional views of light-emitting diode devices according to a fifth embodiment and a sixth embodiment of the present invention, respectively. 10A to 10S are flowcharts of manufacturing the light emitting diode device shown in FIG. 7A and FIG. 7B . 11A is a schematic cross-sectional view of a light-emitting diode device according to a seventh embodiment of the present invention. FIG. 11B is a schematic top view of the embodiment of FIG. 11A . FIG. 11C and FIG. 11D are transmission spectra of anti-reflection layers of different embodiments. FIG. 12A and FIG. 12B are comparison diagrams of the optical effects of the light emitting diode device applying the anti-reflection layer of FIG. 11C and FIG. 11D and the light emitting diode device of the comparative example, respectively. FIG. 13 is a schematic cross-sectional view of a light-emitting diode device according to an eighth embodiment of the present invention. 14A to 14E are flowcharts of manufacturing the light emitting diode device of FIGS. 11A to 11B .

100: light emitting diode chip

CBL: current blocking layer

CML1: the first connection metal layer

CP: depression

E1: first electrode

E2: second electrode

EL: light emitting layer

EDP: electrode part

ESL: epitaxial stack

ECL: etch stop layer

FP: finger

GS: Growth Substrate

IL1: first insulating layer

IL2: Second insulating layer

L1, L2: light beam

MP: Main body

Mesa: Platform Department

OCL: ohmic contact layer

RL1: the first reflective layer

RS1: first reflective stack

SD1: First side

SD2: Second side

SL1: first type semiconductor layer

SL2: Second type semiconductor layer

V1: the first via

V2: the second through hole

V3: The third via

Claims (18)

A light emitting diode chip, comprising: An epitaxial stack, including a first-type semiconductor layer, a light-emitting layer, a second-type semiconductor layer and an unintentionally doped semiconductor layer, Wherein, the light-emitting layer is located between the first-type semiconductor layer and the second-type semiconductor layer, the first-type semiconductor layer is located between the unintentionally doped semiconductor layer and the light-emitting layer, and the first-type semiconductor layer Doped with a first-type carrier, the second-type semiconductor layer is doped with a second-type carrier, the first-type carrier is different in electrical property from the second-type carrier, Wherein, in the epitaxial stack, at least the unintentionally doped semiconductor layer has a roughened structure overlapping with the light-emitting layer; a first electrode electrically connected to the first type semiconductor layer; and A second electrode is electrically connected with the second type semiconductor layer. The light-emitting diode wafer according to claim 1, wherein, in the epitaxial stack, the first-type semiconductor layer further has a roughened structure in which the light-emitting layer is overlapped. The light emitting diode wafer as claimed in claim 1, wherein the light emitting layer has a first side and a second side opposite to each other, and the first type semiconductor layer and the unintentionally doped semiconductor layer are located on the first side side, and the second type semiconductor layer, the first electrode and the second electrode are located on the second side. The light-emitting diode chip as claimed in claim 3, further comprising a reflective stack disposed on the second side and on the second-type semiconductor layer, and the reflective stack further comprises a first an insulating layer, a first reflective layer, a second reflective layer and a second insulating layer, in, The first insulating layer is disposed between the first type semiconductor layer and the first reflective layer, The second reflective layer is disposed between the first reflective layer and the second insulating layer. The light emitting diode wafer as claimed in item 4, wherein, The orthographic projection of the first reflection layer on the first type semiconductor layer is a first orthographic projection, The orthographic projection of the second reflection layer on the first type semiconductor layer is a second orthographic projection, The orthographic projection of the second electrode on the first-type semiconductor layer is a third orthographic projection, Wherein the third orthographic projection is misaligned with the first orthographic projection and the second orthographic projection. The light-emitting diode wafer as claimed in claim 3, further comprising: a third insulating layer disposed on the first side and on the unintentionally doped semiconductor layer, and the third insulating layer has the light-emitting layer Coarsening structure for overlapping settings. The light emitting diode wafer as claimed in claim 1, wherein the second electrode has a plurality of electrode portions separated from each other. The light emitting diode wafer as claimed in claim 1, wherein the first type carriers are N type carriers, and the second type carriers are P type carriers. A light emitting diode device comprising: A light emitting diode chip, comprising: An epitaxial stack, including a first-type semiconductor layer, a light-emitting layer, a second-type semiconductor layer and an unintentionally doped semiconductor layer, Wherein, the light-emitting layer is located between the first-type semiconductor layer and the second-type semiconductor layer, the first-type semiconductor layer is located between the unintentionally doped semiconductor layer and the light-emitting layer, and the first-type semiconductor layer Doped with a first-type carrier, the second-type semiconductor layer is doped with a second-type carrier, the first-type carrier is different in electrical property from the second-type carrier, Wherein, in the epitaxial stack, at least the unintentionally doped semiconductor layer has a roughened structure overlapping with the light-emitting layer; a first electrode electrically connected to the first type semiconductor layer; and a second electrode electrically connected to the second-type semiconductor layer; a first electrode pad, disposed on one side of the LED chip, and electrically connected to the first electrode; A carrier substrate is arranged on the other side of the light-emitting diode chip and is electrically connected with the second electrode. The light-emitting diode device as claimed in claim 9, wherein, in the epitaxial stack, the first-type semiconductor layer further has a roughened structure in which the light-emitting layer is overlapped. The light-emitting diode device as claimed in claim 9, wherein the light-emitting layer has a first side and a second side opposite to each other, and the first-type semiconductor layer and the unintentionally doped semiconductor layer are located on the first side side, and the second type semiconductor layer, the first electrode and the second electrode are located on the second side. The light-emitting diode device as claimed in claim 11, wherein the light-emitting diode wafer further includes a reflective stack, the reflective stack is disposed on the second side and on the second-type semiconductor layer, and the reflective The laminate further includes a first insulating layer, a first reflective layer, a second reflective layer and a second insulating layer, in, The first insulating layer is disposed between the first type semiconductor layer and the first reflective layer, The second reflective layer is disposed between the first reflective layer and the second insulating layer. The light emitting diode device as claimed in claim 12, wherein, The orthographic projection of the first reflection layer on the first type semiconductor layer is a first orthographic projection, The orthographic projection of the second reflection layer on the first type semiconductor layer is a second orthographic projection, The orthographic projection of the second electrode on the first-type semiconductor layer is a third orthographic projection, Wherein the third orthographic projection is misaligned with the first orthographic projection and the second orthographic projection. The light emitting diode device as claimed in claim 11, further comprising: a third insulating layer disposed on the first side and on the unintentionally doped semiconductor layer, and the third insulating layer has the light emitting layer Coarsening structure for overlapping settings. The light emitting diode device as claimed in claim 9, wherein the second electrode has a plurality of electrode parts separated from each other. The light emitting diode device according to claim 9, wherein the first type carrier is an N type carrier, and the second type carrier is a P type carrier The light emitting diode device as claimed in claim 9, further comprising a second electrode pad, wherein the carrier substrate has a first surface and a second surface opposite to each other, the light emitting diode chip and the first electrode pad It is arranged on the first surface, and the second electrode pad is arranged on the second surface. The light emitting diode device as claimed in claim 9, wherein the carrier substrate is a conductive substrate.

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