TW201901987A - Light-emitting element - Google Patents

Light-emitting element Download PDF

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Publication number
TW201901987A
TW201901987A TW106116607A TW106116607A TW201901987A TW 201901987 A TW201901987 A TW 201901987A TW 106116607 A TW106116607 A TW 106116607A TW 106116607 A TW106116607 A TW 106116607A TW 201901987 A TW201901987 A TW 201901987A
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Taiwan
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light
layer
electrode
emitting element
side wall
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TW106116607A
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Chinese (zh)
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TWI699909B (en
Inventor
高慧芳
陳怡名
李世昌
呂志強
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晶元光電股份有限公司
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Priority to TW106116607A priority Critical patent/TWI699909B/en
Priority to CN201810460633.9A priority patent/CN108963043B/en
Publication of TW201901987A publication Critical patent/TW201901987A/en
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Publication of TWI699909B publication Critical patent/TWI699909B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22Roughened surfaces, e.g. at the interface between epitaxial layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • H01L33/42Transparent materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

A light-emitting element comprises: a light-emitting stack having a first side wall and a second side wall opposite to the first side wall, a light emitting surface and a contacting surface opposite to the light emitting surface, wherein the first side wall and the second side wall connect the light emitting surface and the contacting surface; an electrode having a width on the light emitting surface, wherein a distance between the electrode and the first side wall is not greater than about 50 [mu]m; and an insulating layer on the contacting layer, wherein the insulating layer comprises a via hole, and from a view in a stacking direction of the light-emitting stack a distance between the via hole and the electrode is larger than the width.

Description

發光元件Light emitting element

本發明關於一種發光元件,特別是關於一種具有絕緣層之發光元件。The present invention relates to a light emitting element, and more particularly to a light emitting element having an insulating layer.

光電元件,例如發光二極體(Light-Emitting Diode;LED),目前已經廣泛地使用在光學顯示裝置、交通號誌、資料儲存裝置、通訊裝置、照明裝置與醫療器材上。此外,上述之LED可與其他元件組合連接以形成一發光裝置。第1圖為習知之發光裝置結構示意圖,如第1圖所示,一發光裝置1包含一具有一電路14之次載體12;一焊料16位於上述次載體12上,藉由此焊料16將LED 11固定於次載體12上並使LED 11與次載體12上之電路14形成電連接;以及一電性連接結構18,以電性連接LED 11之電極15與次載體12上之電路14;其中,上述之次載體12可以是導線架或大尺寸鑲嵌基底。Optoelectronic components, such as Light-Emitting Diodes (LEDs), have been widely used in optical display devices, traffic signs, data storage devices, communication devices, lighting devices, and medical equipment. In addition, the above-mentioned LED can be combined with other components to form a light-emitting device. FIG. 1 is a schematic diagram of a conventional light-emitting device. As shown in FIG. 1, a light-emitting device 1 includes a secondary carrier 12 having a circuit 14; a solder 16 is located on the secondary carrier 12. 11 is fixed on the sub-carrier 12 and the LED 11 is electrically connected to the circuit 14 on the sub-carrier 12; and an electrical connection structure 18 is used to electrically connect the electrode 15 of the LED 11 and the circuit 14 on the sub-carrier 12; The above-mentioned secondary carrier 12 may be a lead frame or a large-size mosaic substrate.

一發光元件,包含一半導體疊層具一第一側壁、一第二側壁相對於該第一側壁、一出光表面以及一接觸表面相對於該出光表面,該第一側壁與該第二側壁連接該出光表面以及該接觸表面;一電極具有一寬度,該電極位於該出光表面上且與該第一側壁之間的直線距離不大於約50μm;以及一絕緣層位於該接觸表面上;其中該絕緣層具有一孔隙,且從該半導體疊層之堆疊方向觀之,該孔隙與該電極之間具有一直線距離大於該寬度。A light emitting element includes a semiconductor stack with a first side wall, a second side wall opposite to the first side wall, a light emitting surface, and a contact surface opposite to the light emitting surface, the first side wall and the second side wall are connected to the A light emitting surface and the contact surface; an electrode having a width, the electrode being located on the light emitting surface and a straight line distance between the electrode and the first side wall is not greater than about 50 μm; and an insulating layer is located on the contact surface; wherein the insulating layer There is a void, and viewed from the stacking direction of the semiconductor stack, a straight line distance between the void and the electrode is greater than the width.

本發明之實施例會被詳細地描述,並且繪製於圖式中,相同或類似的部分會以相同的號碼在各圖式以及說明出現。The embodiments of the present invention will be described in detail and drawn in the drawings, and the same or similar parts will appear in the drawings and descriptions with the same numbers.

第2A圖繪示本發明一實施例之發光元件100之上視示意圖,第2B圖繪示第2A圖沿剖面線AA’之剖面示意圖。如第2B圖所示,一發光元件100具有一基板20、一導電黏結層21位於基板20之上、一反射結構22位於導電黏結層21之上、一透明導電結構23位於反射結構22之上、一絕緣層24位於透明導電結構23上且具有一孔隙3、以及一半導體疊層2位於絕緣層24之上。半導體疊層2包含一窗戶層29位於絕緣層24之上,並透過絕緣層24的孔隙3與透明導電結構23接觸,且半導體疊層2還包含一發光疊層25依一堆疊方向形成於窗戶層29之上,其中發光疊層25具有一出光表面T,出光表面T可為一非平整表面,且較佳的出光表面T具有一平均粗糙度約在0.1μm~2μm之間,但本發明不以此為限,例如在另一實施例中,出光表面T可為一平面。在本實施例中,發光元件100還具有一第一電極27位於發光疊層25之上、以及一第二電極28位於基板20之下。發光疊層25具有一第一半導體層251、一第二半導體層253、以及一主動層252夾設於第一半導體層251與第二半導體層253之間,其中第二半導體層253位於第一電極27與主動層252之間。此外,在本實施例中發光元件100還可具有一電接觸層26位於第一電極27與第二半導體層253之間,其中電接觸層26係圖形化覆蓋在部分的發光疊層25上且未覆蓋出光表面T。具體而言,在本實施例中,部分的第二半導體層253接觸電接觸層26,其餘部分的第二半導體層253則未被電接觸層26覆蓋,但本發明不以此為限,例如在另一實施例中,發光元件100可不具有電接觸層26。FIG. 2A is a schematic top view of a light-emitting element 100 according to an embodiment of the present invention, and FIG. 2B is a schematic cross-sectional view taken along a section line AA ′ in FIG. 2A. As shown in FIG. 2B, a light-emitting element 100 has a substrate 20, a conductive adhesive layer 21 on the substrate 20, a reflective structure 22 on the conductive adhesive layer 21, and a transparent conductive structure 23 on the reflective structure 22. An insulating layer 24 is located on the transparent conductive structure 23 and has a void 3. A semiconductor stack 2 is located on the insulating layer 24. The semiconductor stack 2 includes a window layer 29 on the insulating layer 24 and contacts the transparent conductive structure 23 through the pores 3 of the insulating layer 24. The semiconductor stack 2 also includes a light-emitting stack 25 formed on the window in a stacking direction. Above the layer 29, the light emitting stack 25 has a light emitting surface T, and the light emitting surface T may be a non-flat surface, and the preferred light emitting surface T has an average roughness of about 0.1 μm to 2 μm, but the present invention Without being limited thereto, for example, in another embodiment, the light emitting surface T may be a plane. In this embodiment, the light-emitting element 100 further includes a first electrode 27 located above the light-emitting stack 25 and a second electrode 28 located below the substrate 20. The light-emitting stack 25 has a first semiconductor layer 251, a second semiconductor layer 253, and an active layer 252 sandwiched between the first semiconductor layer 251 and the second semiconductor layer 253, wherein the second semiconductor layer 253 is located at the first Between the electrode 27 and the active layer 252. In addition, in this embodiment, the light-emitting element 100 may further include an electrical contact layer 26 between the first electrode 27 and the second semiconductor layer 253. The electrical contact layer 26 is patterned on a part of the light-emitting stack 25 and The light emitting surface T is not covered. Specifically, in this embodiment, a portion of the second semiconductor layer 253 contacts the electrical contact layer 26, and the remaining portion of the second semiconductor layer 253 is not covered by the electrical contact layer 26, but the present invention is not limited thereto. In another embodiment, the light emitting element 100 may not have the electrical contact layer 26.

在一實施例中,發光元件100可以焊接或打線方式透過第一電極27以及第二電極28與外部裝置連接,例如與封裝次基板或印刷電路板連接。第一電極27或第二電極28的材料包含透明導電材料或金屬材料,其中透明導電材料包含氧化銦錫(ITO)、氧化銦鋅(IZO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)或石墨烯(Graphene),金屬材料包含鋁(Al)、鉻(Cr)、銅(Cu)、錫(Sn)、金(Au)、鎳(Ni)、鈦(Ti)、鉑(Pt)、鉛(Pb)、鋅(Zn)、鎘(Cd)、銻(Sb)、鈷(Co) 、鍺(Ge) 、鈀(Pd)或上述材料之合金。In one embodiment, the light-emitting element 100 can be connected to an external device through the first electrode 27 and the second electrode 28 in a soldering or wire bonding manner, such as being connected to a packaging sub-board or a printed circuit board. The material of the first electrode 27 or the second electrode 28 includes a transparent conductive material or a metal material, wherein the transparent conductive material includes indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), tin oxide (SnO), Cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or graphene (Graphene), metal materials include aluminum (Al), chromium (Cr), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb ), Zinc (Zn), cadmium (Cd), antimony (Sb), cobalt (Co), germanium (Ge), palladium (Pd) or an alloy of the above materials.

如第2A圖與第2B圖所示,在本實施例中半導體疊層2具有一側壁S1、一側壁S2相對於側壁S1、一側壁S3以及一側壁S4相對於側壁S3,其中側壁S3、S4連接側壁S1、S2。第一電極27具有一電流注入部271及一延伸部272與電流注入部271直接連接,電流注入部271可藉由焊接或打線方式與外部裝置連接並導入電流,延伸部272將電流擴散至發光疊層25未被電流注入部271覆蓋的區域。較佳的,電流注入部271具有一最大寬度W1不大於約120μm,延伸部272具有一寬度W3不大於約10μm,但本發明不以此為限;如第2B圖所示,在本實施例中,電流注入部271與延伸部272的厚度相異,其中電流注入部271的厚度大於延伸部272的厚度,電流注入部271與延伸部272的厚度約在1μm ~10μm之間;在另一實施例中,電流注入部271與延伸部272具有相同的厚度(圖未視),且電流注入部271與延伸部272的厚度也約在1μm ~10μm之間(與圖式不符?在跟發明人校稿時改成厚度不同)。在本實施例中,電流注入部271靠近側壁S1並遠離側壁S2,更具體的說,電流注入部271與側壁S1之間具有一最短的距離d1,電流注入部271與側壁S2之間具有一最短的距離d2,其中距離d1與距離d2的比例約在1%~80%之間,較佳的是約在5%~70%之間。在一實施例中,距離d1可約在10μm~50μm之間,距離d2可約在150μm~200μm之間,距離d1與距離d2的比例即約在5%~67%之間。如第2A圖所示,在本實施例中延伸部272可包含複數個延伸電極272a、272b、272c、272d,以提升電流在第二半導體層253中擴散的均勻性,其中延伸電極272a、272b、272c、272d彼此未直接接觸,延伸電極272b、272c被延伸電極272a、272d包圍,延伸電極272a、272b兩者相鄰並與側壁S2、S4平行排列,延伸電極272c、272d兩者相鄰並與側壁S1、S3平行排列,延伸電極272a、272b與延伸電極272c、272d分別位於對角線BB’兩側對稱排列,且延伸電極272a、272b、272c、272d皆具有大致呈直角的轉折部位在對角線CC’上。如第2B圖所示,電接觸層26僅位於延伸部272之下,被延伸部272覆蓋或包圍且未露出於延伸部272之外。電接觸層26係以半導體材料所形成,例如砷化鎵(GaAs)或氮化鎵(GaN),且電接觸層26與第二半導體層253經由摻雜元素後可同為p型半導體,例如摻雜碳(Si)、鎂(Mg)或鋅(Zn),或可同為n型半導體,例如摻雜銻(Te)或碳(C),其中由於電接觸層26的摻雜濃度大於第二半導體層253,所以電接觸層26與第一電極27的接觸電阻可小於第二半導體層253與第一電極27的接觸電阻而形成相對低電阻的歐姆接觸(Ohmic Contact),例如電接觸層26與第一電極27的延伸部272之間的接觸電阻可小於10-4 Ω-cm,如此可降低延伸部272與第二半導體層253之間的等效電阻,並降低發光元件100的正向電壓(Vf)。在一實施例中,電流注入部271與延伸部272未覆蓋電接觸層26而直接接觸第二半導體層253的部分可與第二半導體層253形成蕭特基接觸(Schottky Contact)。As shown in FIG. 2A and FIG. 2B, in this embodiment, the semiconductor stack 2 has a sidewall S1, a sidewall S2 with respect to the sidewall S1, a sidewall S3, and a sidewall S4 with respect to the sidewall S3, wherein the sidewalls S3, S4 Connect the sidewalls S1 and S2. The first electrode 27 has a current injection portion 271 and an extension portion 272 directly connected to the current injection portion 271. The current injection portion 271 can be connected to an external device by welding or wire bonding and introduce current, and the extension portion 272 diffuses the current to emit light. The area of the stack 25 that is not covered by the current injection portion 271. Preferably, the current injection portion 271 has a maximum width W1 of not more than about 120 μm, and the extension portion 272 has a width W3 of not more than about 10 μm, but the present invention is not limited thereto. As shown in FIG. 2B, in this embodiment, The thickness of the current injection portion 271 and the extension portion 272 are different. The thickness of the current injection portion 271 is greater than the thickness of the extension portion 272. The thickness of the current injection portion 271 and the extension portion 272 is between about 1 μm and 10 μm. In the embodiment, the current injection portion 271 and the extension portion 272 have the same thickness (not shown in the figure), and the thickness of the current injection portion 271 and the extension portion 272 is also about 1 μm to 10 μm (does not match the figure? In the invention (When changing the manuscript, the thickness is changed). In this embodiment, the current injection part 271 is close to the side wall S1 and far from the side wall S2. More specifically, there is a shortest distance d1 between the current injection part 271 and the side wall S1, and there is a distance between the current injection part 271 and the side wall S2. The shortest distance d2, wherein the ratio of the distance d1 to the distance d2 is between about 1% and 80%, and preferably between about 5% and 70%. In one embodiment, the distance d1 may be between about 10 μm and 50 μm, the distance d2 may be between about 150 μm and 200 μm, and the ratio between the distance d1 and the distance d2 is between about 5% and 67%. As shown in FIG. 2A, in this embodiment, the extension portion 272 may include a plurality of extension electrodes 272a, 272b, 272c, and 272d to improve the uniformity of current diffusion in the second semiconductor layer 253, where the extension electrodes 272a, 272b , 272c, 272d are not in direct contact with each other, the extension electrodes 272b, 272c are surrounded by the extension electrodes 272a, 272d, the extension electrodes 272a, 272b are adjacent and arranged in parallel with the side walls S2, S4, and the extension electrodes 272c, 272d are adjacent and Aligned in parallel with the sidewalls S1 and S3, the extension electrodes 272a, 272b and 272c, 272d are symmetrically arranged on both sides of the diagonal BB ', and the extension electrodes 272a, 272b, 272c, and 272d all have approximately right-angled turning points at Diagonal CC '. As shown in FIG. 2B, the electrical contact layer 26 is only located below the extension portion 272, is covered or surrounded by the extension portion 272, and is not exposed outside the extension portion 272. The electrical contact layer 26 is formed of a semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the electrical contact layer 26 and the second semiconductor layer 253 can be both p-type semiconductors after doping elements, for example, Doped carbon (Si), magnesium (Mg), or zinc (Zn), or the same n-type semiconductor, such as doped antimony (Te) or carbon (C), where the doping concentration of the electrical contact layer 26 is greater than Two semiconductor layers 253, so the contact resistance between the electrical contact layer 26 and the first electrode 27 can be smaller than the contact resistance between the second semiconductor layer 253 and the first electrode 27 to form a relatively low resistance ohmic contact, such as an electrical contact layer The contact resistance between 26 and the extension portion 272 of the first electrode 27 may be less than 10 -4 Ω-cm, so that the equivalent resistance between the extension portion 272 and the second semiconductor layer 253 can be reduced, and the positive polarity of the light-emitting element 100 can be reduced. Directional voltage (Vf). In one embodiment, a portion of the current injection portion 271 and the extension portion 272 that does not cover the electrical contact layer 26 and directly contacts the second semiconductor layer 253 may form a Schottky contact with the second semiconductor layer 253.

主動層252的材料包含III-V族化合物材料,例如可發出紅外、紅、橘、黃或琥珀色的光的Alp Gaq In(1-p-q) P ,其中0£p、q£1,或者可發出紫外、藍、或綠光的Alx Iny Ga(1-x-y) N,其中 0£x, y£1。第一半導體層251經由摻雜元素後可提供與第二半導體層253具有相異的極性的載子,例如電洞或電子,第一半導體層251可為p型半導體,例如摻雜碳(Si)、鎂(Mg)或鋅(Zn),或可為n型半導體,例如摻雜銻(Te)或碳(C)。第二半導體層253之出光表面T(與前述的出光表面T差異?漏改)可為一粗糙表面以增加發光疊層25所射出的光線透過散射出光的機會,而提升發光元件100的出光效率。主動層252可包含單異質結構(SH)、雙異質結構(DH)、雙邊雙異質結構(DDH)、多量子井結構(MQW)或量子點(QD)。窗戶層29的導電型可與第一半導體層251相同,但窗戶層29的片電阻值(Sheet Resistance)較第一半導體層251低,且對於主動層252射出的光線來說是透明的。窗戶層29的材料包含透明氧化物或半導體材料,其中透明氧化物包含氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO) 、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)或氧化銦鋅(IZO);半導體材料包含砷化鋁鎵(AlGaAs)、氮化鎵(GaN)或磷化鎵(GaP)。The material of the active layer 252 includes a III-V compound material, such as Al p Ga q In (1-pq) P, which emits infrared, red, orange, yellow, or amber light, where 0 £ p, q £ 1, Or Al x In y Ga (1-xy) N that emits ultraviolet, blue, or green light, where 0 £ x, y £ 1. The first semiconductor layer 251 can provide carriers having different polarities from the second semiconductor layer 253 after doping elements, such as holes or electrons. The first semiconductor layer 251 can be a p-type semiconductor, such as doped carbon (Si ), Magnesium (Mg) or zinc (Zn), or may be an n-type semiconductor, such as doped antimony (Te) or carbon (C). The light-emitting surface T of the second semiconductor layer 253 (different from the light-emitting surface T described above? Missing modification) can be a rough surface to increase the chance of the light emitted by the light-emitting stack 25 to diffuse and emit light, thereby improving the light-emitting efficiency of the light-emitting element 100. . The active layer 252 may include a single heterostructure (SH), a double heterostructure (DH), a bilateral double heterostructure (DDH), a multiple quantum well structure (MQW), or a quantum dot (QD). The conductivity type of the window layer 29 may be the same as that of the first semiconductor layer 251, but the sheet resistance of the window layer 29 is lower than that of the first semiconductor layer 251, and is transparent to the light emitted from the active layer 252. The material of the window layer 29 includes a transparent oxide or a semiconductor material, wherein the transparent oxide includes indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO) , Zinc aluminum oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO); semiconductor materials include aluminum gallium arsenide ( AlGaAs), gallium nitride (GaN), or gallium phosphide (GaP).

如第2B圖所示,絕緣層24與窗戶層29接觸且具有一孔隙3以露出窗戶層29。在一實施例中,絕緣層24對於主動層252發出之光線的穿透率可不小於約90%。在一實施例中,絕緣層24的折射率可小於窗戶層29,且絕緣層24的折射率小於窗戶層29的折射率至少約0.5以上,使絕緣層24與窗戶層29之間形成全反射(TIR)介面,而可增加反射發光疊層25所發出的光線的機率,提升出光效率。在一實施例中,絕緣層24可以折射率介於約1.3到1.4之間的非氧化材料形成,例如II族化合物、IV族化合物或VII族化合物,其中非氧化材料可包含一化合物具有氟碳鍵,例如Cx Fy 的化合物,或包含化學式為MgFx 的氟鎂化合物,例如MgF2 。在一實施例中,絕緣層24可以折射率介於約1.4到1.8之間的氧化物或氮化物形成,例如SiOx 或SiNx 。在一實施例中,絕緣層24的厚度介於約20nm到2μm之間,較佳地是介於約100nm到300nm之間。As shown in FIG. 2B, the insulation layer 24 is in contact with the window layer 29 and has a hole 3 to expose the window layer 29. In one embodiment, the transmittance of the insulating layer 24 to light emitted from the active layer 252 may be not less than about 90%. In an embodiment, the refractive index of the insulating layer 24 may be smaller than the refractive index of the window layer 29, and the refractive index of the insulating layer 24 is smaller than the refractive index of the window layer 29 by at least about 0.5 or more, so that a total reflection is formed between the insulating layer 24 and the window layer 29. (TIR) interface, which can increase the probability of reflecting the light emitted from the light emitting stack 25 and improve the light output efficiency. In one embodiment, the insulating layer 24 may be formed of a non-oxidizing material having a refractive index between about 1.3 and 1.4, such as a Group II compound, a Group IV compound, or a Group VII compound. The non-oxidizing material may include a compound having fluorocarbon. bond, for example, a compound C x F y, or a compound of the formula magnesium fluoride MgF x, for example, MgF 2. In one embodiment, the insulating layer 24 may be formed of an oxide or nitride having a refractive index between about 1.4 and 1.8, such as SiO x or SiN x . In one embodiment, the thickness of the insulating layer 24 is between about 20 nm and 2 μm, and preferably between about 100 nm and 300 nm.

在一實施例中,當絕緣層24包含氟鎂化合物(MgF2 ) 時,可施以剝離製程(Lift-off)將絕緣層24圖形化以形成孔隙3。在一實施例中,當絕緣層24包含氟碳化合物或氧化物時,可施以濕蝕刻製程將絕緣層24圖形化以形成孔隙3,其中蝕刻液包含緩衝氧化蝕刻液(BOE)或氫氟酸(HF)。如第2A圖所示,在本實施例中孔隙3包含主孔隙31與複數個延伸孔隙32a、32b與主孔隙31連接,但本發明不以此為限,例如在另一實施例中,主孔隙31可與複數個延伸孔隙32a、32b分離;在本實施例中,透過孔隙3與第一電極27的設置,驅動發光元件100的電流可在主孔隙31、複數個延伸孔隙32a、32b與電流注入部271、延伸電極272a、272b、272c、272d之間傳輸。在一實施例中,主孔隙31具有一最大寬度W2(圖式為W3?畫錯)約在20μm~100μm之間,延伸孔隙32a、32b具有一最小寬度W4約在1μm~20μm之間。如第2A圖所示,在本實施例中,主孔隙31與電流注入部271大致設置在對角線BB’上,並分別位於發光元件100的兩個相對角落。在一實施例中,主孔隙31與側壁S2之間具有一最短的距離d3,主孔隙31與側壁S1之間具有一最短的距離d4,其中距離d3與距離d4的比例約在1%~80%之間,較佳的是約在5%~70%之間。在本實施例中,距離d3約在10μm~50μm之間,距離d4約在150μm~200μm之間,距離d3與距離d4的比例即約在5%~67% 之間。在一實施例中,延伸孔隙32a與側壁S2、S4平行排列且與側壁S2、S4之間的距離約在10μm~50μm之間,延伸孔隙32b與側壁S1、S3平行排列且與側壁S1、S3之間的距離約在10μm~50μm之間。在本實施例中,延伸孔隙32a、32b彼此未直接接觸,延伸孔隙32a、32b分別比延伸電極272a、272b、272c、272d更靠近側壁S2、S4與S1、S3;延伸孔隙32a、32b分別位於對角線BB’兩側大致對稱排列;延伸孔隙32a、32b皆具有大致呈直角的轉折部,並與延伸電極272a、272b、272c、272d的直角轉折部位於相同對角線CC’上;延伸孔隙32a、32b與延伸電極272a、272b、272c、272d彼此可互相大致平行。在本實施例中,如第2B圖所示,在發光疊層25的堆疊方向上,發光元件100中的孔隙3不和第一電極27及電接觸層26重疊,換言之,絕緣層24較佳地是圖形化後設置於電接觸層26及第一電極27的正下方;另外,如第2A、2B圖所示,在平行出光表面T的方向A上,第一電極27與孔隙3之間具有一直線距離d5,較佳地直線距離d5不小於電流注入部271的最大的寬度或不小於對角線BB’長度的約50%。In one embodiment, when the insulating layer 24 includes a fluoromagnesium compound (MgF 2 ), a lift-off process may be performed to pattern the insulating layer 24 to form the pores 3. In an embodiment, when the insulating layer 24 includes a fluorocarbon or an oxide, the insulating layer 24 may be patterned to form the pores 3 by a wet etching process, wherein the etching solution includes a buffer oxide etching solution (BOE) or hydrofluoride. Acid (HF). As shown in FIG. 2A, in this embodiment, the pore 3 includes a main pore 31 and a plurality of extended pores 32a, 32b connected to the main pore 31, but the present invention is not limited thereto. For example, in another embodiment, the main pore 3 The aperture 31 can be separated from the plurality of extended apertures 32a, 32b. In this embodiment, through the arrangement of the aperture 3 and the first electrode 27, the current driving the light emitting element 100 can be transmitted between the main aperture 31, the plurality of extended apertures 32a, 32b and The current is injected between the current injection portion 271 and the extension electrodes 272a, 272b, 272c, and 272d. In one embodiment, the main pore 31 has a maximum width W2 (the drawing is W3? Wrong) is between about 20 μm and 100 μm, and the extended pores 32 a and 32 b have a minimum width W4 between about 1 μm and 20 μm. As shown in FIG. 2A, in this embodiment, the main aperture 31 and the current injection portion 271 are substantially disposed on the diagonal line BB ′, and are respectively located at two opposite corners of the light emitting element 100. In one embodiment, there is a shortest distance d3 between the main aperture 31 and the side wall S2, and a shortest distance d4 between the main aperture 31 and the side wall S1. The ratio of the distance d3 to the distance d4 is about 1% to 80. %, Preferably between 5% and 70%. In this embodiment, the distance d3 is between about 10 μm and 50 μm, the distance d4 is between about 150 μm and 200 μm, and the ratio between the distance d3 and the distance d4 is between about 5% and 67%. In one embodiment, the extension apertures 32a are arranged in parallel with the sidewalls S2 and S4 and the distance between the sidewalls S2 and S4 is between about 10 μm and 50 μm. The extension apertures 32b are arranged in parallel with the sidewalls S1 and S3 and parallel to the sidewalls S1 and S3. The distance between them is between 10 μm and 50 μm. In this embodiment, the extension apertures 32a, 32b are not in direct contact with each other, and the extension apertures 32a, 32b are closer to the sidewalls S2, S4, and S1, S3 than the extension electrodes 272a, 272b, 272c, and 272d, respectively; the extension apertures 32a, 32b are respectively located at Both sides of the diagonal line BB 'are arranged approximately symmetrically; the extension apertures 32a and 32b each have a substantially right-angled turning portion, and are located on the same diagonal line CC' as the right-angled turning portion of the extension electrodes 272a, 272b, 272c, and 272d; the extension The apertures 32a, 32b and the extension electrodes 272a, 272b, 272c, and 272d may be substantially parallel to each other. In this embodiment, as shown in FIG. 2B, in the stacking direction of the light-emitting stack 25, the pores 3 in the light-emitting element 100 do not overlap with the first electrode 27 and the electrical contact layer 26. In other words, the insulating layer 24 is preferred. The ground is patterned and disposed directly below the electrical contact layer 26 and the first electrode 27. In addition, as shown in FIGS. 2A and 2B, in the direction A parallel to the light emitting surface T, between the first electrode 27 and the aperture 3 It has a straight line distance d5, preferably the straight line distance d5 is not less than the maximum width of the current injection portion 271 or not less than about 50% of the length of the diagonal line BB '.

透明導電結構23對於發光疊層25所發之光可為透明,並可透過與窗戶層29或反射結構22之間的歐姆接觸增加及電流傳導與擴散;如第2B圖所示,本實施例中透明導電結構23具有一第一透明導電層230,位於反射結構22之上,以及一第二透明導電層232,位於絕緣層24與第一透明導電層230之間,但本發明不以此為限,例如在一實施例中,透明導電結構23可包含單一透明導電層。在本實施例中,第二透明導電層232可共形地覆蓋絕緣層24與孔隙3,並透過孔隙3與窗戶層29直接接觸,第一透明導電層230則覆蓋在第二透明導電層232上。在一實施例中,第二透明導電層232的厚度可約在1nm到1μm之間,較佳地是約在10nm到100nm之間或約在1nm到20nm之間。在一實施例中,第一透明導電層230的厚度可約在10nm到1000nm之間,較佳地約在50nm到500nm之間。本實施例中第二透明導電層232的厚度可小於絕緣層24,且第一透明導電層230的厚度不小於絕緣層24。第一透明導電層230與孔隙3相對的一表面230a可為一平坦表面,其中表面230a的平均粗糙度較佳地不大於約2nm。在另一實施例中,較佳地,絕緣層24的厚度可不大於透明導電結構23厚度的約1/5,或者透明導電結構23厚度可不小於絕緣層24的厚度約100nm以上,如此當對透明導電結構23施以研磨製程以平坦化透明導電結構23與反射結構22接觸的表面時,可避免研磨過度而損害到絕緣層24。The transparent conductive structure 23 may be transparent to the light emitted by the light-emitting stack 25, and may increase the ohmic contact with the window layer 29 or the reflective structure 22 and current conduction and diffusion; as shown in FIG. 2B, this embodiment The medium transparent conductive structure 23 has a first transparent conductive layer 230 on the reflective structure 22 and a second transparent conductive layer 232 between the insulating layer 24 and the first transparent conductive layer 230. For example, in one embodiment, the transparent conductive structure 23 may include a single transparent conductive layer. In this embodiment, the second transparent conductive layer 232 can conformally cover the insulating layer 24 and the aperture 3 and directly contact the window layer 29 through the aperture 3, and the first transparent conductive layer 230 covers the second transparent conductive layer 232. on. In one embodiment, the thickness of the second transparent conductive layer 232 may be between about 1 nm and 1 μm, preferably between about 10 nm and 100 nm or between about 1 nm and 20 nm. In an embodiment, the thickness of the first transparent conductive layer 230 may be between about 10 nm and 1000 nm, and preferably between about 50 nm and 500 nm. In this embodiment, the thickness of the second transparent conductive layer 232 may be smaller than that of the insulating layer 24, and the thickness of the first transparent conductive layer 230 is not smaller than that of the insulating layer 24. A surface 230a of the first transparent conductive layer 230 opposite to the pore 3 may be a flat surface, and the average roughness of the surface 230a is preferably not greater than about 2 nm. In another embodiment, preferably, the thickness of the insulating layer 24 may not be greater than about 1/5 of the thickness of the transparent conductive structure 23, or the thickness of the transparent conductive structure 23 may be not less than about 100 nm or more of the thickness of the insulating layer 24. When the conductive structure 23 is subjected to a grinding process to planarize the surface of the transparent conductive structure 23 that is in contact with the reflective structure 22, excessive damage to the insulating layer 24 can be avoided.

如第2B圖所示,透明導電結構23具有一第一接觸上表面231與窗戶層29接觸,絕緣層24具有一第二接觸上表面241與窗戶層29接觸,其中第一接觸上表面231與第二接觸上表面241實質上位於同一水平面。從第2A圖之發光元件100的上視圖觀之,在本實施例中,第一接觸上表面231的表面積相對於第一接觸上表面231和第二接觸上表面241之表面積總和之百分比約為10%~50%之間,但本發明不以此為限,例如在另一實施中,第一接觸上表面231的表面積相對於第一接觸上表面231和第二接觸上表面241之表面積總和之百分比較佳地可約為12.5%~25%之間。在一實施例中,第二接觸上表面241可為一粗糙表面,以散射發光疊層25所發之光以提升光電元件100之出光效率。As shown in FIG. 2B, the transparent conductive structure 23 has a first contact upper surface 231 in contact with the window layer 29, and the insulating layer 24 has a second contact upper surface 241 in contact with the window layer 29, wherein the first contact upper surface 231 and The second contact upper surface 241 is located substantially at the same horizontal plane. From the top view of the light emitting element 100 in FIG. 2A, in this embodiment, the percentage of the surface area of the first contact upper surface 231 to the sum of the surface areas of the first contact upper surface 231 and the second contact upper surface 241 is approximately 10% to 50%, but the present invention is not limited to this. For example, in another implementation, the surface area of the first contact upper surface 231 is relative to the sum of the surface areas of the first contact upper surface 231 and the second contact upper surface 241. The percentage may preferably be between about 12.5% and 25%. In an embodiment, the second contact upper surface 241 may be a rough surface to scatter the light emitted from the light emitting stack 25 to improve the light emitting efficiency of the photovoltaic element 100.

透明導電結構23的材料可包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)、石墨烯(Graphene)或上述材料之組合。在一實施例中,第一透明導電層230與第二透明導電層232材料可為不同,或是第一透明導電層230與第二透明導電層232之材料相較有至少一組成元素相異,例如,第一透明導電層230的材料是氧化銦鋅(IZO),具有一折射率約在2.0到2.2之間,第二透明導電層232的材料則是氧化銦錫(ITO),具有一折射率約在1.8到2.0之間。The material of the transparent conductive structure 23 may include, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO) , Zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), Indium titanium (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene, or a combination of the above materials. In an embodiment, the materials of the first transparent conductive layer 230 and the second transparent conductive layer 232 may be different, or the materials of the first transparent conductive layer 230 and the second transparent conductive layer 232 are different from each other by at least one constituent element. For example, the material of the first transparent conductive layer 230 is indium zinc oxide (IZO), which has a refractive index of about 2.0 to 2.2, and the material of the second transparent conductive layer 232 is indium tin oxide (ITO), which has a The refractive index is between 1.8 and 2.0.

本實施例中,第一透明導電層230的折射率大於第二透明導電層232的折射率,第二透明導電層232的折射率大於絕緣層24的折射率,即第一絕緣層24、第二透明導電層232以及第一透明導電層230的折射率沿著發光疊層25朝向反射結構22的方向遞增,使光線被反射結構22反射朝向發光疊層25前進時,可以減少光線在絕緣層24與第二透明導電層232之間、以及第二透明導電層232與第一透明導電層230之間發生全反射的機率。因此在本實施例中,即使從發光疊層25所發出的光線沒有被絕緣層24與窗戶層29之間的內部全反射(TIR)介面所反射,光線亦可以被透明導電結構23與反射結構22所形成的全方位反射鏡(ODR)反射,並順利從出光表面T及側壁S1~S4射出,用以提升發光元件100的出光效率。In this embodiment, the refractive index of the first transparent conductive layer 230 is greater than the refractive index of the second transparent conductive layer 232, and the refractive index of the second transparent conductive layer 232 is greater than the refractive index of the insulating layer 24, that is, the first insulating layer 24, the first The refractive indices of the two transparent conductive layers 232 and the first transparent conductive layer 230 increase along the direction of the light-emitting stack 25 toward the reflective structure 22, so that when the light is reflected by the reflective structure 22 and proceeds toward the light-emitting stack 25, light can be reduced in the insulating layer. The probability of total reflection occurring between 24 and the second transparent conductive layer 232 and between the second transparent conductive layer 232 and the first transparent conductive layer 230. Therefore, in this embodiment, even if the light emitted from the light-emitting stack 25 is not reflected by the internal total reflection (TIR) interface between the insulating layer 24 and the window layer 29, the light can be reflected by the transparent conductive structure 23 and the reflective structure. The omnidirectional mirror (ODR) formed by 22 reflects and is smoothly emitted from the light emitting surface T and the sidewalls S1 to S4, so as to improve the light emitting efficiency of the light emitting element 100.

反射結構22對於從發光疊層25所發出的光線具有一反射率不小於90%,且反射結構22的材料可包含金屬材料,金屬材料包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)或上述材料之合金等。反射結構22包含一反射層226、一反射黏結層224位於反射層226之下、一阻障層222位於反射黏結層224之下、以及一歐姆接觸層220位於阻障層222之下,其中反射層226可反射來自發光疊層25之光,反射黏結層224黏結反射層226與阻障層222,阻障層222可防止反射層226之材料擴散至歐姆接觸層220,以避免破壞反射層226的結構而導致反射層226的反射率降低,歐姆接觸層220則與下方導電黏結層21形成歐姆接觸。導電黏結層21用以連接基板20與反射結構22,並可為單一層或具有複數個子層(未顯示),其中導電黏結層21之材料可包含透明導電材料或金屬材料,透明導電材料包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)、石墨烯(Graphene)或上述材料之組合,金屬材料包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)或上述材料之合金等。The reflective structure 22 has a reflectivity of not less than 90% for the light emitted from the light-emitting stack 25, and the material of the reflective structure 22 may include a metal material. The metal material includes, but is not limited to, copper (Cu), aluminum (Al), and tin. (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), or an alloy of the above materials. The reflective structure 22 includes a reflective layer 226, a reflective adhesive layer 224 under the reflective layer 226, a barrier layer 222 under the reflective adhesive layer 224, and an ohmic contact layer 220 under the barrier layer 222. The layer 226 can reflect the light from the light-emitting stack 25. The reflective adhesive layer 224 bonds the reflective layer 226 and the barrier layer 222. The barrier layer 222 can prevent the material of the reflective layer 226 from diffusing to the ohmic contact layer 220 to avoid damaging the reflective layer 226. Structure, the reflectivity of the reflective layer 226 decreases, and the ohmic contact layer 220 forms an ohmic contact with the conductive adhesive layer 21 below. The conductive adhesive layer 21 is used to connect the substrate 20 and the reflective structure 22, and may be a single layer or a plurality of sublayers (not shown). The material of the conductive adhesive layer 21 may include a transparent conductive material or a metal material. The transparent conductive material includes but Not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), oxide Gallium zinc (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), titanium indium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene (Graphene), or a combination of the above materials. Metal materials include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), or alloys of the foregoing materials.

基板20可用以支持位於其上之發光疊層25與其它層或結構,其材料可包含導電材料。導電材料包含但不限於銅(Cu)、鋁(Al)、鉬(Mo)、錫(Sn)、鋅(Zn)、鎘(Cd)、鎳(Ni)、鈷(Co)、類鑽碳薄膜(Diamond Like Carbon;DLC)、石墨(Graphite)、碳纖維(Carbon fiber)、金屬基複合材料(Metal Matrix Composite;MMC)、陶瓷基複合材料(Ceramic Matrix Composite;CMC)、矽(Si)、磷化碘(IP)、硒化鋅(ZnSe)、砷化鎵(GaAs)、碳化矽(SiC)、磷化鎵(GaP)、磷砷化鎵(GaAsP)、磷化銦(InP)、鎵酸鋰(LiGaO2)或鋁酸鋰(LiAlO2)。The substrate 20 may be used to support the light-emitting stack 25 and other layers or structures thereon, and the material may include a conductive material. Conductive materials include but are not limited to copper (Cu), aluminum (Al), molybdenum (Mo), tin (Sn), zinc (Zn), cadmium (Cd), nickel (Ni), cobalt (Co), diamond-like carbon films (Diamond Like Carbon (DLC)), graphite (Graphite), carbon fiber (Carbon fiber), metal matrix composite (MMC), ceramic matrix composite (CMC), silicon (Si), phosphating Iodine (IP), zinc selenide (ZnSe), gallium arsenide (GaAs), silicon carbide (SiC), gallium phosphide (GaP), gallium phosphorus arsenide (GaAsP), indium phosphide (InP), lithium gallate (LiGaO2) or lithium aluminate (LiAlO2).

第3A~3D圖係繪示其他實施例之發光元件200~500之上視示意圖。如第3A圖所示,發光元件200與前述發光元件100的差異包括發光元件200的孔隙3僅包含延伸孔隙32a、32b;如第3B圖所示,發光元件300與前述發光元件100的差異包括發光元件300的延伸孔隙32a(第3B圖的32a的指引線不明確須調整已調整)僅沿側壁S2向側壁S4延伸,延伸孔隙32b僅沿側壁S3向側壁S1延伸;如第3C圖所示,發光元件400與前述發光元件100的差異包括發光元件400的孔隙3僅包含延伸孔隙32a、32b,其中延伸孔隙32a僅沿側壁S2向側壁S4延伸,延伸孔隙32b僅沿側壁S3向側壁S1延伸,另外第一電極27更包含延伸電極272e、272f與電流注入部271直接連接並分別平行於側壁S4、S1,其中延伸電極272e、272f分別與側壁S4、S1之間具有一最短直線距離約在10μm~50μm之間;如第3D圖所示,發光元件500與前述發光元件400的差異包括發光元件500的第一電極27僅包含電流注入部271以及延伸電極272b、272c、272e、272f。3A to 3D are schematic top views of light emitting elements 200 to 500 in other embodiments. As shown in FIG. 3A, the difference between the light-emitting element 200 and the aforementioned light-emitting element 100 includes that the pores 3 of the light-emitting element 200 only include extended apertures 32a, 32b; as shown in FIG. 3B, the differences between the light-emitting element 300 and the aforementioned light-emitting element 100 include The extension aperture 32a of the light-emitting element 300 (the guide line of 32a in FIG. 3B is not clear and must be adjusted) only extends along the sidewall S2 to the sidewall S4, and the extension aperture 32b extends only along the sidewall S3 to the sidewall S1; as shown in FIG. 3C The difference between the light-emitting element 400 and the aforementioned light-emitting element 100 includes that the pores 3 of the light-emitting element 400 only include extension apertures 32a, 32b, wherein the extension aperture 32a extends only along the sidewall S2 to the sidewall S4, and the extension aperture 32b extends only along the sidewall S3 toward the sidewall S1. In addition, the first electrode 27 further includes extension electrodes 272e and 272f directly connected to the current injection portion 271 and parallel to the side walls S4 and S1, respectively. Among them, the extension electrodes 272e and 272f and the side walls S4 and S1 have a shortest straight line distance between about 10 μm to 50 μm; as shown in FIG. 3D, the difference between the light-emitting element 500 and the aforementioned light-emitting element 400 includes that the first electrode 27 of the light-emitting element 500 includes only a current injection portion 271 and an extension electrode 272 b, 272c, 272e, 272f.

第4圖係繪示出一照明裝置4分解示意圖,一照明裝置4具有一燈罩41、一光學元件42置於燈罩41之中、一照明模組44位於光學元件42之下、一燈座45承載照明模組44、一連結部47以及一電連結器48,其中燈座45具有一散熱槽46,連結部47連結燈座45與電連接器48。其中光學元件42可包含透鏡、反射杯或導光元件等等。其中照明模組44具有一載體43,以及複數個前述任一實施例之發光元件40,位於載體43之上。FIG. 4 is a schematic exploded view of a lighting device 4. The lighting device 4 has a lamp cover 41, an optical element 42 placed in the lamp cover 41, a lighting module 44 under the optical element 42, and a lamp holder 45. The lighting module 44, a connecting portion 47, and an electrical connector 48 are carried. The lamp holder 45 has a heat sink 46, and the connecting portion 47 connects the lamp holder 45 and the electrical connector 48. The optical element 42 may include a lens, a reflective cup, or a light guide element. The lighting module 44 has a carrier 43 and a plurality of the light-emitting elements 40 of any of the foregoing embodiments, which are located on the carrier 43.

第5圖係繪示出一光電系統4b示意圖。光電系統4b包含一底板49,複數個畫素40’位於底板49上且與底板49電性連接,一控制模組49’ 電性連接底板49以控制複數個畫素40’,其中複數個畫素40’之一包含一個或多個發光元件40b,發光元件40b係包含前述任一實施例所揭露之結構,且每一個發光元件40b可被控制模組49’單獨控制。在一實施例中,每一個畫素40’之中包含一用以發出紅光的發光單元、一用以發出藍光的發光單元以及一用以發出綠光的發光單元,其中至少一發光單元包含發光元件40b。在一實施例中,底板49上的多個發光元件40b可被放置成一具有行/列之矩陣,或具有非對稱的多邊形的外圍輪廓。在一實施例中,較佳地,兩鄰近之畫素40’之間的距離d約在100μm~5mm之間,或兩鄰近之發光元件40b之間的距離d’約在100μm~500μm之間。FIG. 5 is a schematic diagram of a photovoltaic system 4b. The optoelectronic system 4b includes a base plate 49. A plurality of pixels 40 'are located on the base plate 49 and are electrically connected to the base plate 49. A control module 49' is electrically connected to the base plate 49 to control the plurality of pixels 40 ', of which a plurality of pixels One of the elements 40 'includes one or more light-emitting elements 40b. The light-emitting elements 40b include the structure disclosed in any one of the foregoing embodiments, and each light-emitting element 40b can be individually controlled by the control module 49'. In one embodiment, each pixel 40 'includes a light emitting unit for emitting red light, a light emitting unit for emitting blue light, and a light emitting unit for emitting green light. At least one light emitting unit includes Light emitting element 40b. In one embodiment, the plurality of light emitting elements 40 b on the bottom plate 49 may be placed in a matrix with rows / columns, or a peripheral contour with an asymmetric polygon. In one embodiment, preferably, the distance d between two adjacent pixels 40 'is between 100 μm and 5 mm, or the distance d' between two adjacent light emitting elements 40b is between 100 μm and 500 μm. .

第6圖係繪示出一發光單元4c示意圖。發光單元4c包含一發光元件40c,其中發光元件40c係包含前述任一實施例所揭露之結構,兩個電性連接端54、56在發光元件40c上,一波長轉換層55覆蓋發光元件40c並露出兩個電性連接端54、56,以及兩電極墊57、58分別形成且連接兩個電性連接端54、56。FIG. 6 is a schematic diagram showing a light-emitting unit 4c. The light-emitting unit 4c includes a light-emitting element 40c. The light-emitting element 40c includes the structure disclosed in any of the foregoing embodiments. The two electrical connection terminals 54 and 56 are on the light-emitting element 40c. A wavelength conversion layer 55 covers the light-emitting element 40c. The two electrical connection terminals 54 and 56 are exposed, and the two electrode pads 57 and 58 are respectively formed and connected to the two electrical connection terminals 54 and 56.

應當注意,上述提出的各種實施例是用於說明本發明,但並不限制本發明的範圍。各實施例中類似或相同的元件或在不同實施例中具有相同圖式符號的元件可具有相同的化學或物理特性。此外,不同實施例所示的元件可以在適當的情況下彼此組合或替換,在一個實施例的元件連接關係也可應用於另一個實施例中。上述各實施例可進行任何可能的修改而不脫離本發明的技術原理與精神,且均為本發明所涵蓋,並為後述之申請專利範圍所保護。本It should be noted that the above-mentioned various embodiments are provided to illustrate the present invention, but not to limit the scope of the present invention. Similar or identical elements in the embodiments or elements having the same drawing symbols in different embodiments may have the same chemical or physical characteristics. In addition, elements shown in different embodiments may be combined or replaced with each other as appropriate, and the connection relationship of the elements in one embodiment may also be applied to another embodiment. The above embodiments can be modified in any possible way without departing from the technical principles and spirit of the present invention, which are all covered by the present invention and protected by the scope of patent application described later. this

1‧‧‧發光裝置1‧‧‧light-emitting device

11‧‧‧發光二極體11‧‧‧light-emitting diode

12‧‧‧次載體12‧‧‧ times carrier

13、20‧‧‧基板13, 20‧‧‧ substrate

14‧‧‧電路14‧‧‧circuit

15‧‧‧電極15‧‧‧ electrode

16‧‧‧焊料16‧‧‧Solder

18‧‧‧電性連接結構18‧‧‧ Electrical connection structure

100、200、300、400、500‧‧‧發光元件100, 200, 300, 400, 500‧‧‧ light-emitting elements

2‧‧‧半導體疉層2‧‧‧Semiconductor

21‧‧‧導電黏結層21‧‧‧ conductive adhesive layer

22‧‧‧反射結構22‧‧‧Reflective Structure

220‧‧‧歐姆接觸層220‧‧‧ohm contact layer

222‧‧‧阻障層222‧‧‧Barrier layer

224‧‧‧反射黏結層224‧‧‧Reflective Adhesive Layer

226‧‧‧反射層226‧‧‧Reflective layer

23‧‧‧透明導電結構23‧‧‧ transparent conductive structure

230‧‧‧第一透明導電層230‧‧‧The first transparent conductive layer

231‧‧‧第一接觸上表面231‧‧‧ the first contact with the upper surface

232‧‧‧第二透明導電層232‧‧‧Second transparent conductive layer

24‧‧‧絕緣層24‧‧‧ Insulation

241‧‧‧第二接觸上表面241‧‧‧Second contact upper surface

25‧‧‧發光疊層25‧‧‧Light-emitting stack

251‧‧‧第一半導體層251‧‧‧First semiconductor layer

252‧‧‧發光層252‧‧‧Light-emitting layer

253‧‧‧第二半導體層253‧‧‧Second semiconductor layer

254‧‧‧出光上表面254‧‧‧light upper surface

26‧‧‧電接觸層26‧‧‧Electrical contact layer

27‧‧‧第一電極27‧‧‧first electrode

271‧‧‧電流注入部271‧‧‧Current injection unit

272a、272b、272c、272d、272e、272f‧‧‧延伸電極272a, 272b, 272c, 272d, 272e, 272f‧‧‧ extension electrode

28‧‧‧第二電極28‧‧‧Second electrode

29‧‧‧窗戶層29‧‧‧ window layer

3‧‧‧孔隙3‧‧‧ porosity

31‧‧‧主孔隙31‧‧‧ main pore

32a、32b‧‧‧延伸孔隙32a, 32b‧‧‧Extended pores

4‧‧‧照明裝置4‧‧‧lighting device

41‧‧‧燈罩41‧‧‧Shade

42‧‧‧光學元件42‧‧‧ Optics

43‧‧‧載體43‧‧‧ carrier

44‧‧‧照明模組44‧‧‧lighting module

45‧‧‧燈座45‧‧‧ lamp holder

46‧‧‧散熱槽46‧‧‧heat sink

47‧‧‧連結部47‧‧‧ Connection Department

48‧‧‧電連結器48‧‧‧Electric connector

4b‧‧‧光電系統4b‧‧‧Photoelectric system

49‧‧‧底板49‧‧‧ floor

49’‧‧‧控制模組49’‧‧‧control module

40’‧‧‧畫素40’‧‧‧ pixels

40b、40c‧‧‧發光元件40b, 40c‧‧‧light-emitting element

d、d’‧‧‧距離d, d’ ‧‧‧ distance

4c‧‧‧發光單元4c‧‧‧Light-emitting unit

54、56‧‧‧電性連接端54, 56‧‧‧ Electrical connection

55‧‧‧波長轉換層55‧‧‧wavelength conversion layer

57、58‧‧‧電極墊57, 58‧‧‧ electrode pads

AA’‧‧‧剖面線AA’‧‧‧ hatch

BB’、CC’‧‧‧對角線BB ’, CC’ ‧‧‧ diagonal

S1、S2、S3、S4‧‧‧側壁S1, S2, S3, S4‧‧‧ sidewall

d1、d2、d3、d4、d5‧‧‧直線距離d1, d2, d3, d4, d5‧‧‧Straight distance

W1、W2、W3、W4‧‧‧寬度W1, W2, W3, W4‧‧‧Width

第1圖繪示習知之發光裝置結構示意圖;FIG. 1 is a schematic structural diagram of a conventional light emitting device;

第2A圖繪示本發明一實施例之發光元件之上視示意圖;FIG. 2A is a schematic top view of a light emitting device according to an embodiment of the present invention; FIG.

第2B圖繪示第2A圖沿剖面線AA’之剖面示意圖;Figure 2B is a schematic sectional view of Figure 2A along the section line AA ';

第3A~3D圖繪示本發明不同實施例之發光元件之上視示意圖;3A to 3D are schematic top views of light emitting elements according to different embodiments of the present invention;

第4圖繪示本發明又一實施例之分解示意圖;FIG. 4 is a schematic exploded view of another embodiment of the present invention;

第5圖繪示本發明又一實施例之一系統示意圖;FIG. 5 is a schematic diagram of a system according to another embodiment of the present invention; FIG.

第6圖繪示本發明又一實施例之一發光單元示意圖。FIG. 6 is a schematic diagram of a light emitting unit according to another embodiment of the present invention.

Claims (10)

一發光元件,包含: 一半導體疊層具一第一側壁、一第二側壁相對於該第一側壁、一出光表面以及一接觸表面相對於該出光表面,該第一側壁與該第二側壁連接該出光表面以及該接觸表面; 一電極具有一寬度,該電極位於該出光表面上且與該第一側壁之間的直線距離不大於約50μm;以及 一絕緣層位於該接觸表面上;其中該絕緣層具有一孔隙,且從該半導體疊層之堆疊方向觀之,該孔隙與該電極之間具有一直線距離大於該寬度。A light emitting element includes: a semiconductor stack having a first side wall, a second side wall opposite to the first side wall, a light emitting surface, and a contact surface opposite to the light emitting surface, the first side wall being connected to the second side wall The light emitting surface and the contact surface; an electrode having a width, the electrode is located on the light emitting surface and a straight line distance between the electrode and the first side wall is not greater than about 50 μm; and an insulation layer is located on the contact surface; wherein the insulation The layer has a void, and viewed from the stacking direction of the semiconductor stack, a straight line distance between the void and the electrode is greater than the width. 如請求項第1項所述的發光元件,更包含一電接觸層位於該電極與該半導體疊層之間,且從該半導體疊層之堆疊方向觀之,該電接觸層與該孔隙互不重疊。The light-emitting element according to claim 1, further comprising an electrical contact layer located between the electrode and the semiconductor stack, and viewed from the stacking direction of the semiconductor stack, the electrical contact layer and the pores are mutually exclusive. overlapping. 如請求項第1項所述的發光元件,更包含一導電結構覆蓋該絕緣層之一表面且填入該孔隙中與該半導體疊層接觸。The light-emitting element according to claim 1, further comprising a conductive structure covering a surface of the insulating layer and filling the void to contact the semiconductor stack. 如請求項第1項所述的發光元件,其中該絕緣層的折射率不大於約1.4。The light-emitting element according to claim 1, wherein the refractive index of the insulating layer is not greater than about 1.4. 如請求項第1項所述的發光元件,其中,從該半導體疊層之堆疊方向觀之,該出光表面更包含一對角線,該孔隙與該電極之間的該直線距離不小於該對角線長度的約50%。The light-emitting element according to claim 1, wherein viewed from the stacking direction of the semiconductor stack, the light emitting surface further includes a diagonal line, and the straight line distance between the aperture and the electrode is not less than the pair Approximately 50% of the corner length. 如請求項第5項所述的發光元件,該孔隙包含一主孔隙與一延伸孔隙,該主孔隙的寬度不小於約20μm,該延伸孔隙的寬度不大於約20μm。According to the light emitting element in claim 5, the pore includes a main pore and an extended pore. The width of the main pore is not less than about 20 μm, and the width of the extended pore is not more than about 20 μm. 如請求項第6項所述的發光元件,其中,從該半導體疊層之堆疊方向觀之,該主孔隙與該電極位於該對角線上。The light-emitting element according to claim 6, wherein the main aperture and the electrode are located on the diagonal line when viewed from the stacking direction of the semiconductor stack. 如請求項第6項所述的發光元件,其中該電極包含一延伸電極,該延伸電極大致與該第一側壁或該第二側壁平行。The light-emitting element according to claim 6, wherein the electrode includes an extension electrode, and the extension electrode is substantially parallel to the first side wall or the second side wall. 如請求項第3項所述的發光元件,其中該導電結構包含透明導電材料。The light-emitting element according to claim 3, wherein the conductive structure includes a transparent conductive material. 一光電系統,包含: 一底板; 複數個畫素;以及 一控制模組位於該底板上且電連接該些畫素; 其中每一該畫素包含一如請求項第1項所述的發光元件。An optoelectronic system comprising: a base plate; a plurality of pixels; and a control module located on the base plate and electrically connected to the pixels; wherein each of the pixels includes a light-emitting element as described in item 1 of the claim .
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