TW202318932A - 封裝中天線裝置和製造方法 - Google Patents

封裝中天線裝置和製造方法 Download PDF

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Publication number
TW202318932A
TW202318932A TW111131323A TW111131323A TW202318932A TW 202318932 A TW202318932 A TW 202318932A TW 111131323 A TW111131323 A TW 111131323A TW 111131323 A TW111131323 A TW 111131323A TW 202318932 A TW202318932 A TW 202318932A
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Taiwan
Prior art keywords
pcb
antenna
semiconductor
semiconductor package
board
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TW111131323A
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English (en)
Inventor
李勳擇
朴慶熙
金京煥
李承炫
朴相俊
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新加坡商星科金朋私人有限公司
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Publication of TW202318932A publication Critical patent/TW202318932A/zh

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    • H—ELECTRICITY
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    • H01Q—ANTENNAS, i.e. RADIO AERIALS
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    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
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Abstract

本發明提供一種半導體裝置，其具有帶有天線之PCB及安裝至該PCB上之半導體封裝。環氧樹脂模製化合物凸塊形成或安置於與該半導體封裝相對之該PCB上方。第一屏蔽層形成於該PCB上方。第二屏蔽層形成於該半導體封裝上方。板對板（B2B）連接器安置於該PCB上或作為該半導體封裝之部分。導電凸塊安置於該半導體封裝與該PCB之間。

Description

封裝中天線裝置和製造方法
本發明一般係關於半導體裝置，且更特定言之，係關於一種封裝內天線裝置及其製造方法。
半導體裝置通常可見於現代電子產品中。半導體裝置執行廣泛範圍之功能，諸如信號處理、高速計算、傳輸及接收電磁信號、控制電子裝置、將日光變換成電及為電視顯示器建立視覺影像。半導體裝置可見於通信、功率轉換、網路、電腦、娛樂及消費型產品領域。半導體裝置亦可見於軍事應用、航空、汽車、工業控制器及辦公設備。
半導體製造之一個目標為產生較小半導體裝置。較小裝置通常消耗較少功率、具有較高效能，且可更高效地生產。另外，較小半導體裝置具有較小覆蓋面積，其為較小最終產品所需的。較小半導體晶粒大小可藉由前端製程之改良來達成，從而產生具有較小、較高密度主動及被動組件之半導體晶粒。後端製程可藉由電互連及封裝材料之改良而產生具有較小覆蓋面積之半導體裝置封裝。
近年來，將半導體系統及天線整合至一個封裝中的封裝內天線（antenna-in-package；AiP）裝置已用於行動手持機及其他可攜式多媒體裝置。然而，目前製造的AiP封裝並不足以滿足前沿蜂巢式技術所需之減小的介面間距、較高介面接腳計數、減少的厚度、緊密翹曲控制及較高層級之整合及對減少的裝置大小之普遍需要。因此，存在對經改良的AiP裝置及製造其方法之需要。
本發明的一態樣為一種製造半導體裝置之方法，其包含：提供包括天線之PCB；提供半導體封裝；及將該半導體封裝安裝至該PCB上。
本發明的所述態樣之方法進一步包括將環氧樹脂模製化合物凸塊安置於與該半導體封裝相對之該PCB上方。
本發明的所述態樣之方法進一步包括：在該PCB上方形成第一屏蔽層；及在該半導體封裝上方形成第二屏蔽層。
本發明的所述態樣之方法進一步包括將板對板(board-to-board；B2B)連接器安裝至該PCB。
在本發明的所述態樣之方法中，該半導體封裝包括板對板連接器。
本發明的所述態樣之方法進一步包括將導電凸塊安置於該半導體封裝與該PCB之間。
本發明的另一態樣為一種製造半導體裝置之方法，其包含：提供天線PCB；及將半導體封裝安置於該天線PCB上方。
本發明的所述另一態樣之方法進一步包括：將遮罩安置於該天線PCB上方；在該天線PCB及該遮罩上方形成屏蔽層；及移除該遮罩。
本發明的所述另一態樣之方法進一步包括將板對板(board-to-board；B2B)連接器安置於該天線PCB上方，其中該板對板連接器經由該天線PCB耦接至該半導體封裝。
在本發明的所述另一態樣之方法中，該半導體封裝包括一雙側SiP模組。
本發明的又一態樣為一種半導體裝置，其包含：天線PCB；及半導體封裝，其安置於該天線PCB上方。
本發明的所述又一態樣之半導體裝置進一步包括形成於該天線PCB上方之屏蔽層。
本發明的所述又一態樣之半導體裝置進一步包括安置於該天線PCB上方之板對板連接器，其中該板對板連接器經由該天線PCB耦接至該半導體封裝。
在本發明的所述又一態樣之半導體裝置中，該半導體封裝包括雙側SiP模組。
本發明的所述又一態樣之半導體裝置進一步包括安置於該天線PCB上方之凸塊，其中該凸塊包括高介電常數。
在以下描述中參考圖式於一或多個具體實例中描述本發明，在圖式中，相似編號表示相同或類似元件。儘管本發明係依據用於達成本發明目標之最佳模式來描述，但所屬領域中具通常知識者將瞭解，其意欲涵蓋如可包括如由所附申請專利範圍及如由以下揭示內容及附圖支援之其等效物所界定的本發明之精神及範圍內的替代方案、修改及等效物。如本文所使用之術語「半導體晶粒」係指詞之單數形式及複數形式兩者，並且因此，可指單個半導體裝置及多個半導體裝置兩者。
通常使用兩種複雜製造製程來製造半導體裝置：前端製造及後端製造。前端製造涉及在半導體晶圓之表面上形成複數個晶粒。晶圓上之各晶粒含有主動及被動電組件，該等電組件經電連接以形成功能性電氣電路。諸如電晶體及二極體之主動電組件具有控制電流之流動的能力。諸如電容器、電感器及電阻器之被動電組件在執行電氣電路功能所需的電壓與電流之間建立關係。
後端製造係指將成品晶圓切割或單粒化成個別半導體晶粒且封裝半導體晶粒以用於結構支撐、電互連及環境保護。為了單粒化半導體晶粒，沿著稱為鋸切道或劃線之晶圓之非功能性區域刻劃及斷裂晶圓。使用雷射切割工具或鋸片單粒化晶圓。在單粒化之後，將個別半導體晶粒安裝至封裝基板，該封裝基板包括接腳或接觸墊以用於與其他系統組件互連。接著將形成於半導體晶粒上方之接觸墊連接至封裝內之接觸件。可與導電層、凸塊、柱形凸塊、導電膏、接合線或其他適合之互連結構進行電連接。囊封物或其他模製材料沈積於封裝上方以提供實體支撐及電隔離。成品封裝接著插入至電系統中，並且使得半導體裝置之功能性可用於其他系統組件。
圖1a展示具有基座基板材料102之半導體晶圓100，諸如矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽或其他用於結構支撐之塊狀材料。複數個半導體晶粒或組件104形成於晶圓100上且由非作用、晶粒間晶圓區或鋸切道106分隔開。鋸切道106提供切割區以將半導體晶圓100單粒化成個別半導體晶粒104。在一個具體實例中，半導體晶圓100具有100毫米至450毫米（mm）之寬度或直徑。
圖1b展示半導體晶圓100之一部分的橫截面視圖。各半導體晶粒104具有背部或非作用表面108及作用表面110，該作用表面含有實施為主動裝置、被動裝置、導電層及介電層之類比或數位電路，該等介電層形成於晶粒內且根據晶粒之電設計及功能而電互連。舉例而言，電路可包括一或多個電晶體、二極體及形成於作用表面110內以實施類比電路或數位電路之其他電路元件，諸如數位信號處理器（digital signal processor；DSP）、功率放大器、特定應用積體電路（application specific integrated circuit；ASIC）、記憶體或其他信號處理電路。半導體晶粒104亦可含有諸如電感器、電容器及電阻器之IPD以用於RF信號處理。
導電層112使用PVD、CVD、電解電鍍、無電電鍍或其他適合之金屬沈積製程形成於作用表面110上方。導電層112可為鋁（Al）、銅（Cu）、錫（Sn）、鎳（Ni）、金（Au）、銀（Ag）或其他適合之導電材料之一或多個層。導電層112作為電連接至作用表面110上之電路的接觸墊操作。
使用蒸發、電解電鍍、無電電鍍、落球或網版列印製程將導電凸塊材料沈積於導電層112上方。凸塊材料可為Al、Sn、Ni、Au、Ag、鉛（Pb）、鉍（Bi）、Cu、焊料、其組合或具有視情況存在之焊劑溶液的其他適合之導電材料。舉例而言，凸塊材料可為共晶Sn/Pb、高鉛焊料或不含鉛焊料。凸塊材料使用合適附接或接合製程接合至導電層112。舉例而言，凸塊材料藉由將材料加熱超過其熔點而回焊以形成球或凸塊114。在一個具體實例中，凸塊114形成於具有潤濕層、障壁層及黏著層之凸塊下金屬化物（under bump metallization；UBM）上方。凸塊114亦可壓縮接合或熱壓縮接合至導電層112。凸塊114表示可形成於導電層112上方之一種類型之互連結構。互連結構亦可使用接合線、導電膏、柱形凸塊、微型凸塊或其他電互連件。
在圖1c中，半導體晶圓100使用鋸片或雷射切割工具118經由鋸切道106單粒化成個別半導體晶粒104。可對個別半導體晶粒104進行檢驗及電測試以用於已知良好晶粒（known-good die；KGD）後單粒化之識別。
圖2a至圖2i說明形成具有半導體晶粒104之SiP模組150。圖2a為用於製造SiP模組150的用作基座之基板152之部分橫截面圖。基板152可為自較大面板單粒化之單元基板或仍然作為較大基板面板之部分直至製造製程後期。數百或數千個封裝通常形成於單個基板面板中或具有已單粒化之單元基板的公用載體上，使用本文中針對單個單元所描述之相同步驟但整體執行。
基板152包括與一或多個導電層156交錯之一或多個絕緣層154。在一個具體實例中，絕緣層154為芯絕緣板，其中導電層156在例如覆銅層壓基板之頂部表面及底部表面上方經圖案化。導電層156亦包括經由絕緣層154電耦接之導通孔。基板152可包括在彼此上方交錯之任何數目個導電層及絕緣層。焊料遮罩或鈍化層可形成於基板152之任一側上方。在其他具體實例中，任何適合類型之基板或引線框係用於基板152。
實施SiP模組150之預期功能性的所要任何組件安裝至基板152或安置於基板上方及電連接至導電層156。基板152具有兩個主要表面：頂部表面157及底部表面159。電組件可以任何適合之組態安裝至頂部表面157及底部表面159上。圖2a展示半導體晶粒104及僅作為一個實例安裝至頂部表面157上之離散組件186。
在基板152上製造SiP模組150開始於在頂部表面157上表面安裝半導體晶粒104及離散組件186。半導體晶粒104可經選取且置放至導電層156之接觸墊上之具有凸塊114之基板152上。使用焊錫膏或另一適合之附接及連接機構安裝離散組件186（例如，電阻器、電容器、電感器、電晶體或二極體）。焊錫膏回焊於離散組件186與頂部表面157上的導電層156之接觸墊之終端之間，同時凸塊114經回焊以附接半導體晶粒104。在一些具體實例中，在半導體晶粒104與基板152之間使用黏著劑或底部填充層。
在圖2b中，使用膏列印、壓縮模製、轉移模製、液體囊封物模製、真空層壓、旋塗或其他適合之塗覆器將囊封物或模製化合物188沈積於基板152、半導體晶粒104及離散組件186上方。囊封物188可為聚合物複合材料，諸如環氧樹脂、環氧丙烯酸酯或具有或不具有填充劑之聚合物。囊封物188不導電且在環境上保護半導體裝置免受外部元件及污染物影響。囊封物188亦保護半導體晶粒104免受歸因於暴露於光而劣化影響。
在圖2c中，基板150經翻轉或以其他方式定向，使得可接近底部表面159。導電凸塊190以與導電層112上之導電凸塊114類似的方式形成或安置於導電層156之接觸墊上。圖2d展示安置於底部表面159上之輔助半導體晶粒192。半導體晶粒192在結構上類似於半導體晶粒104，但可具有不同的大小及功能性。在一個具體實例中，例如，半導體晶粒104為微處理器或微控制器積體電路（integrated circuit；IC），且半導體晶粒192為半導體晶粒104使用其傳輸及接收蜂巢式信號的第五代（fifth-generation；5G）收發器IC。半導體晶粒104及192可達到任何適合之目的。
圖2e展示以與囊封物188類似的模製製程沈積於底部表面159上方之囊封物194。囊封物194支撐且保護半導體晶粒192及安置於底部表面159上之任何其他組件。在圖2f中，囊封物194視情況使用化學蝕刻、機械研磨、使用研磨器196之化學機械平坦化（chemical-mechanical planarization；CMP）或另一適合之製程進行背磨。研磨器196移除半導體晶粒192上方之囊封物194以暴露半導體晶粒之背表面。半導體晶粒192視情況經背磨以降低半導體晶粒以及囊封物194之高度。背磨製程使得囊封物194之表面與半導體晶粒192之背表面共面。
在圖2g中，開口198形成至囊封物194中以暴露導電凸塊190。使用具有雷射199之雷射切除、機械鑽孔、化學蝕刻或另一適合之方式形成開口198。額外焊料沈積至圖2h中之開口198中且與凸塊190共同回焊以形成較大凸塊200，該等更大凸塊在囊封物194之外部表面上方延伸以使得SiP模組150之後安裝至較大電系統之PCB或基板上。
在圖2i中，SiP模組150再次經翻轉，使得凸塊200朝著載體定向且囊封物188可用於處理。導電材料濺鍍於SiP模組150上方以形成導電屏蔽層210。使用任何適合之金屬沈積技術，例如化學氣相沈積、物理氣相沈積、其他濺鍍方法、噴塗或鍍覆來形成屏蔽層210。濺鍍材料可為銅、鋼、鋁、金、其組合或任何其他適合之導電材料。在一些具體實例中，屏蔽層210可藉由濺鍍於不同材料之多個層上而製得，例如不鏽鋼-銅-不鏽鋼或鈦-銅。屏蔽層210減少SiP模組150之組件與其他鄰近電子裝置之間的電磁干擾（electromagnetic interference；EMI）。屏蔽層210視情況經由導電層156接地以改良EMI減少。
圖3a至圖3e說明形成可與SiP模組150使用以形成AiP裝置的天線PCB之製程。圖3a展示天線PCB之面板220之部分橫截面。面板220在PCB之相對側上具有兩個主要表面：底部表面221及頂部表面223。面板220之天線PCB包括視需要在PCB上及PCB中之導電層，以形成天線且將天線互連至外部裝置。典型地，在底部表面221上或僅在該底部表面內針對各單元形成天線。用於安裝SiP模組150之接觸墊形成於頂部表面223上。導通孔經由頂部表面223與底部表面221之間的天線PCB而形成，以將頂部表面223上之接觸墊電連接至底部表面221上之天線。導電墊、跡線、通孔及任何其他適合之結構可視需要形成於面板220中或面板上。
凸塊224形成於底部表面221上。凸塊224由環氧樹脂模製化合物（epoxy molding compound；EMC）或其他聚合物材料形成。在一些具體實例中選擇具有高介電常數之材料以減少對底層天線之影響。使用模製或列印製程在面板220上形成凸塊224。在其他具體實例中，凸塊224單獨地形成且接著安裝至面板220。
在圖3b中，面板220翻轉至載體225上，其中頂部表面223遠離載體定向。遮蔽膜或帶226層壓至面板220上。使用雷射切割工具228、水切割工具、鋸片或圖3c中的其他適合之機構將具有遮蔽帶226之面板220單粒化成個別天線PCB 230。在圖3d中，屏蔽層240藉由濺鍍或另一適合之方法（例如，用於屏蔽層210之上文所描述的彼等方法）而形成於天線PCB 230上方。在圖3e中移除遮蔽帶226以及遮蔽帶上之屏蔽層240之部分，以僅在天線PCB之側表面上留下具有屏蔽層240之天線PCB 230屏蔽層240視情況存在。在一些具體實例中，在塗覆凸塊224之後面板220立即單粒化成天線PCB 230。若屏蔽層240並非所要，則不執行圖3b、圖3d及圖3e之步驟。
圖3e中之天線PCB 230完成且準備好整合至AiP裝置中。圖4說明具有天線PCB 230及SiP模組150之AiP裝置250。為了開始整合，自載體225、自卷軸帶或自另一類型之儲存媒體取下及置放天線PCB 230，且置放於載體252上。載體252包括用於一或多個AiP裝置250在一起製造的開口253。開口253比凸塊224之組合覆蓋面積更寬，使得凸塊之所有擬合在開口內，而天線PCB 230之周長放置於開口外部的載體252上。在其他具體實例中，AiP裝置250經形成而具有保留於載體225上之天線PCB 230。
SiP模組150及板對板連接器254安裝至頂部表面223上。導電層256說明為形成於頂部表面223上或該頂部表面下，且包括用於安裝SiP模組150、B2B連接器254及任何其他所要組件之接觸墊。焊料凸塊200回焊至導電層256上以將SiP模組150機械地及電耦接至天線PCB 230。B2B連接器254用於將帶狀纜線或另一類型之電管道附接至AiP裝置250，以允許其他封裝與半導體晶粒104及192通信且利用該等半導體晶粒之功能性。SiP模組150經由導電層256連接至B2B連接器254。SiP模組150為可安裝於天線PCB 230上之一個例示性半導體封裝。任何所要半導體封裝可與B2B連接器254一起安裝至天線PCB 230上。
天線260說明為藉由導電層形成於底部表面221上或該底部表面中。天線260可為任何適合類型之天線，諸如微帶天線、平面倒F形天線、開槽波導天線、近場通信（near-field communication；NFC）天線、碎形天線等。在一些具體實例中，多個及可能不同類型之天線形成於單個天線PCB 230上。導通孔262經由天線PCB 230而形成，以將SiP模組150互連至天線260。半導體晶粒104、半導體晶粒192或兩者經由導通孔262、凸塊200及基板152電連接至天線260。
在一個具體實例中，除天線260及SiP模組150與天線之間的導電路徑之外，天線PCB 230不包括其他電組件。所有系統功能由SiP模組150內之組件執行，且天線PCB僅用於容納一天線以廣播及接收電磁輻射。SiP模組150直接安置於天線260上方之天線PCB 230上。
天線260形成為天線PCB 230之部分，與含有半導體晶粒104及其他系統組件之SiP模組150分隔開。AiP 250之單獨形成且接著堆疊的封裝組件使得較高介面接腳計數，減少的各單獨結構的厚度，緊密的翹曲控制及較高層級之整合成為可能。歸因於先前技術中之單個系統加天線基板上之層壓層之數目減小，製造良率得到改良。減少的基板厚度改良翹曲特性。儘管天線260形成於單獨的基板上，但AiP 250維持與先前技術中使用之結構相同或更佳的效能，例如迴轉時間特性。
圖5a至圖5e說明替代性SiP模組具體實例。圖5a展示藉由將半導體晶粒104及離散組件186安置於頂部表面357上而形成於基板352上的SiP模組350，類似於上文SiP模組150之形成。半導體晶粒192在另一橫截面中可安置於頂部表面357上，在後續步驟中安置於底部表面359上或不使用。
圖5b展示沈積於基板352、半導體晶粒104及離散組件186上方之囊封物388。藉由使用遮罩或藉由在沈積之後蝕刻或研磨掉囊封物，頂部表面357之部分仍不具有囊封物388。導電層356之部分仍暴露於囊封物外部的頂部表面357上，以用於後續電互連。
在圖5c中，類似於上文屏蔽層210而形成屏蔽層390。頂部表面357之仍自囊封物388暴露的部分亦仍自屏蔽層390暴露，使得電組件可安置於其上且電連接至導電層356。在屏蔽層390之濺鍍期間使用遮罩或蓋板以阻止直接在未沈積囊封物388之基板352上形成屏蔽層。移除遮罩或蓋板以使頂部表面357之部分暴露。
在圖5d中，B2B連接器392安置於基板352之暴露部分上。在圖5e中，凸塊394安置於底部表面359上，以用於後續連接至天線PCB。圖6展示安裝於天線PCB 230上以形成AiP裝置396之SiP模組350。類似於上文AiP裝置250，半導體晶粒104經由導通孔262、導電層256、凸塊394、導電層356及凸塊114耦接至天線260。在一些具體實例中，一或多個離散組件186亦串聯耦接於半導體晶粒104與天線260之間。AiP裝置396具有AiP裝置250之所有益處。B2B連接器392安置於基板352上，而非AiP裝置250中之天線PCB 230上。SiP模組350僅為包括可用於天線PCB 230之B2B連接器的半導體封裝之一個實例。可使用半導體封裝之任何適合之拓樸，包括諸如SiP模組150之雙側封裝。
圖7說明將上文所描述之AiP裝置（例如，AiP裝置396）併入至電子裝置400中。電子裝置400包括具有安裝於PCB之表面上之複數個半導體封裝（包括AiP裝置396）的PCB 402。具有連接器410之帶狀纜線412插入至B2B連接器392中，以將另一裝置電耦接至AiP裝置396中之組件。連接器410經組態以與B2B連接器392介接，使得帶狀纜線412可經由帶狀纜線將電信號傳導至AiP裝置396及自該AiP裝置傳導電信號。帶狀纜線412可用於將AiP裝置396連接至PCB 402、PCB 402上之另一封裝、相同或不同電子裝置之另一PCB、另一PCB上之另一封裝、另一電子裝置、測試設備等。可使用其他類型之纜線或導體（諸如同軸纜線或雙扭線纜線）而非帶狀纜線。帶狀纜線412經由基板152連接至半導體晶粒104及離散組件186。
取決於應用，電子裝置400可具有一種類型之半導體封裝或多種類型之半導體封裝。電子裝置400可為使用半導體封裝以執行一或多個電功能之獨立系統。替代地，電子裝置400可為較大系統之子組件。舉例而言，電子裝置400可為平板電腦、蜂巢式電話、數位相機、通信系統或其他電子裝置之部分。電子裝置400亦可為圖形卡、網路介面卡或插入至電腦中之另一信號處理卡。半導體封裝可包括微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散主動或被動裝置或其他半導體晶粒或電組件。
在圖7中，PCB 402提供通用基板以用於安裝於PCB上之半導體封裝的結構支撐及電互連。使用蒸發、電解電鍍、無電電鍍、網版列印或其他適合之金屬沈積製程於PCB 402之表面上方或層內形成導電信號跡線404。信號跡線404提供半導體封裝、安裝組件及其他外部系統或組件之間的電通信。跡線404亦視需要將電源連接及接地連接提供至半導體封裝。
在一些具體實例中，半導體裝置具有兩個封裝層級。第一層級封裝為用於將半導體晶粒機械地且電附接至中間基板之技術。第二層級封裝涉及將中間基板機械地且電附接至PCB 402。在其他具體實例中，半導體裝置可僅具有第一層級封裝，其中晶粒直接機械地且電安裝至PCB 402。
出於說明之目的，包括接合線封裝446及覆晶晶片448之若干類型之第一層級封裝展示於PCB 402上。另外，包括球狀柵格陣列（ball grid array；BGA）450、凸塊晶片載體（bump chip carrier；BCC）452、平台柵格陣列（land grid array；LGA）456、多晶片模組（multi-chip module；MCM）458、四邊扁平無引線（quad flat non-leaded；QFN）封裝460、四邊扁平封裝462及嵌入式晶圓級球狀柵格陣列（embedded wafer level ball grid array；eWLB）464之若干類型之第二層級封裝經展示為連同AiP裝置396一起安裝於PCB 402上。導電跡線404將安置於PCB 402上之各種封裝及組件彼此電耦接。
視系統要求而定，經組態具有第一及第二層級封裝式樣以及其他電子組件之任何組合的半導體封裝之任何組合可連接至PCB 402。在一些具體實例中，電子裝置400包括單個附接之半導體封裝，而其他具體實例需要多個互連之封裝。藉由在單個基板上方組合一或多個半導體封裝，製造商可將預製組件併入至電子裝置及系統中。由於半導體封裝包括複雜功能性，因此可使用較不昂貴的組件及流線型的製造製程來製造電子裝置。所得裝置不大可能發生故障且製造起來較不昂貴，從而降低消費者成本。
儘管已詳細說明本發明之一或多個具體實例，但熟習此項技術者將瞭解，可在不脫離如以下申請專利範圍表中所闡述之本發明之範圍的情況下對彼等具體實例進行修改及調適。
100:半導體晶圓 102:基座基板材料 104:半導體晶粒 106:鋸切道 108:背部或非作用表面 110:作用表面 112:導電層 114:凸塊 118:雷射切割工具 150:SiP模組 152:基板 154:絕緣層 156:導電層 157:頂部表面 159:底部表面 186:離散組件 188:囊封物 190:導電凸塊 192:輔助半導體晶粒 194:囊封物 196:研磨器 198:開口 199:雷射 200:更大凸塊 210:導電屏蔽層 220:面板 221:底部表面 223:頂部表面 224:凸塊 225:載體 226:遮蔽帶 228:雷射切割工具 230:天線PCB 240:屏蔽層 250:AiP裝置 252:載體 253:開口 254:板對板連接器 256:導電層 260:天線 262:導通孔 350:SiP模組 352:基板 356:導電層 357:頂部表面 359:底部表面 388:囊封物 390:屏蔽層 392:B2B連接器 394:凸塊 396:AiP裝置 400:電子裝置 402:PCB 404:導電信號跡線 410:連接器 412:帶狀纜線 446:接合線封裝 448:覆晶晶片 450:球狀柵格陣列 452:凸塊晶片載體 456:平台柵格陣列 458:多晶片模組 460:四邊扁平無引線封裝 462:四邊扁平封裝 464:嵌入式晶圓級球狀柵格陣列
[圖1a]至[圖1c]說明具有由鋸切道分隔開的複數個半導體晶粒之半導體晶圓； [圖2a]至[圖2i]說明形成用於AiP裝置中之SiP模組； [圖3a]至[圖3e]說明形成用於AiP裝置中之天線PCB； [圖4]說明將SiP模組及天線PCB組合至AiP裝置中； [圖5a]至[圖5e]說明第二SiP模組具體實例； [圖6]說明具有第二SiP模組具體實例之AiP裝置；且 [圖7]說明將AiP裝置整合至電子裝置中。
104:半導體晶粒
108:背部或非作用表面
110:作用表面
114:凸塊
150:SiP模組
152:基板
154:絕緣層
156:導電層
157:頂部表面
159:底部表面
186:離散組件
188:囊封物
190:導電凸塊
192:輔助半導體晶粒
194:囊封物
198:開口
200:更大凸塊
210:導電屏蔽層

Claims (15)

  1. 一種製造半導體裝置之方法，其包含： 提供包括天線之PCB； 提供半導體封裝；及 將該半導體封裝安裝至該PCB上。
  2. 如請求項1之方法，其進一步包括將環氧樹脂模製化合物凸塊安置於與該半導體封裝相對之該PCB上方。
  3. 如請求項1之方法，其進一步包括： 在該PCB上方形成第一屏蔽層；及 在該半導體封裝上方形成第二屏蔽層。
  4. 如請求項1之方法，其進一步包括將板對板連接器安裝至該PCB。
  5. 如請求項1之方法，其中該半導體封裝包括板對板連接器。
  6. 如請求項1之方法，其進一步包括將導電凸塊安置於該半導體封裝與該PCB之間。
  7. 一種製造半導體裝置之方法，其包含： 提供天線PCB；及 將半導體封裝安置於該天線PCB上方。
  8. 如請求項7之方法，其進一步包括： 將遮罩安置於該天線PCB上方； 在該天線PCB及該遮罩上方形成屏蔽層；及 移除該遮罩。
  9. 如請求項7之方法，其進一步包括將板對板連接器安置於該天線PCB上方，其中該板對板連接器經由該天線PCB耦接至該半導體封裝。
  10. 如請求項7之方法，其中該半導體封裝包括一雙側SiP模組。
  11. 一種半導體裝置，其包含： 天線PCB；及 半導體封裝，其安置於該天線PCB上方。
  12. 如請求項11之半導體裝置，其進一步包括形成於該天線PCB上方之屏蔽層。
  13. 如請求項11之半導體裝置，其進一步包括安置於該天線PCB上方之板對板連接器，其中該板對板連接器經由該天線PCB耦接至該半導體封裝。
  14. 如請求項11之半導體裝置，其中該半導體封裝包括雙側SiP模組。
  15. 如請求項11之半導體裝置，其進一步包括安置於該天線PCB上方之凸塊，其中該凸塊包括高介電常數。
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